JPH0812602B2 - Information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that employs a pipeline processing method.

[Conventional technology]

In general, an information processing apparatus adopting a pipeline processing system operates so that stages of instruction processing such as instruction reading, instruction decoding, operand reading, and instruction execution overlap and progress between consecutive instructions. . Therefore, the subsequent instruction read may precede the execution of the preceding store instruction. If the preceding store instruction modifies an area of memory and a subsequent instruction read has already read the instruction from that area and fetched the instruction into the instruction buffer, a conflict occurs between the memory and the instruction buffer.

Therefore, the conventional information processing apparatus of this type invalidates the instruction buffer and rereads the instruction when the instruction fetched in the instruction buffer is changed in the memory. However, if there is a branch instruction before the changed instruction and the branch succeeds, invalidating the instruction buffer and re-reading the instruction causes the new read instruction to not be used, resulting in performance degradation. As a conventional technique for preventing such performance deterioration, for example, JP-A-60-7724
The technology described in Japanese Patent Publication No. 1 etc. is known.

In this type of conventional technology, when it is detected that the instruction fetched in the instruction buffer is changed in the memory (this is called the first detection), the result is held and the reading of the subsequent instruction is suppressed. However, the operation of the instruction operates so as to continue.
And when trying to execute an instruction in the arithmetic unit,
The stored detection result detects whether or not the instruction has been modified in memory (this is called the second detection), and if it has, it suppresses the execution of the operation unit and invalidates the instruction buffer. And the instruction reading after the changed instruction is redone.

Further, the information processing apparatus according to the above-mentioned conventional technology is provided with an arithmetic unit capable of processing a large number of instructions and a general-purpose register IGPR in a unit for performing pipeline processing, and these are provided independently of the execution of the arithmetic unit. By operating in synchronism with decoding, the speed of the determination of branch instructions and the processing in the case where the registers referred to between the instructions conflict with each other are speeded up, and this is generally called a preceding operation.

For example, L (Load) instruction and A (Add) instruction are consecutive,
If the general register GGPR different from the general register written by the L instruction and the general register GGPR used by the A instruction for operand address calculation have the same number, L
If the operand address of the A instruction was calculated after the instruction was executed in the arithmetic unit and the execution result was written in GGPR, the pipeline would be greatly disturbed and the performance would be degraded. Therefore, by independently writing the operand of the L instruction to the IGPR and calculating the operand address of the A instruction using the IGPR, the disturbance of the pipeline can be suppressed.

In the information processing device having such a preceding arithmetic unit and IGPR, when the above-mentioned mismatch between the memory and the instruction buffer occurs, the execution of the arithmetic unit is suppressed and the IG
If the contents of PR and GGPR do not match, the operation of the subsequent instruction will be inconsistent, so it is necessary to guarantee the match of IGPR and GGPR. Therefore, in the above-mentioned conventional technique, the first detection is performed by, for example, executing the store instruction in the arithmetic unit and issuing the store request, the instruction taken in the store address and the instruction buffer. It is done by comparing with the address of.

In the second detection, for example, when the instruction is fetched from the execution wait queue and is about to be executed by the arithmetic unit, the instruction address of the instruction is obtained in synchronization with the first detection in advance.
It is performed by comparing with the address of the instruction changed on the memory held by the result of the detection.

[Problems to be solved by the invention]

The above-mentioned conventional technique has a problem that the first and second detections are performed in synchronization with the execution stage in the operation unit, and therefore the preceding operation using the general-purpose register IGPR cannot be suppressed by these detection results. . For example, when the store instruction modifies the immediately following instruction, since the first detection is performed in the execution stage of the store instruction, the processing of the modified instruction is started including the preceding operation.
This preceding calculation cannot be suppressed.

Further, in the above-mentioned conventional technique, even if the first detection is performed sufficiently early, the second detection is also performed in the instruction execution stage in the same manner. Therefore, as a result of the second detection, the instruction is changed in the memory. However, even if it is recognized that the preceding operation of the instruction cannot be suppressed. Therefore, when the instruction changed in memory writes to a general-purpose register, the operation unit does not write to GGPR because its execution is suppressed, but the preceding operation is not suppressed and writing to IGPR does not occur. It was done, GGPR and IG
Contradiction occurs in the contents of PR. Therefore, in the above-mentioned conventional technique, in such a case, when the result of the second detection recognizes that the instruction is changed in the memory, the content of IGPR is returned to the content before the execution of the preceding operation of the instruction. , From GGPR
Copying is performed on the IGPR, and there is a problem that it is difficult to improve the performance because of a lot of labor required for the copying.

An object of the present invention is to solve the above-mentioned problems of the prior art, and when an instruction fetched by an instruction buffer is changed in memory by a preceding store instruction, the preceding operation is suppressed in the processing of the instruction, and the IGPR By ensuring that the contents of IGPR and GGPR do not match, the overhead of processing when the contents of the above memory and instruction buffer do not match is reduced, and processing due to false detection is also performed. It is to provide a high-performance information processing device in which the above-mentioned overhead does not occur.

[Means for solving problems]

According to the invention, the object is achieved by performing the first and second detections in synchronism with the preceding operation.
When the first detection is viewed from the store instruction that modifies the subsequent instruction, the detection target is the instruction that is performed after the store instruction is read from the memory and before the store operation is completed in the arithmetic unit. Since this is a read operation, in the present invention, the first detection is the detection from the reading of the store instruction to the decoding (this is called the 1-Ath detection).
And detection from the decoding of the store instruction to the end of the store operation (this is called 1-B detection).

[Action]

The 1-Ath detection can be performed by comparing the store address with the address of the instruction fetched into the instruction buffer when the store instruction is decoded.

The 1-Bth detection holds the store address until the store operation is completed after the store instruction is decoded,
This can be done by comparing the read address and the stored store address (there may be a plurality of stored addresses) when an instruction read request is issued.

According to the 1-A-th and 1-B-th detection results, the store address of the store instruction that changes the subsequent instruction is held in association with the instruction buffer.

The second detection can be performed by obtaining the address of the instruction in synchronization with the decoding of the instruction and comparing it with the stored store address.

From the result of the second detection, it can be recognized that the instruction is changed in the memory, the preceding operation can be suppressed, and the writing to the IGPR can be prevented.

Further, the result of the second detection is held as a flag in association with the execution-waiting instruction queue, and when the instruction is fetched from the queue and is to be executed in the arithmetic unit, the instruction changes it on the memory. Therefore, it is possible to suppress the execution of the operation unit, invalidate the instruction buffer, and redo the instruction read from the changed instruction.

〔Example〕

An embodiment of an information processing apparatus according to the present invention will be described below in detail with reference to the drawings.

1 is an embodiment of the present invention and is a block diagram showing only the portion related to the present invention, FIG. 2 is a block diagram showing the details of the detection circuit 1 in FIG. 1, and FIG. 3 is a detection circuit in FIG. 2 is a block diagram showing the details of FIG. 2, FIG.
FIG. 4 is a detailed block diagram of the address comparison circuit in FIG. 3. 1 to 4, 1 and 2 are detection circuits and 3,4 and 1
4 to 17, 24, 30, 31 are address comparison circuits, 5 is an OR gate, 6
Is KYU, 7-9,22,27-29,36 is selector, 10,11,20,2
1,25,26,34,35 are registers, 12,13 are adders, 18,19,32,3
3,39 are AND gates, and 23 is store queuing.

One embodiment of the information processing apparatus according to the present invention detects, as shown in FIG. 1, that the instruction fetched by the instruction buffer is changed in the memory and carries out the first detection for holding the result. Two detection circuits 1 and 2 to be performed, and two address comparison circuits 3 and 4 for performing a second detection for detecting whether or not the instruction is changed in the memory when the instruction is executed in the arithmetic unit. And an OR gate that performs the logical sum of the results of these comparison circuits 3 and 4, a queue 6 that corresponds to the queued execution instruction that holds the output, and an operation unit to be executed from this queue 6. The selector 7 selects an element corresponding to the instruction.

Next, the operation of the embodiment shown in FIG. 1 configured as described above will be described.

When the preceding store instruction is decoded and the start / end address (SSA / SEA) of the store instruction is obtained, the first
The detection circuit 1, which is a circuit for detecting -A, compares the start / end address of the succeeding instruction that has already been taken into the instruction buffer with the start / end address (SSA / SEA) of the store instruction. As a result, when it is detected that the preceding store instruction modifies the succeeding instruction, the detection circuit 1 internally holds the store address and outputs it to the address comparison circuit 3.

When an instruction read request is issued by a subsequent instruction and the start / end address (iSA / iEA) of instruction read is calculated,
The detection circuit 2, which is a circuit for performing the 1-B detection, stores the start / end address of a store instruction being executed or waiting for execution and the start / end address of the instruction read (iS
A / iEA). As a result, when it is detected that the instruction to be read is changed by the preceding store instruction, the store address is held in the detection circuit 2 even after the end of the store operation. The detection circuit 2 outputs the store address of the store instruction being executed or waiting for execution and the held address.

The instruction is decoded and the instruction start / end address (DS
A / DEA), the address comparison circuit 3 compares the store address held by the detection result of the detection circuit 1 with the start / end address (DSA / DEA) of the instruction. The address comparison circuit 4 also compares the store address held by the detection result of the detection circuit 2 and the store address of a store instruction being executed or waiting with the start / end address (DSA / DEA) of the instruction. To do. The outputs of the address comparison circuits 3 and 4 are ORed by the OR gate 5,
It is detected whether the decoded instruction has been modified in memory by the preceding store instruction. If it is changed, the output of the OR gate 5 inhibits the preceding operation of the decoded instruction and prevents the general register IGPR from being written. The output of the OR gate 5 is stored in the queue 6 corresponding to the queued instruction queue. When trying to execute an instruction in the arithmetic unit,
When the selector 7 selects the detection result and recognizes that the instruction is changed in the memory, the execution of the operation unit is suppressed, the instruction buffer is invalidated, and the read operation after the changed instruction is performed. Start over.

In the detailed diagram of the detection circuit 1 shown in FIG.
8 and 9 select the instruction address side when the instruction buffer is activated, and select the outputs of the adders 12 and 13 at other times. Registers 10 and 11 are the start / end addresses (iBSA * / iBEA *, * = 0,1) of the instruction fetched in the instruction buffer.
Is a register for storing There are two sets of instruction buffers, one stores the subsequent instruction sequence of the instruction being executed,
The other stores the branch destination instruction sequence of the branch instruction. Adder
12 and 13 increase the start address of the register 10 or 11 corresponding to each instruction by the instruction length each time the instruction is fetched from the instruction buffer and decoded. The address comparison circuits 14 and 16 compare the store address of the store instruction with the address of the instruction fetched by the instruction buffer.
In the address comparison circuits 15 and 17, the start address of the store is
It is compared whether it is smaller than the first address held in the registers 20 and 21. Registers 20 and 21 are registers that hold the store address of a store instruction that changes the instruction in each instruction buffer, and the selector 22 selects the currently decoded instruction buffer side.

 The operation of the detection circuit 1 shown in FIG. 2 will be described below.

When an instruction read request is issued and the start / end address (iSA / iEA) is requested, if the instruction read newly activates the instruction buffer, both the start / end address (iSA / iEA) are Otherwise, the end address (i
EA) is held in the register 10 or 11 in response to the instruction buffer that issued the instruction read request.

When the store instruction is decoded and the start / end address (SSA / SEA) to store is determined, the address comparison circuit 1
Reference numerals 4 and 16 compare the address held in the registers 10 and 11 with the start / end address (SSA / SEA) to be stored to detect whether or not the store instruction modifies the instruction in each instruction buffer. . In addition, the address comparison circuit 15,1
7 detects whether or not the start address (SSA) of the store is smaller than the start address held in the registers 20 and 21. At this time, the address comparison circuit outputs true when the address is not held in the registers 20 and 21. AND
By ANDing these comparison results at gates 18 and 19,
When the store instruction changes the instruction in the instruction buffer with an address smaller than the address already held,
The store address is held in the registers 20 and 21.

In general, instructions are executed in order from the smallest address, so if the start address of the store is smaller than the address already held in registers 20,21, register 20,2
It is necessary to store the smaller store address in registers 20 and 21 in preference to the store address in 1.
The address comparison processing as described above is performed.

The store address held in the registers 20 and 21 is selected and output by the selector 22 on the side of the instruction buffer currently being decoded.

In the detailed diagram of the detection circuit 2 shown in FIG.
The queue 23 holds the store address of the store instruction being executed or awaiting execution until the store operation is completed. The address comparison circuit 24 compares the start / end address (SQSA / SQEA) of the store held in the store queue with the instruction read address (iSA / iEA), and the registers 25 and 26:
The result of the address comparison circuit 24 is held in correspondence with the instruction buffer from which the instruction is read. Selector 27,28,29
Selects the detection result or store address of the store instruction for which the store operation has ended. Address comparison circuit 30, 31
Indicates that the start address of the output of the selector 29 is
It is detected whether it is smaller than the start address of 5. Registers 34 and 35 hold the store address of the store instruction that modifies the subsequent instruction after the store operation is completed, and the selector 36
Selects the side corresponding to the currently decoded instruction buffer from the addresses held in the registers 34 and 35.

 Next, the operation of the detection circuit 2 shown in FIG. 3 will be described.

When the store instruction is decoded and the start / end address (SSA / SEA) to store is found, the start / end address to store
The end address (SSA / SEA) is held in the store queue 23 until the store operation is completed.

When an instruction read request is issued and the start / end address (iSA / iEA) of instruction read is found, the address comparison circuit 24
Is the store address held in the store queue 23 and the start / end address of the instruction read (iSA / iEA)
Compare with. As a result, it is detected that the instruction to be read is modified by the preceding store instruction held in the store queue 23. The detection result is held in the register buffer 25, 26 corresponding to the store queue 23 on the side of the instruction buffer where the instruction read is issued.

When the operation of the store instruction is completed, the selector 27,28,29
Corresponds to the detection result and the store
Select an address. The address comparison circuits 30 and 31 detect whether or not the start address of the output of the selector 29 is smaller than the start address held in the registers 34 and 35. At this time, the address comparison circuits 30 and 31 output true if the addresses are not held in the registers 34 and 35. AND gate 3
2, 33 ANDs the comparison result of the address comparison circuit 24 held in the registers 25, 26 with the comparison result of the address comparison circuits 30, 31, so that the store instruction is stored in the registers 34, 35. When changing the instruction in the instruction buffer with an address smaller than the held address, the store address is held in the registers 34 and 35. The store address held in the registers 34 and 35 is the selector 36
As a result, the currently decoded instruction buffer side is selected and output.

The address comparison circuit 3 in FIGS. 1 to 3 described above,
4,14,16,24 are two large and small comparators as shown in FIG.
It is composed of 37, 38 and an AND gate 39.

The comparator 37 detects that the end address of the store is larger than the start address of the instruction, and the comparator 38 detects that the start address of the store is smaller than the end address of the instruction. Then, the AND gate 39 ANDs these detection results.
By doing so, a detection signal indicating that the store instruction stores to the instruction address is output.

As described above, according to the embodiment of the present invention, when the store instruction is decoded, the change of the subsequent instruction is detected (first
The first means for detecting A), when an instruction read request is issued,
Second means for detecting a change in an instruction to be read by a store instruction which is being executed or is being executed (detection of 1-B), and registers 20, 21 for holding a store address of a store instruction for changing a subsequent instruction Third means provided in the first and second means by 34 and 35, fourth means and fourth means by address comparison circuits 3 and 4 which detect that the instruction is changed when the instruction is decoded. 6 that holds the detection results of the means
According to the fifth means of the above, by this, when the instruction fetched in the instruction buffer is changed by the preceding store instruction, the preceding operation is suppressed,
It is possible to guarantee that the contents of IGPR and GGPR match.

〔The invention's effect〕

As described above, according to the present invention, when the instruction fetched by the instruction buffer is changed on the memory by the preceding store instruction, the preceding operation of the changed instruction is suppressed and the IGPR is executed. Can be prevented from being written. As a result, it is not necessary to copy GGPR to IGPR, and the processing in the above case can be performed simply and quickly.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, a block diagram showing only a portion relating to the present invention, FIG. 2 is a block diagram showing details of the detection circuit 1 in FIG. 1, and FIG. 3 is a detection diagram in FIG. The block diagram showing the details of the circuit 2 is shown in FIG.
FIG. 4 is a detailed block diagram of the address comparison circuit in FIG. 3. 1,2 …… Detection circuit, 3,4,14 to 17,24,30,31 …… Address comparison circuit, 5 …… OR gate, 6 …… Kew, 7 ～ 9,22,27
~ 29,36 …… Selector, 10,11,20,21,25,26,34,35 …… Register, 12,13 …… Adder, 18,19,32,33,39 …… AND gate, 23 …… Store Kyu, 37,38 …… Comparison between large and small.

Claims (1)

[Claims] 1. An information processing apparatus of a pipeline processing system in which instruction processing is divided into several stages and a plurality of instructions are processed simultaneously, and a large number of instructions are operated in a unit for controlling the pipeline. In the information processing device, the store instruction is decoded in the unit capable of processing the above-mentioned general-purpose register and the general-purpose register IGPR, and in the unit capable of processing the operations of all the instructions. Means for detecting whether or not the subsequent instruction already fetched to the instruction buffer is changed by the store instruction, and when the instruction read request is issued, the preceding executing or waiting execution Second means for detecting whether or not the instruction to be read is changed by the store instruction of the above, and a subsequent instruction is changed according to the detection results of the first and second means. The store address of the A instruction,
A third means provided in the first and second means for holding associated with the instruction buffer; an address of the instruction when the instruction is decoded and a store associated with the instruction buffer. Fourth means for detecting that the instruction is changed by the preceding store instruction by comparing the address, and holding the detection result of the fourth means as information associated with the execution wait instruction queue And means for suppressing the preceding operation of the unit for controlling the pipeline according to the detection result by the fourth means,
When not writing to the general-purpose register IGPR, and when the instruction is fetched from the queue,
When it is recognized that the instruction has been changed by the information attached to the instruction queue stored in the means, the execution of the arithmetic unit is suppressed, the instruction buffer is invalidated, and the instruction after the changed instruction is read. An information processing apparatus, characterized in that