JPH0812697B2 - Pattern defect inspection system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a defect inspection apparatus using a pattern recognition technique, and more particularly to an inspection object having a geometrical bright and dark pattern formed based on design information ( For example, an inspected image information generating means for imaging a mask or reticle for manufacturing a semiconductor integrated circuit and outputting inspected image information corresponding to the pattern, and a form capable of comparing the design information with the inspected image information. Pattern defect inspection having reference image information generating means for processing the processed image information and outputting as reference image information, and inspection means for comparing the inspected image information and the reference image information and detecting the defect of the pattern from the result. Regarding the device.

[Conventional technology]

A conventional device of this type is disclosed in, for example, Japanese Patent Laid-Open No. 58-134429. In this apparatus, information (bending state, position) representing the bending characteristics of the boundary line (edge) that separates the light and dark of the pattern is extracted from each of the inspection image information and the reference image information, and both image information are extracted. A method of determining that the pattern to be inspected has a defect when the feature information of the same edge is not included is adopted.

[Problems to be solved by the invention]

By the way, although a defect can be repaired after inspection, the cost required for it is proportional to the number of defects and the size of each defect. However, since only the edge feature information is obtained as defect information from the above conventional apparatus, the size of each defect cannot be known even if the number of defects can be detected. Therefore, it is impossible to accurately calculate the cost required to correct the defect in advance.

An object of the present invention is to provide a pattern defect inspection apparatus capable of detecting the size of a defect and accurately calculating the cost required for repairing the defect.

[Means for solving problems]

In order to achieve this object, the pattern defect inspection apparatus of the present invention has the following configuration.

An inspected image information generating means (ID, which inspects an inspected object having an inspected pattern formed based on design information, and outputs inspected image information corresponding to the inspected pattern
BN), reference image information generating means (OM, DF) for processing the design information in a form comparable to the inspected image information and outputting it as reference image information, the inspected image information and the reference image information And an inspection unit (IP) for detecting a defect of the pattern to be inspected from the result of the comparison with the inspection unit (IP), wherein the inspection unit (IP) is a direct comparison unit (IPa) and a feature extraction unit (IPb). The direct comparison means (IPa) excludes the vicinity of the edge of the pattern to be inspected from the object of the comparison as a forbidden zone, and the presence / absence of defects existing in other portions. And the size of the defect and output it as the first defect information, and the feature extraction apparatus (IPb) detects the presence or absence of a defect in the entire pattern to be inspected, including the defect in the forbidden band. Outputting as second defect information, When both the defect information are received and both the first defect information and the second defect information are output from the respective means (that is, the direct comparing means and the feature extracting means simultaneously detect the defects at the same location of the pattern). If detected, only the first defect information is output, the second defect information is not output, and only the first defect information is output from the means (that is, the defect is detected only by the direct comparison means). If the defect is detected, only the first defect information is output, the first defect information is not output, and only the second defect information is output from the means (that is, the defect is detected only by the feature extracting means). In the case of), only the second defect information is output, and if neither the first defect information nor the second defect information is output, nothing is output.

The direct comparison means preferably includes a size determination means, and the size determination means has various directions of a detected defect (in the later examples, directions of 0 degree, 45 degrees, 90 degrees, 135 degrees).
Compare the sizes of, select the largest of them and output.

[Action]

The first defect information including the defect size information obtained from the direct comparison means (IPa) can be obtained as the defect information of the pattern to be inspected. If it cannot be obtained, the defect size cannot be detected but prohibited. It is possible to obtain the second defect information obtained from the feature extracting means capable of detecting the true defect in the band. As a result, normally, the position and size information of the defect can be known from the first defect information, and when the first defect information cannot be obtained, the position of the true defect existing in the forbidden zone can be obtained from the second defect information. It is something you can know.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the entire pattern defect inspection apparatus according to the present invention. In the figure, an inspected object WK such as a reticle and a mask having an inspected pattern formed based on design information is placed on the moving stage ST. The inspected pattern existing in a small area that is a part of the entire inspected pattern is an imaging device ID including a one-dimensional image sensor.
Is imaged by. This imaging is obtained by the stage apparatus ST moving the inspected object WK in one direction, and the imaging apparatus ID reading and scanning perpendicularly to the moving direction. Imaging device
The analog image information obtained from the ID is output to the binarization circuit BN. The binarization circuit BN samples the analog image information 512 times per scanning line of the image pickup device ID, binarizes the level of the sampled analog image information, and obtains the binary image information as the inspected image information. This inspected image information is time-series image data processed in units of 512 × N (N is a numerical value that changes depending on the moving distance of the moving stage, the scanning interval of the image pickup device, etc.), and each pixel (bit) is It becomes a logic "1" (a portion where the pattern is formed by chrome) or a logic "0" (a portion where the pattern is not formed). This inspected image information is output to the inspection circuit IP.

On the other hand, the computer CP stores the reference image information corresponding to the small area of the pattern to be inspected captured by the image capturing apparatus ID in the external storage
Read from OM and output to pattern transformation circuit DF. The transformation circuit DF adds processing to the reference image information from the computer CP,
The reference pattern represented by the reference image information is enlarged or reduced to correspond to the pattern to be inspected, and the processed reference image information is sent to the inspection circuit IP.

The inspection circuit IP compares the inspected image information and the reference image information, which are input in time series in a state of being synchronized with each other,
If there is a difference that should be regarded as a defect in the patterns indicated by both image information, the defect information is output to the computer CP. The computer CP sends this defect information to the external storage device OM to be stored therein and also displayed on the display device VD including the CRT.

The computer CP controls each part in order to properly carry out the defect inspection.

FIG. 3 is a block diagram showing the configuration of the inspection circuit IP. The inspection circuit IP is a direct comparison circuit IPa and a feature extraction circuit IPb.
Composed of and. Direct comparison circuit IPa and feature extraction circuit IPb
Means that both the reference image information from the transforming circuit DF and the inspected image information from the binarizing circuit BN are received, and both image information are compared by different processing methods to perform a defect inspection. As a result, The defect information is sent to the computer CP of FIG. 2 as the first defect information and the second defect information, respectively. calculator
The CP edits both pieces of defect information, stores them in the external storage device OM, and displays them on the display device VD including the CRT.

FIG. 1 is a block diagram showing the configuration of the direct comparison circuit IPa. The reference image information and the inspected image information, which are input in time series to the direct comparison circuit IPa, are the cutout circuits IPa1 and IPa.
Input to a2 respectively.

As shown in FIG. 4, the extraction circuit IPa1 is a 512-bit serial input / serial output type shift register SRa1, SRa2, ...
, SRa8 and 9-bit serial input / parallel output type shift registers SRb0, SRb1, SRb2 ,.

The input terminal of the shift register SRa1 receives the reference image information from the transformation circuit DF, and the output terminal is connected to the input terminal of the shift register SRa2. The output terminal of the shift register SRa2 is connected to the input terminal of the shift register SRa3 (not shown). Since the above connection method is repeated up to the shift register SRa8, the reference image information is expanded into 512 × 8 bits (pixels) in the shift registers SRa1 to SRa8.
Since the number of bits of one scanning line in the image pickup device ID is 512 bits, which is the same as that of each shift register SRa1 to SRa8, reference image information delayed by one scanning line is stored in each shift register SRa1 to SRa8.

The input terminal of the shift register SRb0 receives the reference image information from the transformation circuit DF, and the input terminal of the shift register SRb1 is connected to the output terminal of the shift register SRa1. Similarly, the input terminal of the shift register SRb2 is connected to the output terminal of the shift register SRa2. Since the same connection is made for the shift registers SRb3 to SRb8, the shift register SRb0
In SRb8, the reference image information is expanded into 9 × 9 pixels. Therefore, the 9 × 9 pixel reference image information shifted in the shift registers SRb0 to SRb8 is visualized and expressed as follows. For example, a processing unit of 64 × 64 pixels (which will be described later in detail, of the defects detected in this processing unit, the largest one is recorded in the external storage device OM as the defect of this processing unit, and Displayed in VD)
Observe the reference image information developed in the above through a window of a smaller size of 9 × 9 pixels, and move this window one pixel at a time in the scanning line direction, and every time one scanning line (512 pixels) is moved, This means returning to the scanning line of and repeating the above movement. Shift register SRb0 to SR
Since b8 can output in parallel, it is possible to output the reference image information of 9 × 9 pixels at the same time.

The cutout circuit Ipa2 has the same configuration except that the input is the image information to be inspected from the binarization circuit BN.

FIG. 5 is a schematic view showing a window of 9 × 9 pixels by the cutout circuits IPa1 and IPa2. In order to specify a certain pixel among these by coordinates, numbers 1 to 9 are assigned in the horizontal direction (scanning line direction) and alphabets A to I are assigned in the vertical direction. For example, the pixel in the upper left corner is specified by coordinates (1, A), the pixel in the center is specified by (5, E), and the pixel in the lower right corner is specified by (9, I).

Of the 9 × 9 pixel reference image information and the inspected image information extracted by the extraction circuits IPa1 and IPa2, the coordinates (5, E)
The reference image information and the inspected image information which are input to the pixel of are input to both input terminals of the exclusive OR circuit IPa3, respectively. The exclusive OR circuit IPa3 outputs a logic "1" when both input information do not match, that is, when the pattern to be inspected is defective, and a logic "0" when they match.

Also, 9x cut out by the cutout circuits IPa1 and IPa2
Of the 9-pixel reference image information and the inspected image information, the reference image information and the inspected image information, which are input to 69 pixels denoted by the numbers in FIG.
Input to IPa9 and IPa10 in parallel. Both forbidden band creation circuits IPa9, IPa10 are
Logic array), and in FIG.
All the information of the pixels with "" is logical "1" or logical "0"
, The first output of the logic “1” is added, and when the information of the pixels with and is all the logic “1” or the logic “0”, the second output of the logic “1” is added, and. When the information of all the pixels is "1" or "0", the third output of "1" is output, and the information of the pixels with and are all "1" or "0". Occasionally each produces a fourth output of logic "1". Further, both forbidden band generating circuits IPa9, IPa10 receive the selection control signal output from the computer CP of FIG. 2 and selectively output the first, second, third and fourth outputs. .

The output of the exclusive OR circuit IPa3, which indicates whether or not the information input to the pixel at coordinates (5, E) does not match, is output to one input terminal of the AND circuit IPa11 and one input terminal of the AND circuit IPa12. Are input respectively.

The output of the forbidden band creating circuit IPa9 is sent to the other input terminal of the AND circuit IPa11, and the output of the forbidden band creating circuit IPa10 is sent to the other input terminal of the AND circuit IPa12.

Forbidden band creation circuits IPa9, IPa10 and AND circuit IPa
11 and IPa12 are circuits prepared as countermeasures against pseudo defects. In the vicinity of the edge indicated by the inspected image information, when the imaged information of the inspected pattern is binarized, unevenness due to a binarization error (quantization error) inevitably occurs, and even this unevenness is erroneously determined as a defect. Sometimes. There is also a problem that an erroneous determination may occur due to an alignment error between the reference pattern and the pattern to be inspected (a synchronization shift between the reference image information and the image to be inspected). The defects detected by these erroneous determinations are generally called pseudo defects. Therefore, in order to deal with this pseudo defect, forbidden band creation circuits IPa9, IPa10,
The AND circuits Ipa11 and Ipa12 prohibit the defect detection in the vicinity of the edge, and by the selection by the data selector,
It is possible to set how many pixels of the forbidden band are provided from the edge.
When the first output is selected, a forbidden band for one pixel per one side of the edge is selected, when the second output is selected, a forbidden band for two pixels for one side of the edge is selected, and the third output is selected. In this case, a forbidden band for three pixels is set for one side of the edge, and a forbidden band for four pixels is set for one side of the edge when the fourth output is selected. The size of the forbidden band is determined in consideration of the size of the pseudo defect (which is known in advance by how much the binarization error and the alignment error are allowed).

The output terminals of both AND circuits IPa11 and IPa12 are OR circuits IP
Connected to both a13 input terminals.

The output of the OR circuit IPa13, which is information indicating the presence or absence of a defect, is sent to the cutout circuit IPa4. The cutout circuit IPa4 has the same configuration as the cutout circuits IPa1 and IPa2. A part of the information developed in the 9 × 9 pixel serial input / parallel output type shift register is input to the size determination circuit IPa5.

The direction-based size determination circuit IPa5 sets the defect size to 0 °,
Measure at 45 °, 90 ° and 135 °. In order to measure the size in the 0 ° direction, the hatched coordinates (2, E), (3, E), ... in the schematic diagram shown in FIG.
Information of 7 pixels of (8, E) (size judgment information for 0 °)
In order to measure the size in the direction of 135 °, the coordinates (2,
B), (3, C), (4, D), (5, E), (6, F), (7, G),
Information of 7 pixels of (8, H) (135 ° size judgment information)
Is used to measure the size in the 90 ° direction,
Coordinates (5,
B), (5, C), ..., (5, H) 7 pixel information (90 ° size determination information) is used to measure the size in the 45 ° direction. , The hatched coordinates (2, H), (3, G), (4, F), (5,
Information on seven pixels (E), (6, D), (7, C), and (8, B) (45 ° size determination information) is used. The size determination circuit IPa5 for each direction individually outputs the size determination result in each direction.

The maximum size determination circuit IPa6 obtains the size determination result in each direction, determines the maximum size among them, and outputs information on the size and direction.

FIG. 10 is a block diagram showing the configurations of the direction size determination circuit IPa5 and the maximum size determination circuit IPa6.

In the figure, each of the size determination circuits PL1, PL2, PL3, PL4 for 0 °, 45 °, 90 °, and 135 ° is composed of a PLD (programmable logic device).
Each of the size determination circuits PL1 to PL4 receives each size determination information which is a 7-bit parallel input, and generates a 3-bit parallel output corresponding to the size. Taking the 0 ° size determination circuit PL1 as an example, the circuit PL1 has the coordinates (2, E), (3, E), ..., (8,
In response to the 7-bit 0 ° size determination information input from the pixel E), the information from the pixel at coordinates (4, E), (5, E), and (6, E) is logical "1". , And if the information from the other pixels is logical “0”, 3-bit information indicating that the size is 3 pixels (for example, “01
1 ”) is output from the three output terminals. Each size determination circuit has information indicating that the size of the defect is 0 to 6 pixels,
A total of eight types of size information, including information indicating that the number of pixels is 7 pixels or more, can be output.

The maximum size determination circuit IPa6 is composed of three PROMs (Programmable Read Only Memory) PR1, PR2, PR3. The PROM PR1 receives 8 bits of size information from the 0 ° and 45 ° size determination circuits PL1 and PL2 and 2-bit size determination inhibition information from the size determination inhibition circuit IPa7, which will be described later. Receive on the address line.
Then, the same PROM PR1 outputs the size information of the larger size from the three data lines. However, when the size determination of one size information is prohibited by the size determination prohibition information, the other size information is output from the data line. In addition, indicate which size information was selected 1
Output from the data line of the book. PROM PR2 has 6-bit information from 90 ° and 135 ° size judgment circuits PL3 and PL4.
The 8-bit address lines receive 2-bit size determination inhibition information from the size determination inhibition circuit IPa7, which will be described later, as an input. Then, the same PROM PR2 outputs the size information of the larger size from the three data lines. When the size determination of one size information is prohibited by the size determination prohibition information, the other size information is output from the data line. At the same time, which size information is selected is output from one data line. PROM PR3 is the previous PROM PR
1, Receives 8-bit parallel output from PR2 on 8 address lines, sends maximum size information indicating larger size to computer CP of FIG. 2 with 3 data lines, and determines which maximum size information Direction information indicating whether or not the size corresponds to the direction is output from the two data lines to the computer CP. In addition, PR
The OM PR1, PR2, and PR3 are set to output the size in either direction when the sizes indicated by the size information in both directions are equal.

Returning to FIG. 1, the size determination prohibiting circuit IPa7 is composed of an edge detecting circuit ED and an enlarging circuit EL, as shown in FIG.

The edge detection circuit ED receives the pixel information of the eight coordinates with (1) to (8) in FIG. 12 from the cutout circuit IPa1, and determines the presence / absence of an edge and the direction of the edge, if any. It is detected and information indicating that is output. That is, (1)
All of the 4-bit information of (4) to (4) are logical "1" and all the 4-bit information of (5) to (8) are logical "0", or vice versa, that is, (1 ) ~ (4)
All 4-bit information is logical "0", and (5)
When all of the 4-bit information of (8) to (8) are logic "1", it is determined that the reference image information represents an edge of 0 °, and (8), (1) to (3). If the 4-bit information of is all logic "1" and all the 4-bit information of (4) to (7) is logic "0", or vice versa, the reference image It is judged that the information expresses an edge of 45 °, and the 4-bit information of (7), (8), (1), and (2) is all logical "1", and (3)-
If all the 4-bit information in (6) is logic "0" or the reverse logic, it is determined that the reference image information represents an edge of 90 °, and (6)- (8),
When the 4-bit information of (1) is all logic "1" and the 4-bit information of (2) to (5) is all logic "0", or vice versa. Judges that the reference image information represents an edge of 135 °, and sends a 4-bit parallel output corresponding to four directions to the enlarging circuit EL as edge detection information.

As shown in FIG. 13, the expansion circuit EL includes four serial input / serial output type shift registers SRc1 having 512 bits.
.About.SRc4, an OR circuit OR1, a 4-bit serial input / parallel output type shift register SRd, and an OR circuit OR2.

The input terminal of the shift register SRc1 receives 1 bit of the 4-bit edge detection information, and its output terminal is connected to the input terminal of the shift register SRc2. Shift register
The output terminal of SRc2 is connected to the input terminal of shift register SRc3 (not shown). The above connection method is shift register SRc4
Since it is repeated up to, shift registers SRc1 to SRc4
Then, the reference image information is expanded into 512 × 4 bits (pixels). Since the number of bits of one scanning line in the image pickup device ID is 512 bits, which is the same as that of each shift register SRc1 to SRc4, each shift register SRc1 to SRc4 stores edge detection information delayed by one scanning line.

The OR circuit OR1 has five input terminals, and receives the 1-bit edge detection information input to the shift register SRc1 and the outputs of the shift registers SRc1 to SRc4. OR circuit OR
The output of 1 is sent to the input terminal of the shift register SRd.

The OR circuit OR2 has five input terminals, and the OR circuit OR1
And the output of each bit of the shift register SRd. Therefore, the output of the OR circuit OR2 expands the 1-bit edge detection signal to 5 × 5 pixels.

Enlargement circuit EL consists of shift registers SRc1 to SRc4, OR circuit
Since there are four sets of circuits including the OR1, the shift register SRd, and the OR circuit OR2 corresponding to the four-direction edge detection information, the output thereof is also a 4-bit parallel output.
This parallel output is divided into 2 bits corresponding to the 0 ° and 45 ° edges and 2 bits corresponding to the 90 ° and 135 ° edges, and the PROM described in FIG. It is sent to the data lines of PR1 and PR2 respectively. Further, this 4-bit size determination prohibition information is used in the latter stage in order to use it as information indicating in which direction near the edge the defect indicated by the information is detected when the maximum size information is output from the maximum size determination circuit IPa6. Calculator
Sent to CP.

In FIG. 1, the timing adjustment circuit IPa8 has a center coordinate (5, 5
Upon receiving the pixel information in E), the output timing is delayed so as to match the output timing of the maximum size determination circuit IPa6. When the determination circuit IPa6 outputs the maximum size information indicating the maximum size of the defect and the direction information indicating the direction of the defect, the delay output indicates that the defect is logic "0",
Since it can be used as information for discriminating which of "1", that is, whether the pattern has a white defect that should not be present or a black defect that should be present, it is sent to the computer CP as black and white discrimination information.

FIG. 14 and FIG. 15 are schematic diagrams showing the patterning of the defect inspection process of the direct comparison circuit IPa.

An example of the feature extraction circuit IPb shown in FIG.
A circuit of the system disclosed in Japanese Patent Laid-Open No. -134429 is adopted.
This circuit, when detecting that the edge of the pattern to be inspected is bent at a predetermined step from the image information to be inspected, inspects whether the information corresponding to this step is included in the reference image information, If it is not included, defect information is generated.

 The operation of this embodiment will be described below.

In FIG. 2, the inspection pattern on the inspection object WK is
An image is taken by the imaging device ID as the moving stage ST moves. The analog image information obtained from the imaging device ID is 2
The inspected image information is binarized by the binarization circuit BN, and a portion with a pattern has a logic “1” and a portion without a pattern has a logic “0”, and is output to the inspection circuit IP.

The computer CP reads the reference image information corresponding to the pattern to be inspected picked up by the image pickup device ID from the external storage device OM and outputs it to the pattern transformation circuit DF. The transformation circuit DF enlarges or reduces the reference pattern represented by the reference image information so as to correspond to the pattern to be inspected, and then sends it to the inspection circuit IP.

The inspection circuit IP compares the inspected image information and the reference image information, which are input in time series in a state of being synchronized with each other,
If there is a difference that should be regarded as a defect in the patterns indicated by both image information, the defect information is output to the computer CP. The computer CP sends this defect information to the external storage device OM to be stored therein and displayed on the display device VD. More specifically, the third
In the figure, the direct comparison circuit IPa and the feature extraction circuit IPb which form the inspection circuit IP receive both the reference image information from the transformation circuit DF and the inspected image information from the binarization circuit BN, and have different processing methods. Then, defect inspection is performed by comparing the two image information, and the first defect information and the second defect information are sent to the computer CP of FIG. The computer CP edits both defect information and sends them to the external storage device OM and the display device VD. This editing method will be described later.

In FIG. 1, the reference image information and the inspected image information that are time-sequentially input to the direct comparison circuit IPa are input to the cutout circuits IPa1 and IPa2, respectively, and are developed into 9 × 9 pixels. Of the 9 × 9 pixel reference image information and the inspected image information, the information input to the center pixel of the coordinate (5, E) is
The exclusive OR circuit IPa3 is inputted to the exclusive OR circuit IPa3, and the exclusive OR circuit IPa3 has a logic "1" when both input information do not match, that is, a pattern to be inspected has a defect, and a logic "0" when they match. Is sent to one of the input terminals of the AND circuits IPa11 and IPa12.

FIGS. 14 (a) and 14 (b) show a state in which the reference image information and the inspected image information input to the inspection circuit IP in time series are developed in a processing unit of 64 × 64 pixels and patterned. Shows. FIG. 6C shows a state in which the output of the exclusive OR circuit IPa3 is expanded in the same processing unit. FIG.
The reference pattern PTr corresponding to the reference image information (shown by hatching) and the inspection pattern PTi corresponding to the inspection image information in FIG.
The portion that does not overlap is extracted as a defect pattern PTd1 (hatched in the figure) in FIG. 7C, which corresponds to the output of the exclusive OR circuit IPa3.

Of the 9 × 9 pixel reference image information and the inspected image information extracted by the extraction circuits IPa1 and IPa2, FIG.
The reference image information and the inspected image information that are input to the 69 pixels marked with are the prohibited band creation circuit IPa9,
Input to IPa10 in parallel. It is assumed that the both forbidden band generating circuits IPa9 and IPa10 have the third output selected by the selection control signal output from the computer CP of FIG. 2 at this time. The third output from the forbidden band generating circuits IPa9 and IPa10 is shown in FIG. 17 when all of the information of the pixels marked with, is logic "1" or logic "0", that is, when the edge is not detected. Only, send the output of logic "1" to the other input terminal of AND circuits IPa11, IPa12,
The defect detection is made possible, and a portion up to a total of 6 pixels by 3 pixels centering on the edge is a forbidden band, and 6 points centering on the edges of the reference pattern Pr and the inspected pattern Pi.
Defect detection in the pixel area is prohibited.

The output terminals of both AND circuits IPa11 and IPa12 are OR circuits IP
Connected to both a13 input terminals.

14 (d) and 14 (e) are forbidden band creation circuits IPa9 and IPa1.
The output of 0, the output of the OR circuit IPa13 is 64 × 64 in FIG.
Each of the patterns is developed and patterned for each pixel processing unit. In the same figure (d), the forbidden band PHr provided around the edge of the pattern PTr is hatched, and in the same figure (e), the forbidden band PHi provided around the edge of the pattern PTi is hatched. Indicated by.

The forbidden band PHr of FIG. 7D and the defect pattern PTd1 of FIG. 7C are overlapped and the non-overlapping portions are extracted in the portion shown by upward hatching in FIG. The forbidden band PHi in FIG. 6 (e) and the defect pattern PTd1 in FIG. 6 (c) are overlapped with each other, and the non-overlapping portions are extracted in the part shown by hatching in the lower right of FIG. 6 (f). The defect pattern PTd2 shown by hatching in FIG. This corresponds to the output of the OR circuit IPa13.

By configuring the logic circuit like the AND circuits IPa11, IPa12 and the OR circuit IPa13, the accuracy of defect detection is improved. For example, this logic circuit is effective for detecting so-called isolated defects that are located away from the edge and whose size is hidden in the forbidden band. If this isolated defect is a so-called black defect that should exist where there is no pattern, since it appears as a pattern only in the pattern to be inspected, it can be detected as a defect pattern from the output of the exclusive OR circuit IPa3. This defect pattern is buried in the forbidden band formed by the forbidden band creating circuit IPa10 based on
The defect pattern output cannot be obtained from 2. However, since no black defect appears in the reference pattern, the defect pattern is not buried in the forbidden band created by the forbidden band creating circuit 9 based on the reference pattern.
Can output the defect pattern. On the other hand, in the case of a so-called white defect where the isolated defect does not exist where the pattern should be, it can be detected as a defect pattern from the output of the exclusive OR circuit IPa3 because it appears as a pattern only in the reference pattern. On the basis of this, the defect pattern is buried in the forbidden band formed by the forbidden band forming circuit IPa9, and the output of the defect pattern cannot be obtained from the AND circuit IPa11. However, since white defects do not appear in the inspected pattern, this defect pattern is not buried in the forbidden band created by the forbidden band creating circuit 10 based on the inspected pattern. You can get the output of

An OR circuit IP that is information indicating the presence or absence of the defect pattern PTd2
The output of a13 is sent to the cutout circuit IPa4. Cutting circuit IPa4
Has the same configuration as the cutout circuits IPa1 and IPa2. A part of the information developed in the 9 × 9 pixel serial input / parallel output type shift register is input to the size determination circuit IPa5.

Each of the size determination circuits PL1 to PL4 (Fig. 10) that constitutes the direction-dependent size determination circuit IPa5 has 0 °, 45 °, 90 °, and 135 ° hatched in Figs. 6 to 9. Receive the size judgment information for each direction from the cutout circuit IPa4,
It is assumed that size information indicating that there are 7 pixels or more in the 0 ° direction, 4 pixels in the 45 ° direction, 5 pixels in the 90 ° direction, and 4 pixels in the 135 ° direction is output. Then, the maximum size determination circuit
IPa6 PROM PR1 is 0 °, 45 ° size determination circuit PL1,
The size information of 7 pixels or more and the size information of 4 pixels are received from PL2 from a total of 6 address lines. At that time, if information indicating that the size judgment in either direction is not prohibited is received from the size judgment prohibition circuit IPa7 from the two address lines, the same PROM PR1 is used to input the contents of the memory cell specified by the input of the address line. Is read from the 4-bit data line. The content thereof is preset so as to indicate that the size of the defect is 7 pixels or more and the direction thereof is 0 °.

On the other hand, PROM PR2 is a size judgment circuit PL for 90 ° and 135 °.
3, PL4 receives the size information of 5 pixels and the size information of 4 pixels from a total of 6 address lines. This time,
If the size judgment prohibition information that prohibits the size judgment in the 90 ° direction from the size judgment prohibition circuit IPa7 is received from two address lines, the same PROM PR2 will be read from the memory cell specified by the input of the address line. Defect size is 4
Information indicating that the direction of the pixel is 135 ° is transmitted from the data line.

As described above, the process of removing the size in the direction parallel to the edge from the comparison target is effective when the inspection object WK is a mask, a reticle, or the like. A defect having a large protrusion amount in the direction orthogonal to the edge is in contact with an adjacent pattern to form a bridge when the defect is a black defect, or conversely causes a disconnection when the defect is a white defect. This means that the size having a component in the direction orthogonal to the edge should be more important than the size in the direction parallel to the edge. Therefore, in this embodiment, the size in the direction parallel to the edge is ignored, and the importance of the size having the component orthogonal to the edge is relatively increased.

The PROM PR3 receives a total of 8 bits of parallel output from the previous PROM PR1 and PR2 on eight address lines, and the defect size is 7 pixels or more from the memory cell specified by the input of the address line, and its direction is 0 °. The information indicating that is output to the computer CP from the five data lines.

In FIG. 1 and FIG. 11, the edge detection circuit ED is
Pixel information of eight coordinates with (1) to (8) in the figure is received from the cutout circuit IPa1, and (7), (8), (1), (2)
All 4-bit information is logical "1", and (3)
Whether all the 4-bit information of (6) is logical "0",
Or if the reverse logic is applied, the reference image information is
It is determined that the 90 ° edge is represented, and the bit of the third digit in the 4-bit parallel output is set to logic "1" and the remaining 3 bits are set to logic "0". The 4-bit edge detection information indicates that an edge exists and its direction is 90 °.

The magnifying circuit EL shows that there was a 90 ° edge 4
The bit edge detection information is enlarged to 5 × 5 pixels and sent to the PROM PR2 described in FIG. 10 as size determination prohibition information. The PROM PR2 receives this edge detection information and excludes the size in the 90 ° direction from the comparison target.

FIGS. 15 (a) to 15 (d) are schematic diagrams when the edge detection of the reference pattern PTr of FIG. 14 (a) and the enlargement of the result are performed. The figure (a) shows the detection enlargement of the 0 ° edge, the figure (b) shows the detection enlargement of the edge of 45 °, the figure (c) shows the detection enlargement of the edge of 90 °, and the figure (d). Is 135
The detection and enlargement of the edge of ° are shown respectively, and the size judgment is prohibited at the hatched portions.

The computer CP has defect information consisting of maximum size information and direction information from the maximum size determination circuit IPa6, size determination inhibition information from the expansion circuit EL, black and white determination information from the timing adjustment circuit IPa8, and defect information from the feature extraction circuit IPb. Then, the following processing is performed.

i. The maximum size information is sequentially input to the computer CP, and the maximum size among the processing units of 64 × 64 pixels is set as the defect size of the processing unit. As signal processing for that purpose, each time new size information is input, it is compared with the old size information that was previously input and stored in the memory, and if the new size information is larger, the contents of the memory are Update. This processing is performed within the range of the processing unit, and the finally remaining size information is regarded as a defect of the processing unit, and the coordinates of the processing unit (this can be known by counting sampling pulses of the image pickup device, for example), External size information such as defect size information and direction information, black-and-white judgment information and size judgment prohibition information when the defect is detected
It is recorded in OM or displayed on the display device VD.
In the CRT of the display device VD, for example, the entire screen is configured with 512 × 512 pixels, the reference pattern and the inspected pattern are displayed in an overlapping manner, and the defective processing unit is a frame with a size of 64 × 64 pixels. It is preferable to perform image processing such as displaying the type of the defect in a frame while displaying the defect in. A technique therefor is disclosed in JP-A-59-77576. The defect type refers to, for example, an edge defect close to the edge, an isolated defect separated from the edge, or the like. This is a computer CP
However, if the size determination prohibition information is present, it is determined to be an edge defect, and if not, it is determined to be an isolated defect separated from the edge.

ii. Direct comparison circuit IPa cannot detect a defect in the processing unit,
When the first defect information is not obtained, the computer CP takes in the second defect information from the feature extraction circuit IPb, records it in the external recording device OM, and displays it on the CRT or the like. That is, when there is the first defect information, the computer CP treats the first defect information as priority over the second defect information, treats the first defect information as the defect information of the entire inspection apparatus (third defect information), and When there is no defect information, it functions as an editing unit that handles the second defect information as the third defect information. In the direct comparison circuit IPa, a forbidden band is provided in the vicinity of the edge in order to eliminate a pseudo defect, and the defect detection in the forbidden band is prohibited. Therefore, there is a possibility that even a true defect existing in the forbidden zone may be overlooked. However, although the feature extraction circuit IPb cannot detect the size of the defect, it can detect the presence or absence of the defect existing in the entire pattern to be inspected, including the defect in the forbidden band which the direct comparison circuit IPa misses. Accuracy is guaranteed.

Other editing methods include, for example, the following. When the size indicated by the first defect information is determined and it is indicated that the defect is a predetermined size (for example, 2 pixels) or less, the second defect information is output as the third defect information.

As a method of using the defect direction information, there is a determination of the defect type. For example, as shown in FIG. 16, when an isolated defect Di is continuously sandwiched between two edge defects De1 and De2 and the directions of the defects are the same, each defect is a white defect. In this case, the computer CP can judge that it is a disconnection defect and a black defect is a bridge defect.

Next, a feature extraction circuit IPb having a novel configuration different from that disclosed in Japanese Patent Laid-Open No. 58-134429 will be described with reference to FIGS. 18 to 36.

The feature extraction circuit described below is characterized by being configured by the following three elements.

i. Inspected edge information generating means (7) which detects the edge of the pattern from the inspected image information and outputs the inspected edge information regarding the angle and position thereof. ii. The pattern is ideal based on the design information. From the reference image information when the edge is formed in the
Reference edge information generating means (18) for outputting reference edge information regarding the angle and position of the edge, iii. Receiving the inspected edge information and the reference edge information,
Defect information generating means (8, 9, 11, for detecting defect information that the other edge information does not exist within an allowable range defined based on the angle and position of the edge indicated by the one edge information and generating defect information). 19-21) And, the action is summarized as follows.

The reference edge information from the reference edge information generating means (18) and the inspected edge information from the inspected edge information generating means (7) are compared by the defect information generating means (8, 9, 11, 19 to 21). At this time, assuming that the reference edge information is given an allowable range, the defect determination is as follows: Although the content of the inspected edge information indicates the position (x, y) and the angle θ °. On the other hand, the reference edge information is (x ± Δx, y ± Δ
If the angle does not fall within the angle range of θ ° ± Δθ ° in the position range of y), it is determined as a defect. The content of this defect is (x ± Δx, while the edge of the angle θ ° is detected in the pattern to be inspected of the inspected object WK at the position (x, y).
That is, no edge having an angle within the angle range of θ ° ± Δθ ° was detected in the reference image information within the position range of y ± Δy).

 Hereinafter, the novel feature extraction circuit IPb will be described in detail.

 FIG. 18 is a block diagram of the feature extraction circuit IPb.

The inspected image information from the binarization circuit BN is output to the cutout circuit 6.

The cutout circuit 6 is the cutout circuits IPa1 and IPa2 shown in FIGS. 1 and 4.
It performs the same function as, but the specific structure is different as shown in FIG. In the figure, 601 is binary input image information, 602 is a timing signal, 603 is a control circuit, 604 is a data rearrangement circuit, 611 to 615 are three-state buffers, and 621 to 625 are at least 51 respectively.
Random access memories (RAM) having a storage capacity of 2 addresses × 4 bits, 631 to 635 are 5-bit shift registers. If the image information of 512 pixels corresponding to one scanning line of the image pickup device ID is called one line, the input image information
Digital image information of 512 pixels × N lines is input as 601.

When the first line (line 1) is input, the control circuit 603 turns on the three-state buffer 611.
(A signal is supplied to the data bus of the memory 621), 612 to 615 are turned off (a signal is not passed, the output has a high impedance, and a signal is not supplied to the data bus of the memories 622 to 625), Write to the memory 621. By this operation, the image information of 512 pixels of line 1 of the input image information 601 is written in each address of the memory 621, but the memory 621 simultaneously outputs the same signal as the input image information to the rearrangement circuit 604.

Next, while the line 2 is being input, the control circuit 603 turns on the three-state buffer 612, 611, 613-
615 is turned off, and the image information of line 2 is written in the memory 622. At the same time, the memory 621 reads out the previously written image information of line 1 and rearranges it.
Further, the memory 622 outputs the same information as the image information of the input line 2 to the rearrangement circuit 604. In this way, by changing the memory for each line one after another and writing the image information and setting the memory which is not in the writing state to the reading state, when the input image 601 is the line 5, the memory 621 reads the image information of the line 1. The memory 622 reads the image information of line 2, the memory 623 reads the image information of line 3, the memory 624 reads the image information of line 4, and the memory 625 writes the image information of line 5. And in the rearrangement circuit 604,
Five pieces of image information from the same signal as the input image information 601 (0 line delay) to a signal obtained by delaying the same signal 601 by 4 lines (4 line delay) are input. When the image information of the next line 6 is input, the memory to be written is stored in the memory 621.
, The rearrangement circuit 604 also delays 0 line delay to 4 line delay from the input image information 601 at that time by 5 lines.
The image information of the book is input. By continuing such an operation, the reordering circuit 604 is always input with five pieces of image information with 0 line delay to 4 line delay with respect to the input image information 601. However, it is not constant which signal is delayed by which line among the five inputs, and the input image information 60
It changes every time 1 is input for 1 line.

The data rearrangement circuit 604 is composed of a PLD, and switches a terminal output from these five input signals each time image information for one line is input by a control signal from the control circuit 603, and shift registers 631 to 631 to The image information output to 635 is always image information with 0 line delay to 4 line delay.

The control circuit 603 receives the timing signal 602 such as the sampling clock (hereinafter referred to as a basic clock) of the image pickup device ID, and controls the ON / OFF of the three-state buffers 611 to 615 and the memories 621 to 62 as described above.
5 address control, write / read control, and rearrangement circuit 604 control.

The shift registers 631 to 635 are 5-bit serial input / parallel output type shift registers, and shift input image information as a data input by one pixel (1 bit) in synchronization with a clock input. Each shift register 63
The signals set in the stages 1 to 635 are simultaneously output in parallel. Thus, the inspected image information (output signals from the shift registers 631 to 635) of the window having the 5 × 5 pixel configuration is obtained.

FIG. 20 is a schematic diagram showing the structure of a 5 × 5 window. As shown in FIG. 20, the inspected image information of the window includes numbers 1 to 5 in the scanning line direction of the imaging device ID, that is, in the horizontal direction. However, numbers from A to E are added in the vertical direction, and by designating this number, it is possible to designate a specific pixel of the inspected image information of the window.

In the inspected image information of the window output by the cut-out circuit 6 of this embodiment, the window data required by the edge image creating circuit 7 in the subsequent stage is 3 × 3 pixels, so that 1 in the horizontal direction in FIG. ~ 3,
By using A to C in the vertical direction, the structure shown in the conceptual diagram of FIG. 21 is obtained. In this case, the three-state buffers 614, 615,
Although the memories 624 and 625 and the shift registers 634 and 635 are unnecessary, respectively, in the present embodiment, the cutout circuits 6 and 8 of FIG.
Since 17 and 19 (8, 17, and 19 will be described later) are configured by sharing the memory portion, among them, the memories 624 and 625 are included.
Is not omitted and is left as it is.

The actual output of the cutout circuit 6 is 9 pixels corresponding to each pixel.
Bits are output in parallel.

The memories 621 to 625 have 512 bytes and a word length of 4 bits (512
Since it is a memory of (× 4 bits), the circuit of 605 in FIG. 19 can function as four cutting circuits. In other words, a 4-bit signal can be simultaneously output in parallel by reading one address.
Buffers 611 to 615, rearrangement circuit 604, shift register 6
Three sets of circuits similar to 31 to 635 are added, and 4-bit (4 types) signals are written in the memories 621 to 625 in parallel and read in parallel. Individual cutting circuits 6, 8, 17, 19 can be made.

The inspected image information of the window output from the cutout circuit 6 in the form of parallel output of 9 bits is input to the inspected edge image forming circuit 7. The edge image forming circuit 7 is shown in FIG.
Using the template as shown in (d), the inspected edge information is created by extracting the contour of the inspected image information. That is, the logic "1" is arranged at the center of the 3 × 3 bits, and the logic "0" is arranged at any one of the upper, lower, left and right sides thereof (a) in FIG.
If the four templates of (d) and the image information to be inspected from the cutout circuit 6 are associated with each other and a portion having the same arrangement as at least one template is found, it is determined that the template condition is satisfied. In other words, if there is a logic "1" in the center and there is a logic "0" on either the top, bottom, left, or right, it is determined that the condition of the template is satisfied and the logic "1" is established.
When no template condition is satisfied, a logic "0" is output. As a result, the inspected edge information obtained from the edge image creating circuit 7 is a logic "1" at the contour portion of the pattern (a logic "1" portion in contact with the logic "0") included in the inspected image information. And becomes logic "0" in the other parts.

The output form of the inspected edge image forming circuit 7 is
It is a time series signal output from one line.

The inspected edge information created by the inspected edge image creation circuit 7 is cut out by the cutout circuit 8 into a local region of 5 × 5 pixels and sent to the inspected edge angle detection circuit 9. As described above, the cutting circuit 8 is configured similarly to the cutting circuit 6,
Create window edge information as shown in Figure 20. However, 5x
Since there are 5 pixels, shift registers 634 and 635 are required.
The actual output of the cutout circuit 8 becomes a 25-bit parallel output corresponding to each pixel and is sent to the inspected edge angle detection circuit 9.

The inspected edge angle detection circuit 9 applies the template of FIGS. 23 to 33 in which the logic “1” is arranged in various forms to the edge information of the window based on the inspected image information,
A 4-bit inspected edge angle signal corresponding to 0 °, 45 °, 90 ° and 135 ° is created. That is, in order to detect four kinds of angles, a template group that is divided into four groups as shown in Table 1 is applied to the edge information of the window, and if the condition of at least one template in the template group is satisfied, That is, when the inspected edge information having the logic "1" of the same array as the logic "1" of the template is detected, it is determined that the edge of the angle corresponding to the template group to which the template belongs is present, An edge angle signal in which a logic "1" is set in the bit corresponding to the angle is generated and sent to the comparison circuit 11 described later. This edge angle signal is a 4-bit parallel output.

This edge angle detection processing is performed for all edges of various angles in the pattern of the inspection object by 0 °, 45 °, 90 °.
This is equivalent to rounding as an edge with four kinds of angles of ° and 135 °. For example, at the 22.5 ° edge, 0 ° or
Edge angle signals of 45 ° or both are output. That is, the array of each template is selected and grouped so that the angle detection has an allowable range.

In Table 1, "at the time of high-sensitivity pattern inspection" is intended to increase the sensitivity of defect inspection by increasing the types of edges judged to be 45 °, for example. Depending on the purpose of pattern defect inspection, either "low sensitivity" or "high sensitivity" can be switched, or defect inspection can be performed with both sensitivities and different defect output signals can be obtained, and a suitable one can be selected by the computer CP. Good. Here, the former case, which requires a small circuit scale, will be described.

The number of templates is considerably large as shown in Table 1, but by using PROM, PLD, etc., it can be realized with a very small number (for example, several) of ICs. In this case, PR
Sensitivity switching is easy if a high-sensitivity / low-sensitivity switching signal line is provided in addition to the window edge image signal as the OM and PLD input signal lines.

On the other hand, the reference image information output from the transformation circuit DF in FIG. 2 is the same as the inspected image information output from the binarization circuit BN, and the extraction circuit 17 in FIG. The reference image information is cut out and converted into reference edge information by the reference edge image creating circuit 18. This reference edge information is the cutout circuit.
At 19, it is cut out as reference edge information of a 5 × 5 pixel window.

The cutout circuits 17 and 19 are circuits made by sharing the memory portion of the cutout circuit 6 as described above, and are respectively shown in FIG.
Output the window as shown in Fig. 20. The reference edge image creating circuit 18 is a circuit similar to the inspected edge image creating circuit 7,
An edge image signal of reference image information is created.

The reference edge angle detection circuit 20 applies a template to the reference edge image signal of the window from the cutout circuit 19 and creates a reference edge angle signal by a method similar to the inspected edge angle detection circuit 9. The template is applied according to Table 2. Here, the template is not particularly changed when the high-sensitivity pattern defect is detected and when the low-sensitivity pattern defect is detected. The reference edge angle detection circuit 20 is similar to the inspected edge angle detection circuit 9 in that 0 °, 45 °, 90 °, 13
It outputs a 4-bit reference edge angle signal corresponding to four kinds of angles of 5 °. However, the template is considered so that the range of the edge angle of the reference edge image taken as each angle of 0 °, 45 °, 90 °, and 135 ° is slightly wider than that in the case of detecting the inspected edge angle. . This corresponds to giving an allowable range of angles to the reference edge information with respect to the inspected edge information. The number of templates in Table 1 is larger than that in Table 2 for the following reason. That is, when the analog image information by the image pickup device ID is binarized by the binarization circuit BN, a binarization error inevitably occurs, but the unevenness of one pixel of the image due to the binarization error is not detected as a defect. This is because each of the edge shapes that can be detected in order to allow the inspection with high sensitivity is taken into consideration. On the other hand, Table 2 can be simplified because an image without unevenness for one pixel may be targeted.

In Table 1 for the inspected image information and Table 2 for the reference image information, an edge angle signal of 45 ° is output at the corners of the pattern as shown in FIG. 34 (a). It has become like. This is to prevent the small roundness of the corner as shown in FIG. 34 (b) from being judged as a defect. However, even in this case, the defect as shown in Fig. 34 (c) is 13
Since an edge angle signal of 5 ° is output, it can be detected as a defect (a comparison method will be described later).

The 4-bit inspected edge angle signal output from the inspected edge angle detection circuit 9 and the reference edge angle detection circuit 20
The 4-bit reference edge angle signal output from the above is compared and compared by the comparison circuit 11 described later, and the edge angle (4-bit data content) and position (output timing) represented by both are compared.
It is possible to determine whether the pattern to be inspected is normal or defective depending on whether or not and, but if this is left as it is, an erroneous determination is made due to the following reasons. That is, due to a binarization error in the binarization circuit BN, an error within the manufacturing tolerance of the object to be inspected WK, a positioning error due to the stage ST, etc., the positions represented by both edge angle signals are displaced. Therefore, there is a problem that a normal one is erroneously determined as a defect. Although an angle shift may occur due to a binarization error or the like, an allowable range is added to this when the edge angle of the reference image information is detected by considering the shape of the template as described above.

Therefore, in this embodiment, in order to prevent erroneous determination due to the deviation of both edge angle signals, an allowable range with a certain spread is set around the position represented by the inspected edge angle signal,
It is detected whether or not the reference edge angle signal that matches the inspected edge angle signal exists within this allowable range. Therefore, the output of the reference edge angle detection circuit 20 is expanded by the expansion circuit 21. How much to enlarge depends on how much the allowable range is set in the comparison circuit 11. Although this depends on the manufacturing accuracy of the inspection object WK, the magnification of the image pickup device ID, etc., here, an allowable range of ± 4 pixels (bits) is provided. Then, the enlarging circuit 21 uses the reference edge angle signal for one pixel as a core and fills the range of four pixels around it with the signal of the same logic "1", and the reference edge angle signal for one pixel becomes Enlarged to 9x9 pixels.

A block diagram showing a concrete example of the enlarging circuit 21 is shown in FIG. In FIG. 35, reference numeral 2101 is a 1-bit signal of the 4-bit reference edge angle signal, and 2102 is a timing signal. 2103 is a delay circuit for delaying 0 to 8 lines, which is constituted by a memory according to the same principle as 606 (FIG. 19) in the cut-out circuit 6, and outputs a 1-bit input edge angle signal 2101. On the other hand, 0 line delay (2111), 1 line delay (2112), 2 line delay (2113), ...
., Outputs an edge angle signal with a delay of 8 lines (2114). These nine signals are input to the OR gate 2104,
The ORs are taken and input to the 9-stage (9-bit) serial input parallel output type shift register 2105. The outputs of the respective stages of the 9-bit shift register are ORed by the OR gate 2106, This output 2107 becomes an enlarged reference edge angle signal obtained by enlarging the reference edge angle signal 2101. 2103 is the 19th
It is an extension of 606 in the figure and includes nine memories. As in the case of the cutout circuits 6, 8, 17, and 19, by using a memory in which 4-bit data is obtained in parallel by one read-out for this memory, a 4-bit reference edge angle signal can be obtained. Make four expansion circuits. That is, in order to expand the remaining 3 bits of the reference edge angle signal, the OR gate is used.
An additional 3 sets of circuits including a 2104, a shift register 2105, and a logical sum gate 2106 are prepared to obtain a 4-bit expanded reference edge angle signal in parallel.

As shown in FIG. 36, the comparison circuit 11 includes four circuits of the expansion circuit 21.
The logical product of the corresponding bits of the parallel output obtained by inverting the respective logical values of the parallel outputs 21a to 21d of the bits and the 4-bit parallel outputs 9a to 9d of the inspected edge angle detection circuit 9,
It is obtained through four AND gates 1101 (only one shown). The output of the logical product (4-bit parallel output) is output to a defect information storage circuit (not shown).

For example, when an edge angle signal of 0 ° (a signal whose output 9a becomes a logic "1") is input from the inspected edge angle detection circuit 9 based on the inspected image information, the reference image information is enlarged. If the circuit 21 does not receive an edge angle signal of 0 ° (a signal whose output 21a is logic "1"), it is determined to be defective.

This means that, with respect to the 0 ° edge of the pattern of the small area of the inspection object WK, there was no 0 ° edge within the allowable range of ± 4 pixels (bits) from the corresponding position of the design information. ing.

By the way, since the inspected edge angle signal and the reference edge angle signal reach the comparison circuit 11 through different paths, each circuit in the middle undergoes a different amount of delay. Therefore, it is necessary to take positional correspondence between both signals. For that purpose, at the time of input to the comparison circuit 11, the 1 bit of the center of the reference edge angle signal enlarged to 9 × 9 bits and the 1 bit of the inspected edge signal corresponding to the center are simultaneously compared. The stage ST may be controlled by a driving unit (not shown) so that it is input to the circuit 11.

The defect information storage circuit (not shown) stores the defect information input from the comparison circuit 11 in the storage circuit of the address corresponding to the position (which is known from the time when the signal arrives). The stored defect information is read by the computer CP shown in FIG. 2 collectively for each fixed amount and stored in the external storage device OM.

[Effects of the Invention] As described above, according to the pattern defect inspection apparatus of the present invention, the size of the defect can be determined from the first defect information.
It is possible to calculate the cost required for defect repair. If the first defect information cannot be obtained, the second defect information obtained from the feature extracting means that cannot detect the size of the defect but can detect the true defect in the forbidden band can be obtained.

[Brief description of drawings]

1 is a block diagram showing the configuration of a direct comparison circuit IPa, FIG. 2 is a block diagram showing the entire pattern defect inspection apparatus according to the present invention, FIG. 3 is a block diagram showing the configuration of the inspection circuit IP, and FIG. Is a circuit diagram showing the configuration of the cutout circuit IPa1, FIG. 5 is a schematic view showing a window of 9 × 9 pixels by the cutout circuits IPa1 and IPa2, and FIGS. 6 to 9 are for size determination in each direction. FIG. 10 is a schematic diagram showing the coordinates of the information used, FIG. 10 is a block diagram showing the configuration of the direction-dependent size determination circuit IPa5 and the maximum size determination circuit IPa6, and FIG. 11 is the size determination inhibition circuit IPa7.
FIG. 12 is a schematic diagram showing the coordinates of the information received by the edge detection circuit ED, FIG. 13 is a circuit diagram showing the configuration of the enlargement circuit EL, and FIGS. 14 and 15 are direct comparison circuits. IPa
Pattern diagram showing the defect inspection process of
The figure is an enlarged view showing a disconnection defect or a bridge defect,
FIG. 17 is a schematic diagram showing coordinates of reference image information and inspected image information, which are input in parallel to the forbidden zone creation circuits IPa9 and IPa10, respectively, and FIG. 18 is a block diagram of the feature extraction circuit IPb,
FIG. 19 is a block diagram showing the configuration of the clipping circuit 6, FIG. 20 is a conceptual diagram showing the configuration of a 5 × 5 window, FIG. 21 is a conceptual diagram showing the configuration of a 3 × 3 window, and FIG. 22. (A) to (d) are conceptual diagrams showing templates adopted in the edge image creating circuits 7 and 18, and FIGS. 23 to 33 are conceptual diagrams showing templates adopted in the edge angle detecting circuits 9 and 20. FIG. 34 is an enlarged view showing the corners of the three types of patterns, and FIG. 35 is an enlarged circuit 21.
FIG. 36 is a block diagram showing a concrete example of the above, and FIG. 36 is a circuit diagram showing a concrete example of the comparison circuit 11. [Explanation of symbols of main parts] ID, BN ... Inspected image information generating means OM, DF ... Reference image information generating means IP ... Inspecting means IPa ... Direct comparing means IPb ... Feature extracting means CP ... Editing means

Claims (3)

[Claims] 1. An inspected image information generating means for imaging an inspected object having an inspected pattern formed based on design information and outputting inspected image information corresponding to the inspected pattern, and the design. Reference image information generating means for processing information in a form comparable to the inspected image information and outputting it as reference image information, and comparing the inspected image information and the reference image information,
In a defect pattern inspection device having an inspection means for detecting a defect of the inspection pattern from the result, the inspection means includes a direct comparison means, a feature extraction means, and an editing means, the direct comparison means, The vicinity of the edge of the pattern to be inspected is excluded from the object of the comparison by forming a forbidden zone, and the presence or absence of a defect existing in the other part is detected and the size of the defect is output as first defect information. The extraction unit detects the presence or absence of a defect existing in the entire pattern to be inspected, including the defect existing in the forbidden zone, and outputs it as second defect information, and the editing unit receives the both defect information, the first defect When both the information and the second defect information are output from the respective means, only the first defect information is output, the second defect information is not output, and only the first defect information is output by the means. Output only the first defect information, the first defect information is not output, and when only the second defect information is output from the means, only the second defect information is output. A pattern defect inspecting apparatus, wherein nothing is output when neither the first defect information nor the second defect information is output. 2. The direct comparison means includes a size determination means, which compares the sizes of the detected defects in various directions, and selects and outputs the maximum size from them. The pattern defect inspection apparatus according to claim 1. 3. The inspection means detects the direction of an edge represented by the reference image information, and excludes the size in the direction parallel to the edge from the comparison target in the comparison means. The pattern defect inspection apparatus according to item 1.