JPH0812752B2 - Semiconductor storage device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a serial access memory.

[Conventional technology]

Serially write the stored information to be stored in the storage device,
A FIFO (First In First Out) memory is known as one of serial access memories having an input / output format of serially reading. By setting the write and read functions of the FIFO memory so that they can be controlled independently and asynchronously, it is possible to set a fixed number of delay bits between the write and read operations of information for the same address. This constant delay bit number setting function is effective as a processing function of image information, and the realization of a high-speed and large-capacity FIFO memory is awaited with the development of information equipment for image processing. Conventionally, in a product called a FIFO memory, a static type memory cell was used, and it was difficult to manufacture a large capacity FIFO memory because of its complicated structure.

It should be possible to increase the capacity by using dynamic memory cells for the FIFO memory. However, in order to read information from the dynamic memory cell, bit line precharge,
Since it is possible to output only after the procedure of selecting the word line and sensing the cell information is reached, if the procedure is repeated every time each address is accessed, no speedup can be expected. The following technical measures can be considered for this problem.

As shown in FIG. 3, the memory cell group is divided into two matrices. Then, while one row of one matrix is being accessed, a read preparation (sense of selected cell information of a bit line precharge word line) of one row of the other matrix is performed in advance. Is the adoption of. That is, while reading from address i to address j of one block, read preparation (digit digitage to cell information sense) of address j + 1 to address k of the other block is performed in advance. This is a read-ahead method. If the access loop is formed by using this read-ahead method, it is possible to realize a high-speed and large-capacity memory with a constant delay bit number because the access delay due to the use of dynamic memory cells becomes invisible. .

[Problems to be solved by the invention]

In response to the expansion of the field of use of the FIFO memory, a function is required that can arbitrarily specify an arbitrary number of delay bits instead of the constant number of delay bits as described above. In other words, the work of addressing the entire memory cell in a fixed sequence is terminated at any address and returned to address 0.
A function of setting an arbitrary delay bit number by a reset operation of restarting serial access from address 0 is required. In response to this request, in the FIFO memory according to the above-described read-ahead method using dynamic cells, the read-ahead operation becomes invalid at the reset operation to the address 0. Therefore, the read operation according to the procedure is required again at the address 0, and the access time at this time is slower than that in the case of serial access.
The occurrence of this access delay is a problem when configuring a large capacity FIFO memory with a reset function using a dynamic memory.

A semiconductor memory device of the present invention has first and second memory cell groups each having a plurality of rows, and while one row of one memory cell group is being accessed, the other memory cell is accessed. A semiconductor memory device which reads data from each row of the first and second memory cell groups alternately and serially so as to prepare for reading a row to be accessed next to the cell group. Each of the memory cells that makes resetting possible from any row of the memory cell group and that constitutes the first row of the first memory cell group returned by the reset is a static memory cell. Each memory cell forming each row is composed of a dynamic memory cell.

〔Example〕

 FIG. 1 shows a block diagram of an embodiment of the present invention.

Array 1 from address 0 to address a is composed of static memory cells, and arrays 2 and 3 from address a + 1 to final address are composed of dynamic memory cells.

The operation of this embodiment will be described. First, at start, the address 0 of the static memory cell array 1 is always selected. While access from address 0 to address a is in progress, read preparation (digit precharge to cell information sense) from address a + 1 to address b is preceded. Next, when moving from address a to address a + 1, the next b
Preparation for reading from address +1 to address c is preceded.
This operation is performed similarly to the conventional example.

 Now consider a reset operation from an arbitrary address.

The memory cell group from address 0 to address a is composed of static cells as shown in FIG. 2, and it is possible to immediately output signals when a cell selection signal is received. Therefore, the read procedure (word line up ~
Information sense) is unnecessary.

Therefore, even if addressing is performed from an arbitrary address to address 0, it is possible to access the memory cells without a time delay as compared with normal serial access, that is, accessing memory cells in the order of addresses. If the cell information from the address a + 1 to the address b is read in advance while the access from the address 0 to the address a progresses, the access delay does not occur when the address a is selected from the address a + 1. This is the same as the conventional one.

As described in detail above, the operation of returning to address 0 by the reset signal, which has been a problem in the past, eliminates the need for pre-reading preparation because cells from address 0 to a are made up of static cells, which causes an access delay problem. Does not happen.

According to the present invention, of the memory cell group, the memory cell group for the time required for the preceding read operation, that is, the cell group for at most one row can be statically configured to configure most of the remaining memory cell group with dynamic memory cells. It will be possible. According to the present invention, the FIFO memory having the reset function can be increased in speed and capacity for the first time.

〔The invention's effect〕

As described above, according to the present invention, since a part of the memory cell group including the address 0 is used as a static memory cell, there is no access delay that occurs at the time of start and at the time of reset. Can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory cell of the present invention, FIG. 2 is a circuit diagram of a static cell, and FIG. 3 is a block diagram of a conventional dynamic cell.

Front page continuation (72) Inventor Yasushi Nishikawa 5-7-15 Shiba, Minato-ku, Tokyo NEC Electric microcomputer system Co., Ltd. (56) Reference JP-A-53-136924 (JP, A)

Claims (1)

[Claims] 1. A first memory cell group and a second memory cell group each having a plurality of rows, wherein while one row of one memory cell group is being accessed, the memory cell group of the other memory cell group is being accessed. A semiconductor memory device for reading data alternately and serially from each row of the first and second memory cell groups by preparing to read a row to be accessed next, wherein the first and second memory cells Each memory cell that enables resetting from any row of the group and that constitutes the first row of the first memory cell group returned by the reset is composed of static memory cells, and each row of the first memory cell group is A semiconductor memory device characterized in that each of the constituent memory cells is composed of a dynamic memory cell.