JPH0812864B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to improvement of a channel stopper necessary for preventing surface inversion in a semiconductor device such as a high voltage bipolar IC.

<Prior Art> In a conventional high breakdown voltage bipolar IC, as shown in FIG. 2, an n-type collector layer 101 formed as an isolation island is formed.
The p-type base region 103 is formed on the substrate, and the n-type emitter region 105 is formed on the base region 103. Then, the channel stopper layer 107 having an impurity concentration higher than that of the collector layer 101 is formed on a part of the surface of the collector layer 101. This is because when the collector layer 101 is covered with aluminum wiring or the like with silicon oxide in between, the surface of the collector layer 101 is inverted to form a channel,
This is to prevent a leak current from being generated.

Here, the collector layer formed by epitaxial growth
The impurity concentration of 101 is 10 ¹⁵ cm ⁻³ , and the impurity concentration of the channel stopper layer 107 is about 10 ²⁰ cm ⁻³ as in the emitter layer 105.

This is because the channel stopper layer 107 having the same conductivity type as the emitter layer 105 is formed by predeposition using the same mask.

<Problems to be Solved by the Invention> However, such a conventional high voltage bipolar IC
In that case, since the concentration of the channel stopper layer is too high,
In order to prevent the breakdown voltage from deteriorating, it is necessary to keep the distance between the p-type isolation regions on both sides. For this reason, there is a problem that the cell size is large as a whole because a required interval is required even in the mask alignment process.

Therefore, it is an object of the present invention to reduce the cell size and, in turn, the chip size.

<Means for Solving the Problems> In the semiconductor device according to the present invention, in a semiconductor device having a channel stopper layer on the surface of a collector layer,
The impurity concentration of the channel stopper layer is higher than that of the collector layer and lower than that of the emitter layer,
This channel stopper layer is provided in contact with the isolation layer.

<Operation> In the semiconductor device according to the present invention, the impurity concentration of the channel stopper layer is lowered as compared with the concentration of the emitter layer, and the channel stopper layer is in contact with the separation layer. Can be prevented and the pressure resistance can be maintained. Therefore, it is not necessary to consider the alignment accuracy of the mask, and the cell size can be reduced as a whole.

<Example> Hereinafter, a first example of the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which the present invention is applied to a high breakdown voltage npn bipolar transistor.

In FIG. 1, 11 is a p-type substrate and 13 is a low concentration n-type collector layer. This collector layer 13 is formed by epitaxial growth via the buried layer 15,
They are separated by p-type isolation layers 17 and 19.

Reference numeral 21 denotes a p-type base region diffused in the collector layer 13, in which an emitter layer 23 is diffused and formed.

Here, on a part of the surface of the collector layer 13, channel stopper layers 25 and 27 containing n-type impurities having a higher concentration than the impurity concentration of the collector layer 13 are formed. The channel stopper layers 25, 27 are the p-type isolation layers 17,
19 are formed in contact with each.

Here, the impurity concentration of the channel stopper layers 25 and 27 is
For example, that of the collector layer 13 is 10 ¹⁵ cm ^-3 and that of the emitter layer 23 is 10 ²⁰ cm ^-3 , whereas it is about 10 ¹⁷ cm ^-3 . This is set so that the breakdown voltage satisfies the specified voltage even if the channel stopper layers 25 and 27 are in contact with the isolation layers 17 and 19. At this time, the field inversion voltage is also optimized so as to satisfy the specified voltage.

In the bipolar IC having the above structure, the channel stopper layers 25 and 27 are formed by the ion implantation method and the impurity concentration thereof is appropriately controlled. And the emitter layer
This is a process different from the diffusion of 23.

<Effect> As described above, according to the present invention, since the channel stopper layer is brought into close contact with the isolation layer, it is unnecessary to consider the mask error. Then, the cell size and the chip size can be reduced. For example, when the channel stopper is brought into contact with the isolation, the cell size can be reduced by about 40% as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a sectional view of a bipolar IC according to the first embodiment of the present invention, and FIG. 2 is a sectional view of a conventional bipolar IC. 13 ... Collector layer, 23 ... Emitter layer, 25, 27 ... Channel stopper layer.

Claims (1)

[Claims] 1. A semiconductor device having a channel stopper layer on the surface of a collector layer, wherein the impurity concentration of the channel stopper layer is higher than that of the collector layer and lower than that of the emitter layer, and the channel stopper layer is formed. A semiconductor device, wherein the layer is provided in contact with the isolation layer.