JPH0812919B2 - High voltage MOSFET - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOSFET, and more particularly, to a horizontal type having a drain lead-out line extending in a plane radial direction from an island-shaped drain region and a loop-shaped source region. High voltage MOSFET
Regarding

[Conventional technology]

Conventionally, for example, the structure of a lateral high-voltage MOSFET in an intelligent switching device or the like has a structure in which an N ⁻ -type epitaxial layer 2 epitaxially grown on a P-type substrate 1 is formed as shown in FIGS. An annular P-type isolation region 3 defined by PN junction isolation, an N ⁺ -type drain region 4 formed in an island shape in the epitaxial layer 2, and surrounding the drain region 4 along the isolation region 3 A ring-shaped P-type body (channel diffusion) region 5 formed, a ring-shaped N ⁺ -type source region 6 formed in the body region 5, and a drain region 4 and a body region 5 are defined. A circular drain drift region 2a
An annular polysilicon gate 8 extending over the drain drift region 2a and the source region 6 via a gate oxide film 7, a drain electrode 9 on the drain region 4, a polysilicon gate 8 and a drain electrode 9 A ring-shaped polysilicon high specific resistance film 11 whose inner and outer peripheral ends are connected to the drain polysilicon part 10 connected to the source electrode 12, a source electrode 12 connected to the source region 6, and a drain electrode 9 on the interlayer insulating film 13. The drain lead-out wiring 14 connected to and extending in the radial direction from the drain lead-out wiring 14 and the shield area 15 disposed in the middle between the isolation isolation area 3 and the drain lead-out wiring 14 are provided.

The polysilicon high resistivity film 11 is a drain drift region 2a.
Is a resistive field plate that makes the electric field uniform, and the shield region 15 prevents the formation of an inversion layer on the surface of the isolation region 3 due to the potential of the drain lead wiring 14 and maintains the PN junction separation. Further, the polysilicon high resistivity film 11 prevents the depletion layer from expanding due to the potential of the drain lead wiring 14 in the formation of the accumulation layer on the surface of the drain drift region 2a, and prevents the avalanche voltage from decreasing. It also has a function of blocking the potential of the lead wiring 14.

As described above, in the conventional high breakdown voltage MOSFET, the presence of the polysilicon high specific resistance film 11 and the shield region 15 shields the surface layers of the drain drift region 2a and the isolation region 3 from the potential of the drain lead-out wiring 14. Therefore, a high breakdown voltage can be maintained.

[Problems to be Solved by the Invention]

However, in the above conventional high voltage MOSFET,
When the potential of the drain lead-out wiring 14 becomes high, an inversion layer is formed at the intersection of the drain lead-out wiring 14 and the ring-shaped polysilicon gate 8, and a narrow area is formed between the source region 6 and the drain drift region 2a at the intersection. The channel c is formed and the leakage current increases. That is, a parasitic capacitance in which the interlayer insulating film 13 is interposed is inevitably generated at the intersection of the drain lead-out wiring 14 and the polysilicon gate 8, and this parasitic capacitance is connected in series to the local gate capacitance. Therefore, it does not matter when the potential of the drain lead-out wiring 14 is relatively low, but when it becomes high potential,
The local gate capacitance is charged and an inversion layer is formed immediately below the polysilicon gate 8 at the intersection.

In order to shield the polysilicon gate 8 at the intersection from the potential of the drain lead-out wiring 14, it is conceivable to newly interpose a shield region similar to the shield region 15 at the intersection. Since the parasitic capacitance is only connected in series, when the drain lead-out wiring 14 becomes high potential, the polysilicon gate 8
An inversion layer is generated just below the channel and a channel c is formed.

Therefore, an object of the present invention is to provide a structure in which a channel is not formed even if an inversion layer is formed immediately below the gate at the intersection due to the influence of the potential of the drain lead wiring, and thus an increase in leakage current can be suppressed. It is to provide a high breakdown voltage MOSFET.

[Means for solving the problem]

In order to solve the above problems, the means taken by the present invention are:
An island-shaped first region (for example, the drain region 4), an annular second region of the same conductivity type that surrounds the island (for example, the source region 16), and a second region between the first region and the second region. An adjacent gate (eg, polysilicon gate 8) along
A high breakdown voltage MOSFET including a lead-out wiring (for example, drain lead-out wiring 14) connected to the first region and extending in a radial direction on a plane from at least a lead-out portion of a crossing portion of the second region and the lead-out wiring. Next to the both side edges of the wiring, a second area cutout portion (for example, overhang cutout portions 14b, 14c) for forming the second area in an open loop shape is provided.

[Action]

According to such means, the inversion layer is induced just below the intersection by the potential of the extraction wiring, but the second region should be formed into an open loop shape at least adjacent to both side edges of the extraction wiring in the intersection. Since the two-region cutout portion is provided, the inversion layer induced at the intersection does not reach the second region having the open loop shape, and no local channel is generated. Therefore, the leakage current can be suppressed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 (A) is a sectional view showing an embodiment of a high breakdown voltage MOSFET according to the present invention, and FIG. 1 (B) is a plan view of the same embodiment. In FIGS. 1A and 1B, the same parts as those in FIGS. 2A and 2B are designated by the same reference numerals, and the description thereof will be omitted.

In the figure, an island-shaped drain electrode 9 is formed on the island-shaped N ⁺ type drain region 4 formed in the center on the substrate plane. An annular P-type body region 5 is formed inside the annular isolation region 3 that surrounds the N ⁺ -type drain region 9, and an open-loop source region 16 is formed in the body region 5. There is. An annular polysilicon gate 8 is adjacent along the open-loop source region 16. A drain lead wiring 14 is connected to the drain electrode 9 and extends in the radial direction on the plane through the source cutout portion 18 of the source region 16. The source cutout portion 18 is provided as a source impurity non-introduced region at the intersection of the source region 16 and the drain lead wiring 14, and the cross cutout portion 18a and the drain lead wiring 14 directly under the crossing portion 14a of the drain lead wiring 14 are provided. It is composed of narrow overhanging notches 18b and 18c adjacent to both side edges 14b and 14c.

When a high potential is applied to the drain lead-out wiring 14, an inversion layer (N-type layer) is formed immediately below the polysilicon gate 8 at the intersection or in the intersection cutout portion 18a in some cases. However, no inversion layer is generated in the overhanging cutout portions 18b and 18c, and the P-type is maintained. That is, since the overhanging notches 18b and 18c are not affected by the potential of the drain lead-out wiring 14 and have the meaning of a non-inversion layer, no channel is formed at the intersection. Depending on the film thickness of the interlayer insulating film 13, the intersection cutout portion 18a exists, and the portion just under the intersection portion 14a of the drain lead wiring 14 is the P-type body region 5. Therefore, as described above, this surface layer portion is formed. Also, an inversion layer may occur. Therefore, the presence of the overhanging cutouts 18b, 18c is indispensable, but the source impurity introduction region may be provided directly under the crossing 14a without the crossing cutout 18a. The polysilicon gate 8 at the intersecting portion may be partially removed so as to have an open loop shape, but an inversion layer may be formed under the gate portion of the drain lead wiring 14 which is partially removed at a high potential. Partial deletion is not so important.

As described above, since the source lacking portion 18 is positively provided at the intersecting portion, even if a local inversion layer is generated, it does not contact the source region 16, so that the intersecting portion is not formed. A channel is not formed and leakage current can be suppressed.

〔The invention's effect〕

As described above, the high breakdown voltage MOSFET according to the present invention is
At least both sides of the lead-out wiring at the intersection with the lead-out wiring that is connected to the first conductive area and the second area of the same conductivity type that surrounds and separates the island-shaped first area and extends in a radial direction from the first area. The second area next to the edge should be open looped
Since it has a region cutout portion, even if an inversion layer is formed immediately below the lead-out wiring at the intersection, it does not reach the channel formation. Therefore, eliminate adverse effects due to the potential of the lead-out wiring such as increase in leakage current. You can

[Brief description of drawings]

FIG. 1 (A) is a sectional view showing an embodiment of a high breakdown voltage MOSFET according to the present invention, and FIG. 1 (B) is a plan view of the same embodiment. FIG. 2A is a sectional view showing an example of a conventional high breakdown voltage MOSFET, and FIG. 2B is a plan view of the conventional example. 1 ... P-type semiconductor substrate, 2 ... N ^- type epitaxial layer,
3 ... P-type isolation region, 4 ... N ⁺ -type island drain region, 5 ... P-type body region, 7 ... gate oxide film, 8 ... polysilicon gate, 9 ... drain electrode,
10 ... Drain polysilicon part, 11 ... Polysilicon high resistivity film, 12 ... Source electrode, 13 ... Interlayer insulating film, 14 ...
… Drain lead wiring, 14a …… Intersection, 14b, 14c …… Side edge, 16 …… Open loop N ⁺ type source region, 18 …… Source cutout, 18a …… Cross cutout, 18b, 18c …… Overhanging cutout section.

Claims (1)

[Claims] 1. An island-shaped first region, a ring-shaped second region of the same conductivity type that surrounds the island-shaped region, and a gate adjacent to the first region and the second region along the second region. A high withstand voltage MOSFET including a lead wiring connected to the first region and extending in a radial direction from the first region, wherein at least both side edges of the lead wiring at a crossing portion of the second region and the lead wiring. A high breakdown voltage MOSFET characterized in that it is provided with a second region cutout portion adjacent to the second region to make the second region open loop.