JPH0812935B2 - Superconductor electronic device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to superconductor electronic devices, and more particularly to pressure gate type transistors.

[Conventional technology]

Among conventional transistors, the Schottky barrier type field effect transistor is, for example, an n-type transistor as shown in FIG.
A gate electrode 102 in Schottky contact with GaAs is provided on the surface of the GaAs conductive layer 101, and a drain current flowing between the source electrode 21 and the drain electrode 22 provided so as to sandwich the gate metal is formed on the n-type GaAs surface immediately below the gate electrode. Depletion layer 10
Controlled by the thickness of 5. In addition, the magnetic field coupling type Josephson 3-terminal element provides an input by coupling the magnetic field created by the current flowing in the wiring to the Josephson element, and the Josephson field effect transistor is shown in FIG. As shown, a voltage is applied to the weak coupling portion 109 in the degenerate region formed between the superconductor-semiconductor junction portion of the weak coupling type Josephson element to form a depletion layer to form the source electrode 106 and the drain electrode 106 of the superconductor. It controls the number of superconductors flowing between 108.

[Problems to be Solved by the Invention]

Among the conventional transistors described above, the Schottky barrier field effect transistor has a problem that the mutual conductance g _m is only about 100 mS because of its large channel resistance. In addition, since the magnetic field coupling type Josephson 3-terminal element requires a large area to secure the magnetic flux amount φ ₀ (= 2.07 × 10 ^-15 Wb), it is difficult to achieve high integration with such an element. Further, the Josephson field effect transistor has a problem that the device resistance is high due to the junction of semiconductor coupling and that the IV characteristic has hysteresis.

An object of the present invention is to provide a new superconductor electronic device which has a large mutual conductance and can be highly integrated.

[Means for solving the problem]

A superconductor electronic device of the present invention is a superconductor crystal layer of a predetermined shape having a crystal plane that is epitaxially grown on a surface of an insulating crystal substrate having a predetermined plane orientation and that exhibits a two-dimensional superconductivity in a direction parallel to the surface. And including a piezoelectric element provided on the superconductor crystal layer across the superconductor crystal layer, and applying a pressure to the superconductor crystal layer in a direction perpendicular to the crystal plane due to strain generated by an input voltage applied to the piezoelectric element. A pressure gate to be applied and a source electrode and a drain electrode made of a pair of conductive films attached to the superconductor crystal layer with the pressure gate interposed therebetween, and a superconducting current between the source electrode and the drain electrode is generated. It is controlled by the input voltage.

[Work]

Pseudo-perovskite structure and K ₂ NiF ₄ type ceramic crystals known as ceramic superconductors are Y, some of the lanthanoid elements (La, Yb, Tm, Er, Ho, Dy, Tb, Gd, Eu, S
m) and alkaline earth metals (Ba, Ca, Sr, etc.) and divalent (C
It is a Ln-A-Cu (Ag) oxide composed of u, Ag) and O, and exhibits superconductivity in which its electric resistance becomes zero at low temperature. Y51,
A superconductor composed of Ba52, Cu53, O54, such as YBa ₂ Cu ₃ O _6.69
Belongs to the orthorhombic system as shown in FIG. 4, and has a lattice constant (a =
As can be seen from 3.8845Å, b ＝ 3.8293Å, C = 11.693Å), Cu-O bond chains 55 are long in the C-axis direction and in the ab plane perpendicular to the C-axis.
Has a structure that expands infinitely. This Cu-O bond chain
The plane of 55 is laminated in layers in the C-axis direction, and the superconductivity of the crystal is such that the strongly bound electrons generated by the mixture of the 3d orbital of Cu and the 2p orbital of O of this Cu-O bond chain are highly conductive. It is said to occur to form the Fermi surface of the strip.
Therefore, the superconductivity of the crystal occurs only in the ab plane perpendicular to the C-axis, that is, only in the Cu-O bond chain plane, and there is a characteristic that the conductivity is two-dimensionally leaking slightly in the C-axis direction. . In a superconducting crystal that exhibits such two-dimensional superconductivity, when pressure is applied in the direction perpendicular to the C-axis, Cu-
The O bond distance becomes smaller, and as a result, the superconducting dislocation temperature Tc
Is known to increase and the electrical resistance decreases.

The principle of the present invention is to control the channel conductance of the superconducting crystal between the source and drain electrodes by applying pressure to the crystal to change the state density distribution of the Fermi surface of the Cu—O bond chain. When pressure is applied perpendicularly to the C-axis, the channel conductance in the ab plane increases, whereas when pressure is applied in the C-axis direction, the channel conductance conversely decreases. Therefore, in the present invention, a pressure gate such as a piezoelectric element is arranged so as to completely traverse the surface of the superconductor crystal layer serving as a channel, a bias input is applied to the piezoelectric element, and the pressure gate is driven to perform electric / pressure conversion. Then, a pressure is applied in the C-axis direction of the superconductor crystal layer, and the normally-on type transistor in which the channel conductance between the source and drain electrodes is controlled by applying this pressure. By arranging the pressure gate so as to completely traverse the surface of the superconductor crystal layer which becomes the channel, the superconducting current flowing through the channel can be completely pinched off by the pressure gate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a chip showing a first embodiment of the present invention.

In this example, a rectangle (1 cm ×) having a crystal plane (ab plane) which is deposited on the (100) plane of an insulating substrate (MgO substrate 10) and exhibits two-dimensional superconductivity in a direction parallel to the (100) plane. 0.1 cm) superconductor crystal layer (YBa ₂ Cu ₃ O _6.69 crystal layer 11) and YBa ₂ Cu ₃ O
_6.69 A piezoelectric element (having a PZT film 31 and a pair of comb-shaped electrodes 41 and 42) provided across the crystal layer 11 is provided, which is generated by an input voltage applied to the piezoelectric element. a pressure gate for applying pressure to the crystal surface by the distortion (ab plane) and perpendicular to the superconductor crystal layer (YBa ₂ Cu ₃ O _6.69 crystal layer 11) to, YBa ₂ Cu ₃ O _6.69 across the pressure gate of the above It has a source electrode 21 and a drain electrode 22 formed of a pair of conductive films deposited on the crystal layer 11, and suppresses the superconducting current between the source electrode and the drain electrode by the input voltage. It should be called a pressure gate type field effect transistor.

 Next, the manufacturing method of this embodiment will be described.

2 (a) and 2 (b) are cross-sectional views of the chips arranged in the order of steps for explaining the manufacturing method of the first embodiment.

First, as shown in FIG. 2 (a), the MgO substrate 10 (10
Since it was deposited on the (0) surface by the sputtering method, it was heat treated to form YBa ₂ C with a thickness of 1 mm, a width of 1 cm and a length of 5 mm.
u ₃ O _{6.69 The} crystal layer 11 is provided. At this time, the YBa ₂ Cu ₃ O _6.69 crystal layer 11 has the C axis in the direction perpendicular to the MgO substrate 10. Next, as shown in FIG. 2 (b), YBa ₂ Cu ₃ O _6.69 crystal layer 11
A source electrode 21 and a drain electrode 22 are provided by depositing Au on both ends of the crystal film 11 including the plane parallel to the C axis. Then the first
As shown in the drawing, a voltage is applied so that the surface of the YBa ₂ Cu ₃ O _6.69 crystal layer 11 sandwiched between the source electrode 21 and the drain electrode 22 is completely crossed. PZ with a thickness of 1 μm as a pressure gate
A piezoelectric element composed of T (= solid solution of Zr-Ti-Pb) 31 and a pair of comb-shaped electrodes 41 and 42 (made of Au) for gate signal input provided on the PZT 31 is provided. This example has about 80
When cooling to K and applying a maximum gate signal input of 1 V to the comb-shaped electrodes 41 and 42, the comb-shaped electrode 4 depends on the input voltage.
1,42 The PZT film 31 immediately below is expanded in the direction perpendicular to the surface of the YBa ₂ Cu ₃ O _6.69 crystal layer 11, and as a result, pressure is applied to the superconductor crystal layer immediately below the PZT film 31 to reduce the lattice spacing of this crystal film. Can be changed. As is well known, when pressure is applied in the C-axis direction, the lattice spacing in the ab plane where the Cu—O bond chains are present becomes large and the superconducting current decreases accordingly. In the case of the present embodiment, as shown in FIG. 3, when Vg = 1 V was input to the pressure gate, the superconducting current I _ds was controlled to 0 A at 50 A when 0 V was input. When the pressure gate width, that is, the channel width is 1 cm, the transconductance corresponds to 5000 mS / mm.

 FIG. 5 is a sectional view of the chip showing the second embodiment.

In this embodiment, a sapphire substrate 60 as an insulating substrate,
This is the same as the first embodiment except that the (La · Ca) ₂ AgO ₄ crystal layer is used as the superconductor crystal layer.

 Next, the manufacturing method of the second embodiment will be described.

6 (a) and 6 (b) are cross-sectional views of the chips arranged in the order of steps for explaining the manufacturing method of the second embodiment.

As shown in FIG. 6 (a), the (01
2) A (La · Ca) ₂ AgO ₄ crystal layer 61 having a thickness of 1 mm is formed on the surface and heat treatment is performed. At this time, (La · Ca) ₂ AgO ₄ belongs to the orthorhombic system, and the C axis of the (La · Ca) ₂ AgO ₄ crystal layer 61 is perpendicular to the sapphire substrate 60.

Next, as shown in FIG. 6 (b), (La · Ca) ₂ AgO ₄
A source electrode 21 and a drain electrode 22 are provided by depositing Au on both ends of the crystal layer 61 including a plane parallel to the C axis. Next, as shown in FIG. 5, it was sandwiched between the source and drain electrodes (La.
Ca) ₂ AgO ₄ crystal layer 61 has a thickness of 1 as a pressure gate that is displaced in the C-axis direction of the superconductor film by applying a voltage.
A μm PZT 31 and comb-shaped electrodes 41 and 42 for inputting a gut signal are provided on the PZT 31.

When the pressure-gate type transistor of the present invention thus obtained is cooled to about 30 K and a gate signal input Vg of maximum 1 V is applied to the comb-shaped electrodes 41 and 42, the superconducting current between the source and drain electrodes is 0 V input. When 30A was suppressed to 0A. If the channel width is 1 cm, the transconductance is 3000 mS / mm.

In the above examples, YBa ₂ Cu ₃ O was used as the superconductor crystal.
_6.69 and (La · Ca) ₂ AgO ₄ have been described as an example, and PZT has been described as an example of the pressure gate material. However, other superconducting materials such as Ln-A-Cu-O system or Lu-A-Ag-O system are used. Also in the body, LiTa
The use of other piezoelectric crystals such as O ₃ and LiNbO ₃ does not impair the idea of the present invention. The substrates that can be used are not limited to MgO and sapphire, and it goes without saying that the present invention is applicable to any substrate that can grow a superconductor film such as SrTiO ₃ crystal.

〔The invention's effect〕

As described above, the present invention, by applying a gate signal of about 1V to the pressure gate provided on the surface parallel to the surface showing the superconducting property of the superconductor crystal layer, the Fermi surface of the coupling chain of the superconductor crystal By controlling the superconducting current between the source and drain of the superconductor crystal by changing the density of states distribution, it is possible to obtain a superconductor electronic device having an extremely large transconductance g _m of ^{3 to} 5 × 10 ³ mS / mm. it can. Furthermore, in many conventional transistors, the characteristics depend on the cleanliness of the boundary between the gate electrode and the crystal film and are extremely sensitive to the surface, but the present invention modulates by applying mechanical displacement using a pressure gate. Therefore, it also has an effect that the surface characteristics are insensitive and stable on the surface. Also, if a piezoelectric element is used as the pressure gate, the size of the transistor can be small,
Therefore, high integration is easy.

[Brief description of drawings]

FIG. 1 is a sectional view of a chip showing a first embodiment of the present invention,
2 (a) and 2 (b) are cross-sectional views of the chips arranged in the order of steps for explaining the manufacturing method of the first embodiment, and FIG. 3 is a signal waveform diagram for explaining the operation of the embodiment. Figure 4 shows YB
a ₂ Cu ₃ O _6.69 crystal structure model, FIG. 5 is a cross-sectional view of a chip showing the second embodiment, and FIGS. 6 (a) and 6 (b) explain the manufacturing method of the second embodiment. 7 is a cross-sectional view of a chip showing a Schottky barrier field effect transistor, and FIG. 8 is a cross-sectional view of a chip showing a Josephson field effect transistor. 10 …… MgO substrate, 11 …… YBa ₂ Cu ₃ O _6.69 crystal layer, 21 …… Source electrode, 22 …… Drain electrode, 31 …… PZT film, 41,42…
… Comb-shaped electrodes for gate signal input, 51 …… Y, 52 …… B
a, 53 …… Cu, 54 …… O, 55 …… Cu-O bond chain, 60 ……
Sapphire substrate, 61 …… (La ・ Ca) ₂ AgO ₄ crystal layer, 101…
... n-type conductive layer, 102 ... gate electrode, 106 ... superconductor source electrode, 107 ... superconductor gate electrode, 108 ... superconductor drain electrode, 105, 109 ... depletion layer of weak coupling portion, 110 ...
… Semiconductor substrate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 41/04

Claims (1)

[Claims] 1. A superconducting crystal layer having a predetermined shape and having a crystal plane which is epitaxially grown on a surface of an insulating crystal substrate having a predetermined plane orientation and has a two-dimensionally superconducting property in a direction parallel to the surface, and the superconducting layer. A pressure gate including a piezoelectric element provided across the body crystal layer, for applying a pressure to the superconductor crystal layer in a direction perpendicular to the crystal plane by strain generated by an input voltage applied to the piezoelectric element; A source electrode and a drain electrode made of a pair of conductive films deposited on the superconductor crystal layer with the pressure gate sandwiched therebetween, and a superconducting current between the source electrode and the drain electrode at the input voltage. A superconductor electronic device characterized by controlling.