JPH0812984B2 - PLL tuning device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL channel selection device used in a television receiver, an AM / FM radio receiver, or the like.

2. Description of the Related Art In recent years, PLL channel selection devices have been widely used in television receivers and radio receivers.

Hereinafter, an example of a conventional PLL channel selection apparatus including a prescaler will be described with reference to the drawings. FIG. 3 is a block diagram of a conventional channel selection device. In the figure, 1 is a voltage controlled oscillator used as a local oscillation of a receiver, 2 is a prescaler for dividing the output of the voltage controlled oscillator 1 into 1 / N, and 5 is a tuning operation unit and is connected to a tuning control unit 4. Has been done. Reference numeral 4 denotes a tuning control unit, which is composed of a microcomputer, and when a tuning instruction of a new frequency is input from the tuning operation unit 5, calculates frequency division data M for obtaining the local oscillation frequency and calculates it. It has a function of transferring to the tuning frequency divider 3. Reference numeral 3 is a channel selection frequency divider, which latches the frequency-divided data transferred, frequency-divides the signal from the prescaler 2 to 1 / M, and supplies it to one of the phase comparators 6. On the other hand, 7 is a reference frequency oscillator, and the signal oscillated here is divided into 1 / L by the reference frequency divider 8 and supplied as the reference comparison signal to the other input of the phase comparator 6. The output of the phase comparator 6 is input to the active low-pass filter 9, and its output is connected to the voltage controlled oscillator 1 as a control voltage.

In the PLL channel selecting device configured as described above, FIG. 4 shows a state in which the frequency _L which has already been selected is switched to _L '. T ₁ indicates the time when the tuning operation unit 5 is operated and the tuning control unit 4 calculates the frequency division ratio M'and transfers it to the channel selection frequency divider 3 and the frequency division ratio is switched from M to M '. There is.
When the frequency division ratio changes to M ', the output phase from the channel selection frequency divider 3 changes, and the voltage of the phase comparator 6 generated by this phase difference is smoothed by the active low-pass filter 9 to control the voltage of the voltage controlled oscillator 1. The frequency divided by the prescaler 2 and the tuning frequency divider 3 is matched with the output frequency of the reference frequency divider 8. That is, the control voltage ν _t converges to ν _t ′ at time T ₃ .

Problems to be Solved by the Invention However, such a conventional device has the following problems.

It is known that the convergence time T of the control voltage when the frequency is switched can be shortened by increasing the phase comparison frequency _REF . When the prescaler frequency division ratio is N and the minimum frequency unit that can be selected, that is, the frequency resolution, is _RES , the relational expression (1) holds. _REF = _RES / N (1) Equation (1) shows that in order to increase _REF , the prescaler frequency division ratio N can be reduced or the frequency resolution _RES can be increased. Dividing ratio N
When is smaller, the output frequency of the prescaler is higher,
Problems such as the need for a high-speed tuning frequency divider and an increase in the interference level that harmonics give to the desired signal occur.
In addition, the frequency resolution _RES determines the resolution of automatic and manual fine adjustment of the frequency, and it is difficult to increase it because appropriate fineness is required.

That is, the frequency division ratio N and frequency resolution of the prescaler
_There is a problem that it is impossible to increase the phase comparison frequency _{REF to} shorten the control voltage convergence time T without changing _RES .

In view of the above-mentioned problems, the present invention has a frequency division ratio N of the prescaler.
And a PLL tuning device that can shorten the control voltage convergence time without changing the frequency resolution _RES .

Means for Solving the Problems In order to solve the above problems, a PLL tuning device of the present invention is a prescaler for dividing the output of a voltage controlled oscillator in a fixed manner, and an output of the prescaler for dividing at a desired division ratio. Tuning frequency divider, a reference frequency divider that divides the reference frequency oscillation signal at an arbitrary frequency division ratio, and frequency division of both the tuning frequency divider and the reference frequency divider when tuning. The tuning control unit controls the rate so that the rate is temporarily reduced to the same rate.

Operation According to the present invention having the above-described configuration, the channel selection control unit temporarily reduces the frequency division ratios of both the channel selection frequency divider and the reference frequency frequency divider to the same rate when the channel is tuned. As a result, the phase comparison frequency is increased and the control voltage convergence time is shortened.

Embodiment A PLL channel selecting apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a PLL channel selection apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 5 denotes a tuning operation unit and a tuning control unit 4
It is connected to the. The tuning control unit 4 is composed of a microcomputer, and when a tuning instruction of a new frequency _L' is input from the tuning operation unit 5, the frequency division data M'to obtain the local oscillation frequency is multiplied by 1/2. Of M ′ and calculate the time T ₁ <
When t <T ₂ , 1/2 times M ′ is transferred, and at time t> T ₂ , M ′ is transferred to the tuning frequency divider 3 and at the same time the frequency division data L of the reference frequency divider 8 and 1/2 are transmitted. It has a double L, and has a function of transferring 1/2 to L when time T ₁ <t <T ₂ and L to time T> T ₂ to the reference frequency divider 8. Reference numeral 8 is a reference frequency divider having a function of dividing the signal of the reference frequency oscillator 7 by the division ratio transferred from the tuning controller. Others are the same as in the conventional example, and therefore omitted.

The operation of the PLL channel selecting device configured as described above will be described below. FIG. 2 shows how the already-selected local oscillation frequency _L is switched to _L '. At t = T ₁ , the tuning operation unit 5 is operated and the tuning control unit 4 divides the frequency division ratio M ′ by 1/2 and the frequency L by 1/2 into the tuning frequency divider 3 and the reference frequency, respectively. The frequency division ratio of the tuning frequency divider 3 is changed from M to 1 / 2M 'and the frequency division ratio of the reference frequency divider 8 is changed from L to 1 / 2L. At this time, the frequency sent from the reference frequency divider 8 to the phase comparator is doubled, and the frequency from the tuning frequency divider 3 is 2M '/ M times. This phase difference (frequency difference) causes a voltage in the phase comparator 6, which is smoothed by the active low-pass filter 9 so that the control voltage becomes the second voltage.
Begin to change toward the υ _{t 'than} as υ _t of Fig. t =
At T _1, the phase comparison frequency applied to the phase comparator is
It was _L / NM ', but here it is 2 _L / NM, which is twice the conventional value.

Therefore, the changing speed of the control voltage at this time becomes faster than the conventional _one, and the time from T ₁ to T _{2 in} the conventional example of FIG. 4 is shortened as T ₁ to T ₂ of FIG.

Next, at an appropriate time t = T ₂ when the control voltage approaches υ _t ′, the tuning control unit 4 changes the frequency division ratio of the tuning frequency divider from 1/2 M ′ to M ′, and the fundamental frequency divider 8 Change the frequency division ratio of to L from 1 / 2L. As a result, the control voltage operates in the same manner as the conventional one until the complete convergence of t = T ₃ .

As described above, the total convergence time T ₁ to T ₃ of the control voltage when _L ′ is selected from the frequency _L can be shortened.

As described above, according to the present invention, in the PLL channel selection device provided with the prescaler for fixed frequency division, the frequency divider and reference frequency for dividing the output of the prescaler at an arbitrary frequency division ratio are set. A reference frequency divider that divides at an arbitrary division ratio and tuning control that controls the division ratio of both the tuning frequency divider and the reference frequency divider are provided. The frequency division ratio of both the tuning frequency divider and the reference frequency divider is temporarily reduced to the same rate from the steady state, so that the control voltage convergence time can be maintained without changing the frequency division and the frequency division rate of the prescaler. Can be shortened.

Further, if the control voltage convergence time is fixed in the present invention, the phase comparison frequency can be selected low, so that the frequency division ratio of the prescaler can be increased and the frequency resolution can be made fine.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL channel selecting apparatus according to an embodiment of the present invention, FIG. 2 is a time chart showing the time relationship between its control voltage and frequency division ratio, and FIG. 3 is a conventional example of the PLL channel selecting apparatus. The block diagram and FIG. 4 are time charts showing the time relationship between the control voltage and the frequency division ratio. 1 ... Voltage controlled oscillator, 2 ... Prescaler, 3 ... Tuning frequency divider, 4 ... Tuning controller, 7 ... Reference frequency oscillator, 8 ... Reference frequency divider.

Claims (1)

[Claims] 1. A frequency fi of an output signal of a voltage controlled oscillator.
A prescaler that divides (t) by a fixed dividing ratio N, a tuning divider that divides the output of this prescaler by an arbitrary dividing ratio M, and the frequency of the oscillation output signal of the reference frequency oscillator.
A reference frequency divider that divides fr at an arbitrary division ratio L, a channel selection control unit that controls the frequency division ratios of the channel selection frequency divider and the reference frequency divider, and the channel selection control unit. The tuning operation unit that gives a tuning instruction and the phases of the tuning frequency divider output signal and the reference frequency frequency divider output signal are compared, and the detection voltage Vd is detected according to the phase difference.
A tuning frequency divider for outputting (t), wherein the tuning control unit receives a tuning instruction input signal from the tuning operation unit to obtain a local oscillation frequency corresponding to the tuning instruction signal. Frequency division data M'and its frequency division data M '
Of 1 / m of the divided data M '* (1 / m) of
Dividing data L of 1 / m of dividing data L of the reference frequency divider
* (1 / m) is calculated, and when the tuning instruction signal is input from the tuning operation unit, at T ₁ , the specified frequency is divided by the tuning controller and the reference frequency divider. The divided frequency data of 1 / m is supplied, and the output frequency fi of the voltage controlled oscillator is
F when (t) becomes equal to a predetermined frequency (M ′ × N / L) fr
i (T2) = (M ' × N / L) after reaching the time T ₂ of the fr is then supplied to the respective predetermined frequency division data from the channel selection instruction signal input time T ₁ of the said T ₂ In the interval T ₁ ≤t ≤T ₂ , the tuning control unit performs each tuning operation so that the time change rate of the detection voltage Vd (t) is m times the time change rate in T ₂ ≤t. A PLL tuning device characterized in that the frequency division ratio is switched and controlled.