JPH0813052B2 - Loop filter circuit for carrier recovery circuit - Google Patents

Description

The present invention relates to a carrier recovery circuit for demodulating an audio signal such as a character broadcasting signal and a satellite broadcasting signal, and a loop filter circuit forming a part of this carrier recovery circuit. It is about.

"Prior Art" A conventional carrier recovery circuit is configured as shown in FIG. In this circuit, the input QPSK signal is converted into a digital signal by the A / D converter (1), and the multiplier (2)
Phase detector (6) consisting of (3) and LPF (4) ( 5 )
The cos φ and sin ψ are taken out respectively through (7), the phase difference ψ is obtained by the phase difference comparator (8), passed through the loop filter circuit (9), and further through the D / A converter (10).
Go to (11), compare the phase difference of the carrier on the generation side of the QPSK signal, and control so that the difference becomes zero.

However, the conventional loop filter circuit (9) has a third
As shown in the figure, the first and second coefficient units (12) (13),
In addition to the first adder (14), a complete adder (17) including a second adder (15) and a latch circuit (16) is provided.

In this circuit, the first and second adders (14)
(15) and the latch circuit (16) are provided with overflow protection for protecting the PLL because the PLL cannot be pulled in if the output becomes 0 due to overflow.

[Problems to be Solved by the Invention] However, the initial value of the latch circuit (16) of the complete integration section (17) when the power is turned on is not constant, but changes depending on the situation at that time. When the initial value of the latch circuit (16) at power-on is large and the amplitude on the input side at this time is small, the output of the phase difference becomes smaller than the value of the latch circuit (16), and the latch circuit (16 It may be buried in the value of 16). Then, the output of the latch circuit (16) does not change, and the phase difference on the input side is not reflected on the output side.
Therefore, there is a problem that the PLL may not be pulled in.

It is an object of the present invention to obtain a circuit in which the PLL is surely locked no matter how large the value of the complete integration part of the loop filter circuit when the power is turned on.

"Means for Solving the Problem" The present invention divides a QPSK signal input to a QPSK input terminal into two, and sends them to a VCO via a phase detector, a phase difference comparator, and a loop filter circuit, respectively. In the carrier recovery circuit in which the phase difference between the input carrier and the reproduction carrier difference is controlled to be 0 by sending the signal of (1) to the phase detector, the loop filter adds a steady small constant value. And a first and second coefficient unit,
It is composed of a first adder and a complete integrator, and this complete integrator forms a loop by the second adder and a latch circuit without overflow protection.

"Operation" The QPSK input to the QPSK input terminal passes through the phase detector (multiplier and LPF) and is sent to the phase difference comparator. In the phase comparator, the phase of the carrier wave on the QPSK signal generation side is compared with the phase difference of the reproduced carrier wave generated by the VCO, and a control signal is added to the VCO so that the difference becomes 0. The output is integrated via the loop filter circuit. At this time, there is no overflow protection in the latch circuit,
Since a constant small constant value is added to the phase difference, even if the initial value of the latch circuit at power-on is large and the input phase difference becomes small, the latch circuit will eventually overflow in several loops. It becomes 0. However, since the steady small constant value is added to the phase difference, it immediately becomes a small non-zero value in the next loop. If the value of the latch circuit becomes a small value other than 0, even a small phase difference is reflected in the output without being buried in the latch circuit, the PLL is pulled in, and when the phase of the QPSK signal and the oscillation signal of the VCO are synchronized, the latch circuit The value of locks stably. PLL
When is locked, the VCO oscillation becomes a stable and constant value.

In addition, the output value of the latch circuit causes a gap from the maximum value to 0 at a dash due to overflow, but the phase of the QPSK signal and the oscillation signal of the VCO are not synchronized and the entire circuit is unstable. No problem. Also,
After the PLL locks and the oscillation of the latch circuit and VCO stabilizes, the value of the latch circuit does not change significantly unless the input QPSK signal is abnormal, and the latch circuit overflows again. There is no such thing.

Further, the loop filter operates as if the phase difference between the original QPSK signal and the oscillation signal of the VCO and an extra phase difference by the steady small constant value added by the adder. As a result, to be exact, the PLL locks in a state where a negative phase difference is generated between the QPSK signal and the oscillation signal of the VCO by the steady small constant value, but the steady constant value to be added is fixed. By making it small, it is within the error range for the loop filter circuit and is ignored.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

1 is different from FIG. 3 in that an adder (18) for adding a steady constant value is inserted in the preceding stage of the loop filter, and the latch circuit (16) has no overflow protection. Is to use.

In the above configuration, the operation up to the loop filter circuit (9) will be described first with reference to FIG.
The QPSK signal input to the QPSK input terminal (19) is converted into a digital amount by the A / D converter (1), and the signal is transferred to the digital multipliers (2) and (3) of the phase detectors (6) and (7). The signal passes through the digital LPF (4) ( 5 ) and is sent to the phase difference comparator (8) to obtain the phase difference φ. This phase difference data ψ is sent to the adder (18) of FIG. 1 to add a preset small constant value. In other words, due to the influence of the phase change in the process of data transmission, the phase difference information should not be 0 even when the PLL is completely locked.

The complete integrator (17) has no overflow protection and adds a steady small constant value to the phase difference, so the initial value of the latch circuit (16) at power-on is large and the input phase difference is small. Even so, the integrated value of the latch circuit (16) gradually increases due to several loops and eventually overflows to 0. However, since the steady small constant value is added to the phase difference, it immediately becomes a small non-zero value in the next loop. Latch circuit (1
When the value of 6) becomes a small value other than 0, a small phase difference is not buried in the latch circuit (16) and reflected in the output, so that the PLL is pulled in.

[Advantages of the Invention] Since the present invention is configured as described above, even if the value of the complete integration unit is any value such as when the power is turned on, the PL
L becomes locked, and the operation of the loop filter becomes stable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a loop filter circuit of a carrier recovery circuit according to the present invention, FIG. 2 is a block diagram of a carrier recovery circuit, and FIG. 3 is a block diagram of a conventional loop filter circuit. (1) …… A / D converter, (6) (7) …… Phase detector,
(8) …… Phase difference comparator, (9) …… Loop filter circuit, (10) …… D / A converter, (11) …… VCO (voltage controlled oscillator), (12) (13) …… First and second coefficient units,
(14) (15) …… First and second adders, (16) ……
Latch circuit, (17) …… Complete integration section, (18) …… Adder, (19) …… Data input terminal, (20) (21) …… Output terminal.

Claims (1)

[Claims] 1. A QPSK signal input to a QPSK input terminal (19) is branched into two, which are respectively passed through a phase detector (6) (7), a phase difference comparator (8) and a loop filter circuit (9). VC
By sending the signal of this VCO (11) to O (11) and sending it to the phase detectors (6) and (7), the phase difference between the input carrier wave and the reproduction carrier difference is controlled to be zero. In the carrier recovery circuit, the loop filter circuit (9) includes a phase difference comparator (8).
Adder (18) for adding a constant small constant value to the input signal from, the first and second coefficient multipliers (12) (13) to which the output of this adder (18) is connected, and the second Coefficient multiplier (13)
And a first adder (14) for adding the output of the first coefficient multiplier (12) and the output of the complete integrator (17). The integrator (17) includes a latch circuit (16) to which an output of a second adder (15) described later is connected and which has no overflow protection, an output of the latch circuit (16) and the second coefficient unit ( A loop filter circuit of a carrier wave regenerating circuit, characterized in that a loop is formed by a second adder (15) for adding and outputting the output of 13).