JPH0813121B2 - Time axis error correction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis error correction apparatus that is most suitable for a video tape recorder (hereinafter abbreviated as VTR).

Conventional technology In recent years, due to the rapid development of semiconductor technology, large-scale digital circuits have been integrated into LSIs and A / D, D / A capable of operating at video rates.
Converters have become affordable at a low cost, and it has become possible to implement time base correction (time base collector) of playback video signals using digital memory even in consumer VTRs.

This conventional time-axis correction device is a device that corrects fluctuations in the time axis due to waveform distortion of the horizontal synchronizing signal of the reproduced video signal. Generally, the horizontal synchronizing signal of the reproduced video signal is easily disturbed by the influence of the video waveform whose leading edge precedes. However, since the time reference for image display is the front edge of the horizontal sync signal, fluctuations occur at the front and rear edges of the horizontal 1H of the image plane. The following proposal has already been made for this time axis correction means, but it was to replace it with a horizontal synchronizing signal having a well-shaped waveform.

Hereinafter, the conventional time axis correction device will be described with reference to FIGS. 3 and 4.

As shown in the figure, the horizontal sync signal separation circuit (HSS) 4 separates the horizontal sync signal b of the reproduced video signal a from the input terminal 1, and the separated signal is supplied to the write clock generation circuit (W-CL
K) 5 and write reset pulse generation circuit (R-RST) 6. The write clock generation circuit 5 uses the horizontal synchronization signal b
A write clock d that starts in phase synchronization with the trailing edge is generated and supplied to the A / D converter (A / D) 2 and the memory 3.
Further, the write reset pulse generating circuit 6 generates a reset pulse c which is phase-synchronized with the trailing edge of the horizontal synchronizing signal b and supplies it to the memory 3. The A / D converter 2 writes the reproduced video signal a with the reset pulse c as a time axis reference and the write clock d.
Sampling is performed at the timing of, and the data is input to the memory 3.

On the other hand, the reference oscillator 8 generates a reference clock e and supplies it to the memory 3, the D / A converter 7 and the synchronizing signal generating circuit 9. The synchronizing signal generator 9 generates a reference reset pulse f and a reference composite synchronizing signal g formed by dividing the reference clock e. A D / A converter (D / A) 7 converts the data in the memory 3 into a video signal h and inputs it to the replacement circuit 10. This data reading is performed at the timing of the reference clock e with the reset pulse f as a time axis reference. The replacement circuit 10 replaces the composite sync signal of the video signal h with the reference composite sync signal g formed by the sync signal generation circuit 9.

The operation of the above conventional configuration will be described. The waveforms shown in FIG. 4 represent the output waveforms of the circuit blocks shown in FIG. 3, and the same symbols correspond to the same signals.

The principle of this operation is to replace the disturbed horizontal sync signal of the reproduced video signal with another horizontal sync signal having a well-shaped waveform. However, this replacement is impossible in real time, and it is necessary to delay the video signal by at least the time width of the horizontal synchronizing signal and perform waveform manipulation. As this delay means, a certain waveform delay can be obtained by A / D converting the reproduced video signal once, writing it in the memory, reading the memory again, D / A converting it and reproducing the waveform. it can. This delay operation can be accurately performed by digital processing using a clock.

The reproduced video signal a input to the input terminal 1 is input to the A / D converter 2, and is sequentially sampled at the timing of the write clock d and converted into digital data. By sequentially writing the digital data in the memory 3 at the timing of the reset pulse c, the data in the memory 3 becomes each sample data of the video signal waveform starting from the trailing edge of the horizontal synchronizing signal. This data is sequentially read according to the reference clock e at the timing of the reference reset pulse f, and the D / A converter 7
When converted to an analog signal, the output h is a waveform in which the horizontal synchronizing signal trailing edge of the reproduced video signal a is used as a starting point and is delayed in time. This time delay is the time required for the A / D conversion, memory writing / reading, and D / A conversion. Input this delay waveform into the replacement circuit 10,
Therefore, the composite sync signal g generated separately from the composite sync signal of the waveform h is replaced with its trailing edge. Since the composite synchronizing signal g is formed based on the reference oscillator 8, its waveform is regular. Further, since the waveform g is not only a horizontal sync signal but also a composite sync signal including a sync signal in the vertical blanking interval, it is possible to replace the horizontal sync signal of all reproduced video signals with a regular waveform.

In the conventional configuration as described above, the time width of the replaced horizontal synchronizing signal is formed in advance by the synchronizing signal generating circuit 9 to a standard value. For example, in the NTSC system, the standard time is 4.7 μsec. This time width does not necessarily match the time width of the horizontal synchronizing signal of the original reproduced video signal. Therefore, the video signal waveform with the sync signal in which the trailing edge of the sync signal is matched and replaced, the leading edge of the horizontal sync signal does not always match the leading edge of the original sync signal, and there is a deviation. Occurs.

On the other hand, in the image display on the television screen, the display operation is performed based on the front edge of the sync signal. Therefore, with the video signal obtained with the above configuration, there is a problem that the display image becomes an image that is moved left and right by the time difference of the shift.

The present invention solves the above-mentioned problems. While the time axis error correction is performed with the trailing edge portion of the horizontal synchronizing signal as a reference, the leading edge portion of the synchronizing signal of the obtained video signal waveform is the same as the above. An object of the present invention is to provide a time error correction device that matches the leading edge of the synchronization signal.

Means for Solving the Problems According to the present invention, in order to achieve the above-mentioned object, a writing means for writing a first video signal input to a memory, a synchronization signal generating means for generating a reference composite synchronization signal, and a first memory. The video signal of is read at the timing of the reference composite sync signal,
A reading means for outputting as a second video signal and a time axis for outputting a third video signal in which the trailing edge portion of the composite sync signal of the second video signal is replaced with a phase-adjusted reference composite sync signal for replacement. The time axis correction means includes a correction means and a width detection means for detecting a time width of the horizontal synchronization signal of the second video signal and outputting a control signal corresponding to the width, and a reference composite synchronization with the control signal. Phase adjusting means for adjusting the time width of the horizontal synchronizing signal in the signal at the front edge thereof.

The present invention has the above-mentioned configuration, and the second read from the memory
The horizontal sync signal is separated from the video signal of, the pulse width of the separated horizontal sync signal is measured, the difference from the normal sync signal width is detected, and the horizontal sync signal of the second video signal is always detected by the detected difference signal. The leading edge of the reference composite sync signal for replacement is set so as to coincide with the leading edge of, and is output as the third video signal.

Embodiment An embodiment of the present invention will be described below with reference to FIG.

In the figure, a horizontal sync signal separation circuit (HSS) 14, a write clock generation circuit (W-CLK) 15, a write reset pulse generation circuit (W-RST) 16, an A / D converter (A / D) 13, Memory 17, D / A
The converter (D / A) 20, the reference oscillator 18, the synchronizing signal generating circuit 19, and the replacement circuit 24 perform the same functions and operations as those shown in the conventional example of FIG. 3, and their explanations are omitted. . Further, the A / D converter 13, the horizontal synchronization signal separation circuit 14, the write clock generation circuit 15, and the write reset pulse generation circuit 16 constitute the writing means 30, and the reference oscillator 18 and the synchronization signal generation circuit 19 synchronize with each other. The signal generating means 32 is configured to include the synchronizing signal generating means 32 and the D / A.
The converter 20 constitutes the reading means 31, and a horizontal synchronizing signal separation circuit
21, the width detection circuit 22, the phase adjustment circuit 23, and the replacement circuit 24 constitute the time axis correction means 33.

In the embodiment of the present invention, means newly provided in comparison with the conventional example are a horizontal synchronizing signal separating circuit 21, a width detecting circuit 22 and a phase adjusting circuit 23.

The horizontal sync signal separation circuit 21 separates the horizontal sync signal I included in the video signal output H of the D / A converter 20 and inputs it to the width detection circuit 22. The width detection circuit 22 detects the time width of the horizontal synchronizing signal I and inputs a control signal corresponding to the width to the phase adjustment circuit 23. The phase adjusting circuit 23 receives the control signal and adjusts the time width of the horizontal synchronizing signal in the reference composite synchronizing signal G generated in advance at the leading edge thereof,
Reference composite sync signal J equal to the time width of horizontal sync signal I
Is output.

The operation of the above configuration will be described with reference to FIGS. 1 and 2. However, FIG. 2 shows the output waveform in each circuit block of FIG. 1, and the same reference numerals are given to the same signals. This operation principle is the same as that of the conventional example in that the horizontal synchronizing signal having a disturbed waveform of the reproduced video signal is replaced with another horizontal synchronizing signal having a well-shaped waveform. However, the horizontal synchronizing signal to be replaced is improved as compared with the conventional example. In this replacement operation, the playback video signal is delayed by more than the width of the horizontal sync signal to perform the waveform operation.The delaying means is that the playback video signal is once A / D converted and written to the memory, and then the memory is read again. The process of D / A converting and reproducing the waveform is the same as in the conventional example.

The reproduced video signal A input to the input terminal 12 is the A / D converter 1
The data is input to 3 and sequentially sampled at the timing of the write clock D to be converted into digital data. Sequential memory of the digital data at the timing of reset pulse C
By writing to the memory 17, the data in the memory 17 becomes each sample data of the video signal waveform starting from the trailing edge of the horizontal synchronizing signal. This data is sequentially read according to the reference clock E at the timing of the reference reset pulse F, and the D / A converter 20
When converted to an analog signal, the output H becomes a waveform in which the waveform of the reproduced video signal A starting from the trailing edge of the horizontal synchronizing signal is delayed in time. This time delay is the time required for the A / D conversion, memory writing / reading, and D / A conversion. The delayed waveform is input to the replacement circuit 24, and the composite synchronizing signal J having the waveform H is replaced therewith by the composite synchronizing signal J which is generated separately. The composite sync signal J is the phase adjustment circuit 23 that determines the time width of the horizontal sync signal in the reference composite sync signal G formed based on the reference oscillator 18.
Is adjusted to be equal to the time width of the horizontal synchronizing signal of the reproduced video signal at the leading edge thereof. Therefore, the output of the replacement circuit 24 is such that the trailing edge of the horizontal sync signal is equal to the trailing edge of the original horizontal sync signal, and its leading edge is also equal to the leading edge of the original horizontal sync signal. Is natural.

It should be noted that this time width adjustment may be adjusted including timing deviations due to other causes not described above, and it is not always best to make the time widths equal. Therefore, the function of adjusting the time width of the horizontal synchronizing signal in synchronization with that of the reproduced video signal is important. Since the composite synchronizing signal J is formed in advance, its waveform is regular. Further, since the waveform J is not only a horizontal sync signal but also a composite sync signal including a sync signal in the vertical blanking interval, the horizontal sync signal of all reproduced video signals can be replaced with a regular waveform.

As described above, according to the time-axis error correction apparatus of the embodiment of the present invention, the horizontal sync signal width detection circuit and the phase adjustment circuit of the reproduced video signal are provided to adjust the time width of the horizontal sync signal in the replaced composite sync signal. By doing so, the timing of the leading edge of the horizontal synchronizing signal can be made the same as that of the original playing video signal, even though the waveform operation is performed with the trailing edge of the horizontal synchronizing signal of the reproduced video signal as a reference. .

EFFECTS OF THE INVENTION As is apparent from the above embodiments, the present invention is a time axis correction means for replacing a composite sync signal of a reproduced video signal with a composite horizontal sync signal separately provided with reference to the trailing edge of the horizontal sync signal. A means for adjusting the time width of the horizontal sync signal in the composite sync signal to be replaced is provided, and the timing of the leading edge of the horizontal sync signal of the playback video signal whose time axis is corrected is made equal to the timing of the original playback video signal. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis error correction device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing output waveforms of each block of FIG. 1, and FIG. 3 is a conventional time axis error correction device. A block diagram and FIG. 4 are waveform diagrams showing the output waveforms of the blocks of FIG. 12 ... video signal input terminal, 17 ... memory, 19 ... synchronization signal generation circuit, 22 ... width detection circuit, 23 ... phase adjustment circuit,
24 ... Replacement circuit, 25 ... output terminal, 30 ... writing means, 31 ... reading means, 32 ... synchronous signal generating means, 33 ...
Time axis correction means.

Claims (1)

[Claims] 1. A writing means for writing the input first video signal in a memory, a sync signal generating means for generating a reference composite sync signal, and a synchronization signal generating means for generating the reference composite sync signal from the memory. A reading means for reading out at a timing and outputting it as a second video signal, and a third synchronizing means which replaces the composite synchronizing signal of the second video signal by matching the trailing edge portion with the reference composite synchronizing signal whose phase is adjusted. A time axis correcting means for outputting a video signal, wherein the time axis correcting means detects a time width of the horizontal synchronizing signal of the second video signal and outputs a control signal corresponding to the width. And a phase adjusting means for adjusting the time width of the horizontal sync signal in the reference composite sync signal at the leading edge thereof with the control signal, and the time width of the horizontal sync signal of the third video signal is the second width. Video signal Time base error correcting apparatus characterized by being adjusted by the duration of the horizontal synchronization signal.