JPH0814609B2 - IC test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for performing a functional test of an IC, and more particularly, to an automatic timing error generated when a plurality of test signal patterns are output or an output result of an IC under test is judged. The present invention relates to an IC test device that has a function of dynamically correcting.

2. Description of the Related Art As semiconductor integrated circuit technology advances, the density and speed of ICs are advancing, and it is desirable to increase the number of pins that can be tested and the test speed for IC test equipment that tests these ICs. . The time required to correct the timing error increases in proportion to the increase in the number of test pins. In addition, since the test speed is improved, the test timing is inevitably required to be highly accurate, and more time is required to correct the timing error.

Normally, the IC test equipment has the function of supplying the test signal pattern for each test pin and judging the output result of the IC under test (this hardware is called pin electronics). Two to four independent timing signals are required to define the rising and falling timings of the signal waveform.
The comparison circuit that determines the output result of <1> requires a timing signal for defining the determination timing. The number of timing signals to be corrected is proportional to the number of timing signals per pin and the number of test pins, and is 1000 or more in a commercially available multi-pin tester (256 pins).

In the conventional IC test equipment, the main controller with minicomputer class capability collectively controls the entire IC test equipment including the pin electronics group, and executes the above-mentioned timing error correction serially for each pin. Was there. Further, a reference timing signal generator is provided as a time standard in the above timing error correction, and it is connected to one pin electronics to be corrected, and the correction is executed by switching this with a switch.

Problems to be Solved by the Invention As described above, in the conventional IC test apparatus, the timing error correction can be executed only serially for each pin, which requires a great deal of time, which increases test pin count and increases test efficiency. It was a big problem.

Means for Solving the Problems The present invention was devised to solve the above problems, and one of a test timing generating circuit and a test timing adjusting circuit, a test pattern supplying circuit and a test result judging circuit. In each of the input / output channels, each of the input / output channels is divided into two or more groups in an IC test device that supplies a test signal pattern to the IC under test and judges whether the response result of the IC under test is good or bad. A controller that is installed for each division unit when divided, and that performs error measurement between the test pattern supply timing and the test result determination timing in the installation unit, and performs calculation and control related to error correction, and the time in the timing error measurement. A standard reference timing signal generator and all the test result judging circuits which output signals of the reference timing signal generator. It is characterized in that it is provided with means for simultaneously distributing and supplying to the input end of.

In the IC test apparatus according to the present invention, the output signal of the reference timing signal generator provided as a time standard for timing correction is simultaneously distributed and supplied to the pin electronics group, and the pin electronics group is divided into two or more groups. Each division unit has a controller that can operate independently. The controller can perform timing error measurement in each block and calculation and control related to error correction. With this configuration, the transmission of the reference timing signal and the accumulation of the response result in the pin electronics can realize completely parallel operation between the test pins, and the determination of the response result and the setting of various conditions on the pin electronics according to the determination result, etc. In the processing involving the controller, parallel operation can be realized between the divided blocks.
The processing related to the controller in the divided blocks is serial processing, but the processing time is reduced to 1 / the number of divided blocks or more as compared with the conventional apparatus in which all the processing related to the timing correction described above is executed by serial processing. can do. For example, 4 pins / block to 16 in a tester with an operating rate of 100 MHz and a total of 256 test pins
When the number of pins / blocks (number of divisions 64 to 16) is taken, assuming that the number of reference timing pulse transmission bits and the controller clock rate are 10 Kbit and 10 MHz, the processing time is 1/200 to 1 / It can be greatly shortened to around 100. Embodiments will be described below with reference to the drawings.

Embodiment FIG. 1 shows an embodiment of a timing system of an IC test apparatus according to the present invention. FIG. 2 shows a configuration example of pin electronics of the IC test apparatus according to the present invention. The waveform shaping circuit 3, the pattern generation circuit 7, and the driver circuit 4 shown in FIG.
Of the test pattern supply circuit A, the comparison circuit 5, the test result determination circuit B of the comparison result storage circuit 6, and the operation timings of the test pattern supply circuit A and the test result determination circuit B. N pieces of pin electronics 9-1 to 9-n having each test unit group of the timing generation circuit 2 as a basic constituent element are prepared corresponding to the input / output pins 1-1 to 1-n of the IC under test. (Fig. 1). The pin electronics is divided into m blocks as one unit, and the controller 8 is connected to each block S1 to Sk via the intra-block bus 100 with the intra-block test unit group. On the other hand, in order to correct the timing error in the generation of the test signal pattern and the response result judgment of the IC under test, the reference timing signal generator 11 serving as the time reference at the timing error correction is prepared, and the reference timing signal generator 11 is provided. The output of the above can be simultaneously distributed and supplied to the signal line group from all the pin electronics 9 to the input / output pins of the IC under test by the signal distributor 14. Generation of test signal patterns required for test execution and IC under test in each pin electronics 9-1 to 9-n
Response Result Judgment Operation Cycle and Reference Timing Signal Generator
The clock signal that defines the 11 operating cycles is the rate generator.
Distributed from 10 at the same time. Furthermore, the controller 8
-1 to 8-k, the rate generator 10, and the reference timing signal generator 11 are connected to the main controller 1 via the host bus 200.
Connected with 5.

The test signal pattern is generated as follows. That is, the transmission rate of the test signal pattern is the rate generator.
Waveform shaping timing edges 2-a to 2-d determined by the clock frequency of 10 and set in the timing generation circuit 2.
The output timing of the test signal pattern determines the rising and falling start times of the waveform in each cycle, and the pattern mode and level in each cycle, for example, RZ (Return
to Zero) signal low level and NRZ (Non-Return to Ze)
ro) The high level of the signal is specified by the waveform shaping circuit 3 based on the output data of the pattern generation circuit 7,
The shaped test signal pattern is sent from the driver circuit 4 to the input pin of the IC under test connected thereto.

On the other hand, the response result of the IC under test to the input of the test signal pattern is determined as follows. That is, the comparison circuit 5
The expected value level of the response result of the IC under test is set to one input, and the output pin of the IC under test is set to the other input (simply set to the intermediate level of the expected output signal of the IC under test). The signal levels of both inputs are compared at the output timing of the response result determination timing edge 2-e that is connected and set in the timing generation circuit 2, and the result is the comparison result storage circuit 6
Is accumulated in

The output timing of the test signal pattern and the DUT may vary depending on the characteristics of each test unit, the length of the connecting line between the test units, and the fluctuations in the ambient temperature and power supply voltage.
The IC response result judgment timing varies from pin to pin. These timing error corrections can be realized by adjusting the signal that defines the above-described test operation timing with respect to one time reference, that is, the timing edges 2-a to 2-e generated by the timing generation circuit 2. As the reference timing signal generator 11 serving as a time reference when correcting the timing error, a highly accurate signal generation source whose output delay time timing is calibrated is used.

First, in each of the pin electronics 9-1 to 9-n, the reference voltage of the comparison circuit 5 is set in advance to a voltage level to be compared (for example, an intermediate level of the input signal) by the control of the block controller 8 of the block to which each controller belongs. Then, the switch 18 is opened, the switches 16 and 17 are connected, the reference timing signal generator 11 and all the pin electronics are connected, and the timing error correction process is prepared.

Next, in each pin electronics, based on the reference timing signal input to the comparison circuit 5 via the signal distributor 14 at the same time for all pins, the test result determination timing edge 2-
Go to error correction of e. The timing of the adjusted edge 2-e is set to a certain value, and the reference timing signal generator
The output timing of 11 is scanned in the vicinity of the timing set value of the edge to be adjusted, the timing at which the two match is detected by the comparison circuit 5, and this is stored as the skew zero point timing. The error of the test result determination timing edge 2-e is given by the difference between the skew zero point timing and the setting timing of the adjusted edge, and this is stored as an offset value in the comparison result storage circuit 6, for example.

Next, the switch 18 is connected, the reference IC is not connected and the reference timing signal generator 11 sends the reference timing signal to all the pins, and the reflected from the end point of the signal line from each pin electronics to the IC under test. The reference timing signal is input to the comparison circuit 5. When the reference voltage applied to the comparison circuit 5 is, for example, 1/4 and 3/4 of the input signal level, the test result is obtained when the rising time or the falling time of the input waveform caused by reflection is changed. It can be obtained from the timing difference of the skew zero point detected by scanning the timing edge for determination. Since the timing difference is equal to the propagation delay time that travels back and forth in the signal line, the signal line length between the pin electronics and the IC under test can be measured by the above procedure, and the difference between the measured value and the reference value can be calculated by using the offset value of the signal line length. For example, it is stored in the comparison result storage circuit 6.

Next, using the test result determination timing edge 2-e after the timing error measurement as the reference timing, the error measurement of the test pattern supply timing edges 2-a to 2-d is sequentially performed. The timing of the adjusted edge is set to a certain value, and the timing of the reference test result determination edge is scanned to obtain the timing skew zero point of both of them by the comparison circuit 5. The error of the test pattern supply timing edge can be measured by obtaining the difference between the zero point timing and the setting timing of the adjusted edge, and further adding an offset value corresponding to the error of the test result determination timing edge to this value. Is stored in the comparison result storage circuit 6, for example.

Timing without error can be generated by subtracting various timing error data obtained by the above operation from the timing setting data as offset values.
For example, when setting the timing of the test pattern supply edge, the error amount of the edge and the pin electronics-
The output timing of the edge may be selected so as to generate the timing obtained by subtracting the inter-IC line length error amount from the timing setting value. Also, when setting the test result determination timing edge, the error amount of the edge and the pin electronics-
The output timing of the edge may be selected so as to generate the timing obtained by subtracting the line length error amount between the ICs under test from the timing setting value.

The following procedure is repeated to detect the zero-skew point of the test result determination timing edge.

That is, (1) reference timing edge timing setting, (2) adjusted edge timing setting, (3) pattern output, (4) comparison circuit response result accumulation, (5) response result reading, (6) response Zero skew result judgment,
(7) Timing change of reference timing edge, (8)
Calculation of the timing error amount, and (9) storage of the timing error amount. However, pin electronics-under test
Step (2) is not required when measuring the signal line length between ICs.

The output of the reference timing signal generator 11 is used as the reference timing edge in the error measurement of the test result determination timing edge. Therefore, in the above procedure,
(1), (3), (4), and (7) can perform parallel processing between test pins, and procedures (2), (5), (6), (8), and (8) involving the processing of the controller 8 are involved. In 9), parallel processing is performed between blocks. On the other hand, since the signal line length between the pin electronics and the IC under test and the test pattern supply timing edge error measurement use the test result determination timing edge as the reference timing edge, steps (1) and (7) are performed between blocks. It becomes parallel processing.
Since dynamic fluctuations such as jitter occur at both the rising and falling edges of the adjusted edge and the reference timing edge, the skew zero point is usually judged from Kbit to 100Kbi.
A timing signal pattern of length t is added, and the skew zero point is determined when the number of bits to be the low level output or the high level output of the comparison circuit is close to 50% of the input bit number. For example, when the reference signal pattern length is 10 Kbits in a tester with an operation rate of 100 MHz, the time required for the above procedure (3) is 100 μs. On the other hand, if microprocessors are applied to the main controller 15 and the controller 8 and both clock rates are set to 10 MHz, the processing time for one instruction is 0.5 to
It will be about 1 μs. Of the parallel processing (1), (3), (4) and (7) between the test pins, the processing (1), (4) and (7) involving the controller is about 6 instructions at most. Mu. Therefore, the time required for the parallel processing at the test pins is almost the sending time of the reference signal pattern and is estimated to be 100 μs. Parallel treatment between blocks (1), (2), (3),
Since (5), (6), (7), and (8) require about 10 instructions per pin, the processing time is estimated to be about 5 to 10 μs under the above conditions.

Therefore, when the number of pins per divided block is m, the processing time required for zero-skew comparison between one timing set value of one timing edge of all pins and the reference timing is
(100 + 10m) μs. For example, with 4 pins / block to 16 pins / block configuration, processing time is 140 to 260μ.
It is about s. 1 if performed by simple serial processing
The processing time required per pin is (100 + 10) μs, which is a multiple of the number of pins. For example, a multi-pin tester with 200 to 500 pins requires 20 to 50 ms, and the processing according to the present invention requires 100 to 2
00 times faster speed can be realized.

In this embodiment, the case in which the timing generation circuit 2 is provided for each pin has been described. However, when the timing generation circuit is shared by all pins, the timing generation circuit 2 in FIG. 1 is replaced with a timing adjustment circuit. By performing the procedure described above, the same timing correction can be realized. As described above, the controller 8 which is a component of the present invention only needs to have the ability to perform simple processing such as data transfer, data operation, comparison, etc., and is a low-priced one-chip chip of 8 to 16 bjt. A microprocessor is enough.

According to the present invention, the signal from the reference timing signal generator 11 is simultaneously supplied to all pin electronics by the signal distributor 14, and the reference timing signal generator-
Timing errors also occur due to variations in the signal line length between pin electronics, but by configuring the signal distributor 14 as described below, the errors can be suppressed to a small level. The signal distributor must carry out signal distribution corresponding to the number of test pins with the same signal amplitude as that of the signal source. This is, for example, one of the embodiments of the signal distributor 14 in the present invention shown in FIG. As shown in the figure, it can be realized by connecting OR logic gates with one input and multiple outputs in a tree shape. For example, if an LSI such as a gate array with a gate delay time of about 100 ps is used and a logic gate with one input and two outputs is used. Even with a 1: 1000 distribution, each signal path can be configured by connecting 10 stages of gates in series. Therefore, if the layout is such that the connection wiring length between the logic gates is the same, even if there is a large variation of about 5% in the gate delay and the inter-gate connection wiring delay, the variation of each signal line length is suppressed to about 50 ps. be able to. The total timing accuracy guaranteed by the current LSI tester is ± 500 ps or more, and the above variation in signal line length does not pose a problem in terms of accuracy.

EFFECTS OF THE INVENTION As is apparent from the above description, in the IC test apparatus according to the present invention, the timing correction processing is performed by the function of distributing and supplying the reference timing signal to all pins simultaneously and the function of the controller group installed in the divided block unit. Since most of the processing can be performed in parallel, the time required for timing correction can be greatly reduced compared to the conventional serial processing. For example, with a 200-500 pin tester, 4 to 16 pins /
When the block structure is adopted, the processing time is shortened to about 1/100 to 1/200.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a timing system of an IC test apparatus according to the present invention. FIG. 2 is a block diagram showing an embodiment of the pin electronics of the IC test device according to the present invention. FIG. 3 shows an embodiment of a signal distributor which is a component of the IC test apparatus of the present invention. 1 ... IC under test 1-1 to 1-n ... Input / output pin 2 ... Timing generation circuit 2-a to 2-d ... Test pattern output timing edge signal 2-e ... Test result determination timing Edge signal 3 ... Waveform shaping circuit 4 ... Driver circuit 5 ... Comparison circuit 6 ... Comparison result storage circuit 7 ... Pattern generation circuit 8-1 to 8-k ... Controller 9-1 to 9-n ... Pin electronics 10 …… Rate generator 11 …… Reference timing signal generator 14 …… Signal distributor 15 …… Main controller 16,17 …… Switch 18 …… Switch 20-1 to 20-n …… Logic gate A… … Test pattern supply circuit B …… Test result judgment circuit S1 to Sk …… Divided block a …… Input end b-1 to bm …… Output end 100 …… Internal bus 200 …… Upper bus

Claims (1)

[Claims] 1. An IC under test having one of a test timing generating circuit and a test timing adjusting circuit, a test pattern supplying circuit and a test result judging circuit for each input / output channel.
Supply of test symbol pattern to IC and IC under test
In the IC test device for judging the quality of the response result, the input / output channel is installed for each division unit when the input / output channel is divided into two or more groups, and the test pattern supply timing and the test result determination timing in the installation unit are set. Error measurement and controller for performing calculation and control relating to error correction, a reference timing signal generator serving as a time standard in the timing error measurement, and an output signal of the reference timing signal generator for all the test result determination circuits. An IC test device, characterized in that the input end of the device is provided with means for simultaneously distributing and supplying.