JPH0814790B2 - Processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital arithmetic processing technique and a technique particularly effective when applied to a floating point arithmetic system. For example, the present invention is applied to a digital signal processor capable of floating point arithmetic. And effective technology.

[Prior Art] Conventionally, in a processor such as DSP (Digital Signal Processor) HD 61810 manufactured by Hitachi, Ltd.,
It has an arithmetic unit as shown in FIG. 3 so that floating point addition and subtraction can be performed. That is, the two floating point data A ₁ and A ₂ to be operated are input data registers.
The data is input to 1a and 1b, and the magnitude determination circuit 2 determines which data has a larger exponent part. Then, the selector 3 is switched according to the magnitude determination result, and the mantissa part of the data with the smaller exponent part is controlled to be supplied to the digit alignment circuit 4. Then, the mantissa part of the data having the larger exponent part and the mantissa part of the data having the smaller exponent part which are shifted for digit matching in the digit matching circuit 4 are supplied to the fixed-point adder / subtractor 5. Calculation is performed. Then, the calculation result is supplied to the normalization circuit 6, and if the most significant digit (MSB) below the decimal point is a positive number, a shift (movement of the mantissa part) becomes "1" and a negative number causes "0". The exponent is changed according to the shift amount and then transferred to the accumulator 7.

In addition, the floating point data A ₁ calculated by the above arithmetic unit,
A ₂ is represented as A ₁ = m ₁ × 2 ^e1 and A ₂ = m ₂ × 2 ^e2 . Here, m ₁ and m ₂ are mantissa parts, e ₁ and e ₂ are exponent parts,
m ₁ and m ₂ are numbers between -1 and 1.

[Problems to be Solved by the Invention] In the above arithmetic processor, two data A to be arithmetically operated.
If the magnitudes of the exponents of ₁ and A ₂ are different, mantissas cannot be added or subtracted as they are, so digit alignment is performed. Moreover, in this case, in order to prevent overflow of the mantissa part, the smaller exponent part is aligned with the larger exponent part. Therefore, the mantissa part is shifted to the right by e ₁ -e ₂ bits as shown in FIG. Then, after the shift, bits less than the LSB (minimum digit) of the mantissa part are truncated.

Therefore, an error (maximum 1 LSB) corresponding to the truncated bits occurs. At the same time, in the subtraction, the subtraction is executed by taking the sum of the 2's complement of the subtraction (decrementing number) A ₂ and the minuend A ₁ , but the 2's complement of the subtraction A ₂ A ₂
Is obtained by adding 1 to the least significant bit of the inverted number of A ₂ .

However, the exponent of the subtrahend A ₂ is smaller than the exponent part of the minuend A _1, 1 to the least significant bit of A ₂ in the process of calculating the two's complement of A ₂ for A ₂ is shifted by the digit combined The addition operation becomes impossible, and this also causes an error.

Therefore, let the mantissa parts of A ₁ and A _{2 be} P and X, respectively, be the inversion number of X, and () be the number after shifting and truncating for digit alignment (add 1 to the least significant bit). ), The calculation result can be obtained by approximating P−X with P− (). However, if such an approximation is performed, for example, when two numbers whose mantissas are both 0 and exponents have different sizes are subtracted, the operation result which should be 0 should not be 0. there were.

In particular, the above-mentioned errors are accumulated when a repetitive operation is performed and become a very large error.

An object of the present invention is to provide an arithmetic processing system capable of reducing an error caused by truncation due to digit alignment in floating point arithmetic.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, one bit is added to the least significant bit side of the digit matching circuit to increase the number of bits of the digit matching circuit by one more than the number of bits of the mantissa part, and this additional bit is also shifted for digit matching. And the content of the additional bits can be supplied to the adder / subtractor as carry information, and the minuend is output as it is in the preceding stage of this adder / subtractor, especially in the case of the subtraction operation, and the number of exponents is larger. If the corresponding mantissa data is a divisor, add 1 to the data and output it, and if the mantissa data corresponding to the smaller number of exponents is a divisor, provide a full adder to output the data as it is Is.

[Operation] According to the means described above, when the data of the mantissa part overflows due to the shift for digit alignment, the contents of the additional bits are supplied as carry information to the adder / subtractor, so that the bits truncated by the shift are supplied. By adding or not adding "1" to the least significant bit of the operation data in a form of rounding off, the above object of reducing the error of the floating point operation can be achieved.

In addition, in the subtraction operation, in particular, the minuend is output as it is, and if the mantissa data corresponding to the smaller number of the exponent part is the divisor, this divisor is also output as it is, thereby simplifying the configuration while maintaining the calculation accuracy. As a result, the degree of integration can be improved and the calculation speed can be improved.

[Embodiment] FIG. 1 shows an embodiment of a floating point logical operation circuit according to the present invention.

The floating point logical operation circuit of this embodiment has almost the same configuration as the floating point logical operation circuit (FIG. 3) described above.

The difference is that the digit matching circuit (right shifter) 4 has a 1-bit additional bit 4a on its LSB side, and is configured to have a 17-bit structure that is 1 bit larger than the 16-bit width mantissa part. Is output to the fixed-point adder / subtractor 5 as the carry signal C, and the full adder 8 is provided in front of the fixed-point adder / subtractor 5.

In this embodiment, the two floating point data A ₁ and A ₂ to be calculated are input to the input data registers 1a and 1b,
The size determination circuit 2 determines which data has a larger exponent part. Then, the selector 3 is switched according to the magnitude judgment result, the mantissa part of the subtraction part is bit-inverted, and the mantissa part of the smaller data of the exponent part is the digit matching circuit 4.
Is supplied to. Here, when the data supplied to the digit matching circuit 4 is the minuend A _1, that is, when the exponent part e ₁ of the minuend A ₁ is smaller than the exponent part e ₂ of the subtraction A ₂ (e ₁ <
In e ₂ ), the mantissa part a ₁ of the minuend A ₁ is supplied to the digit matching circuit 4 and right shift is performed. Furthermore, (bits inverted value selector 3) a ₂ mantissa subtrahend A ₂ is supplied to the full adder 8, and 1 is added to the least significant bit on the basis of a signal from the magnitude determination circuit 2. That is, the mantissa part a
_{The 2} 's two's complement is calculated. Then, the two's complement of the mantissa part a ₂ and the mandable A which are digit-matched by the digit-matching circuit 4 are used.
₁ of the mantissa a _1, is supplied to the fixed point unit 5,
The sum of the two is taken. Then, the calculation result is taken into the magnitude determination circuit 2, supplied to the normalization circuit 6 together with the exponents e ₁ and e ₂ , and normalized, and is stored in the accumulator 7.

On the other hand, when the data supplied to the digit alignment circuit 4 based on the control signal from the magnitude determination circuit 2 is the subtraction A ₂ (value bit-inverted by the selector 3), that is, the subtraction A ₂
In the case towards the exponent e ₂ is smaller than the exponent e ₁ of the minuend _{A 1 (e 1> e 2} ), the right-shift mantissa a ₂ meiotic A ₂ is supplied to the digit combined circuit 4 Done. At this time, of the bits protruding from the 16-bit shifter of the digit alignment circuit 4, the bits except the most significant bit included in the additional bits are truncated. For example, as shown in FIG.
Considering the case where the bits b _{15 to} b ₀ of the mantissa part of ₂ are shifted to the right by 3 bits, b ₁ , excluding b ₂ out of the bits b ₂ , b ₁ , b ₀ protruding from the 16-bit shifter b ₁ , b ₀ is truncated and b ₂ is held in the additional bit 4a of the digit alignment circuit 4.
The bit (b ₂ ) in the additional bit 4a is supplied to the fixed point adder / subtractor 5 as a carry signal as described above.

Further, the upper 16-bit data right-shifted by the digit matching circuit 4 passes through the full adder 8 (without adding 1 to the least significant bit), and the fixed point together with the mantissa part a ₁ of the minuend A _1. It is supplied to the adder / subtractor 5.

The fixed point adder / subtractor 5 sums the two, and if it is "0" in accordance with the carry signal C from the additional bit 4a of the digit matching circuit 4, the calculation result is sent to the accumulator 7 as it is. On the other hand, if the carry signal C from the additional bit 4a is "1", 1 is added to the least significant bit of the operation data and then the operation data is sent to the accumulator 7.

As described above, in the above embodiment, since the most significant bit (b ₂ ) of the bits to be rounded down at the time of digit alignment is added to the LSB of the mantissa as a carry, the maximum value | er | max and the expected value | er of the operation error | er. | ex is represented by | er | max = 1 / 2LSB | er | ex = 1 / 4LSB. On the other hand, regarding the errors | et | masx and | et | ex due to the truncation method in the conventional arithmetic circuit (FIG. 3), if the right shift amount is set to M (≧ 1), | et | ex = 1/2 | et | maxLSB, and the relationship | er | max≤ | et | max, | er | ex≤ | et | ex always holds. That is, the calculation error is significantly reduced as compared with the conventional case.

For example, when M = 7, | er | = 1 / 2LSB, | et | max = 0.9922
= 1LSB.

Further, according to the above-described embodiment, when two numbers whose mantissas are both “0” and the exponents are different in size are subtracted from each other, the calculation result of the conventional method is ≠ 0. You will get 0.

Therefore, the arithmetic circuit of the present embodiment is most effective when applied to a signal processor such as a digital filter that repeatedly executes high-speed product-sum calculation.

An arithmetic processor having a floating-point arithmetic circuit as described above is provided with, for example, an instruction ROM (read-only memory) in which a microprogram is stored, and the microinstruction read from this instruction ROM is decoded. The respective circuits are controlled according to a predetermined algorithm by the control signal formed by the above operation, and a desired floating point operation is executed.

As described above, in the above embodiment, one bit is added to the least significant bit side of the digit matching circuit to increase the number of bits of the digit matching circuit by one larger than the bit width of the mantissa part. Since the shift is also performed for digit alignment and the contents of the additional bits are supplied as carry information to the adder / subtractor, if the data in the mantissa part overflows due to the shift for digit alignment, the additional bits By supplying the contents of to the adder / subtractor as carry information, by the action that "1" is added or not added to the least significant bit of the operation data in a form of rounding off the bits truncated from the shift, There is an effect that an error caused by truncation due to digit alignment is reduced in the floating point arithmetic.

In the subtraction operation, the minuend exponent e ₁ of A ₁ and compares the exponent e ₂ of the subtrahend A _2, particularly e ₂ is mantissa a of A ₂ by right shifting is smaller than e ₁ By not doing anything in _2, it is possible to simplify the configuration while maintaining the calculation accuracy, improve the degree of integration, and improve the calculation speed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the output of the additional bit provided in the digit alignment circuit is supplied as a carry signal to the fixed-point adder / subtractor. However, instead of forming the carry signal, the shift digit alignment circuit The error due to the truncation may be reduced by adding 1 to the least significant bit of the data according to the content of the additional bit when the value is 1 and not adding 1 when the value is 0.

In the above description, the invention mainly made by the present inventor is described as being applied to an arithmetic processor such as DSP which is a field of application which is the background of the invention, but the present invention is not limited thereto and has a floating point arithmetic circuit. It can be used for data processing devices in general.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in floating-point arithmetic, it is possible to reduce an error caused by truncation due to digit alignment.

In addition, in the subtraction operation, in particular, the minuend is output as it is, and if the mantissa part data corresponding to the smaller number of the exponent part is the divisor, this divisor is also output as it is, thereby simplifying the configuration while maintaining the calculation accuracy. As a result, the integration speed can be improved and the calculation speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a floating point arithmetic circuit according to the present invention, and FIG. 2 is an explanatory diagram showing handling of bits of a mantissa part in a digit alignment circuit of the floating point arithmetic circuit according to the present invention. FIG. 3 is a block diagram showing a configuration example of a conventional floating point arithmetic circuit, and FIG. 4 is an explanatory diagram showing how to handle bits of a mantissa part in a digit matching circuit of the conventional floating point arithmetic circuit. 1a, 1b …… Input data register, 2 …… Size judgment circuit,
3 ... Selector and bit-reversal circuit for subtraction, 4 ... Digit matching circuit, 4a ... Additional bits, 5 ... Operation unit (fixed point adder / subtractor), 6 ... Normalization circuit, 7 ... Accumulator, 8 ... … Full adder.

Claims (1)

[Claims] 1. A first binary coded floating-point data having an n-bit width first mantissa part and a first exponent part, and a second n-bit width mantissa part and a second exponent part. An arithmetic processing device for performing addition / subtraction processing of binary-coded floating-point data of No. 2 and a magnitude determination circuit for determining the magnitude of the first and second exponent parts and obtaining the difference between the first and second exponent parts. According to the result of the magnitude determination circuit, the mantissa data corresponding to the larger one of the first and second exponents is stored in the first path in the number of the first and second exponents. The mantissa data corresponding to the smaller one is distributed to the second path, and the output of the selector circuit is received. The mantissa data is output as it is in the case of addition, and the mantissa part is the mantissa in the case of subtraction. The data is output after bit-inversion, and the mantissa data that is The bit inversion circuit that outputs the bit inversion circuit and the mantissa part data of the second path that is output from the bit inversion circuit with the width obtained by adding an additional bit of 1 bit to the least significant bit of n bits. A digit matching circuit that shifts to the right by the number of differences in the exponent part, a mantissa data of the first path output from the bit inverting circuit, and a mantissa data of the second path output from the digit matching circuit are received. , In the case of addition, each mantissa data is output as it is, in the case of subtraction, the mantissa is output as it is, and if the mantissa data of the first path is a subtraction, 1 is added to the mantissa data. A full adder that outputs the mantissa data of the second path and outputs the mantissa data of the second path as it is, and a mantissa data of the first path output by the full adder;
An arithmetic processing unit comprising: a mantissa data of the second path; and a fixed point adder / subtractor for adding one additional bit formed by the digit matching circuit.