JPH0814997B2 - Semiconductor memory circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to an ultraviolet erasable PROM type semiconductor memory circuit which can be written only once.

[Conventional technology]

Conventionally, this type of semiconductor memory circuit is encapsulated by resin,
Since molding is performed, UV erasing of program data is not possible after assembling, and programming of the memory cell part,
The read operation is checked only on the wafer, and the operation cannot be checked in the assembled state.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory circuit.

This circuit has a plurality of memory cells 1 each having a FET M ₁ having a floating gate, and when writing an operation check, the write voltage supply circuit 2 _A supplies a predetermined power supply voltage between the drain and source of the FET M _1. VPP is supplied, a predetermined write line 4 is selected by the write selection circuit 5 _A, and a predetermined write voltage V is applied to the control gate of FET M ₁ via this write line 4.
PM is applied to write data in the selected memory cell 1.

When reading the operation check, the data of the selected memory cell 1 is transferred to the sense amplifier circuit 7 _C via the read line 6.
Read by.

After the operation check, the data written for the operation check is erased by ultraviolet rays, encapsulated, molded and shipped as a finished product.

[Problems to be Solved by the Invention]

In the conventional semiconductor memory circuit described above, it is not possible to check the write and read operation defects of the memory cell 1 that have occurred after the assembly, so that they are not found until the user uses them after shipping, and the degree of mixing of defects in the shipped products is high. There is a drawback that.

An object of the present invention is to provide a semiconductor memory circuit that can reduce the degree of defective mixing of shipped products.

[Means for solving the problem]

A semiconductor memory circuit of the present invention includes a plurality of memory cells capable of erasing ultraviolet light, a write power supply circuit for generating a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and a switching signal. A first switching circuit for selecting and supplying one of the first and second power supply voltages to each of the memory cells and a predetermined memory cell of the plurality of memory cells. A plurality of write lines for writing data by a write voltage; a first write voltage for selecting one of the write lines and writing data in the selected memory cell; Second lower than 1 write voltage
Write selection circuit for generating a write voltage and a second switch circuit for selecting one of the first and second write voltages by the switch signal and supplying the selected write line. When,
A read line for reading data of each memory cell, a first sense amplifier circuit having a first logic threshold voltage for amplifying an input voltage, and a first sense amplifier circuit lower than the first logic threshold voltage. A second sense amplifier circuit which has a logic threshold voltage of 2 and amplifies the input voltage, and data of the read line is switched by the switching signal and input to one of the first and second sense amplifier circuits. And a third switching circuit for selecting the first power supply voltage, the write voltage, and the first sense amplifier circuit during normal writing and reading operations, and writing and reading data in the selected memory cell. At the time of operation check after the ultraviolet erasing and assembling, the second power supply voltage, the write voltage and the second sense amplifier circuit are selected to write and read the data of the selected memory cell and Note Cells, with the first sense amplifier circuit is configured as a said is judged non-write state the second sense amplifier circuit having a threshold voltage in the range it is determined that the write state.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment shows a FET M ₁ with a floating gate.
A write power supply circuit 2 for generating a plurality of memory cells 1 UV erasable, second lower than the first power supply voltage VPP ₁ of the first power supply voltage VPP ₁ Toko a supply voltage VPP ₂ comprises a, FETM
_A first switching circuit 3 _A that includes ₃₁ and M ₃₂ , selects one of the first and second power supply voltages VPP ₁ and VPP ₂ by the switching signal S, and supplies the selected one to each memory cell 1; A plurality of write lines 4 for selecting a predetermined memory cell of the memory cells 1 and writing data by a supplied write voltage, and a memory selected by selecting one of the write lines 4 The first write voltage VPM ₁ for writing data to the cell 1 and the first write voltage VPM 1
Write voltage and write select circuit 5 for generating a second write voltage VPM ₂ lower than VPM _1, FET M _33, signal Setsu equipped with M ₃₄ S, first and second write voltage by VPM ₁ Switching circuit for selecting one of VPM ₂ and VPM ₂ and supplying it to the selected write line 4
3 _B , a read line 6 for reading data of each memory cell 1, a first sense amplifier circuit 7 _A for amplifying an input voltage having a _first logical threshold voltage VT 1, A second sense amplifier circuit 7 _B having a _second logic threshold voltage VT ₂ lower than the logic threshold voltage VT ₁ for amplifying the input voltage, and FET M
₃₅ and M ₃₆ , and a third switching circuit 3 _C for switching the data of the read line 6 by the switching signal S and inputting it to one of the first and second sense amplifier circuits 7 _A and 7 _B. Has become.

 Next, the operation of this embodiment will be described.

FIG. 2 is a voltage / current characteristic diagram of the FET M ₁ of the memory cell 1 for explaining the operation of this embodiment.

In the unwritten state, the FET M ₁ is the curve CV _{1 in} FIG.
It has the following voltage and current characteristics.

The switching signal S is set to an active level (is an inactive level) at the time of wafer state or normal writing and reading.

When the switching signal S is set to the active level, the switching circuits 3 _{A to} 3 _C cause the first power supply voltage VPP ₁ of the write power supply circuit 2, the first write voltage VPM ₁ of the write selection circuit 5, and the The first sense amplifier circuit 7 _A is selected, the FET M ₁ is in the write state of the voltage-current characteristic shown by the curve CV ₂ in FIG. ₂ , and the first threshold value of the first sense amplifier circuit 7 _A is set at the time of reading. Value voltage VT
Whether _{1 is} written or not is determined by ₁ .

When the writing / reading operation check in the wafer state is completed, the written data is erased by ultraviolet rays and the assembly is performed.

After assembly, the switching signal is set to an active level (S becomes an inactive level), and write and read operation checks are performed.

When the switching signal is set to the active level, the switching circuits 3 _{A to} 3 _C cause the second power supply voltage VPP ₂ of the write power supply circuit 2, the second power supply voltage VPM ₂ of the write selection circuit 5, and the second power supply voltage VPM ₂ . Sense amplifier circuit 7 _B is selected, and FET M ₁ is in a write state with a low level of voltage-current characteristics shown by the curve CV ₃ in FIG.
At the time of reading, the second sense amplifier circuit 7 _{B determines} whether to write or not based on the _second threshold voltage VT ₂ . That is, the memory cell FET M ₁ in the written state is
In the first sense amplifier circuit 7 _A , the non-writing state is determined,
In the second sense amplifier circuit 7 _B , the threshold voltage is within the range in which it is determined that the writing state.

As a result, the non-defective product is shipped without erasing, but when the switching signal S is at the active level, it is in the writing state.
The voltage-current characteristic of the FET M ₁ is the curve CV ₃ , whereas the voltage-current characteristic of the FET M ₁ is the curve CV ₂ when normal writing is performed. Therefore, the first sense amplifier circuit With 7 _A , writing and non-writing can be discriminated with a sufficient margin.

〔The invention's effect〕

As described above, according to the present invention, the operation check after assembling can be performed by providing the writing circuit and the reading circuit of two systems having different levels, so that the defective product in the shipped product is mixed. And there is an effect that the degree can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a voltage / current characteristic diagram of the FET of the memory cell for explaining the operation of the embodiment shown in the figure, and FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory circuit. 1 ... Memory cell, 2,2 _A ... Power supply voltage supply circuit, 3 _{A to} 3 _C
...... Switching circuit, 4 …… Write line, 5,5 _A …… Write selection circuit,
6 ... Read-out line, 7 _{A to} 7 _C ... Sense amplifier circuit, M ₁ , M _{31 to} M
₃₆ …… FET.

Claims (1)

[Claims] 1. A plurality of memory cells that can be erased by ultraviolet light, a write power supply circuit that generates a first power supply voltage and a second power supply voltage that is lower than the first power supply voltage, and the first signal based on a switching signal. A first switching circuit that selects one of a first power supply voltage and a second power supply voltage and supplies it to each of the memory cells, and a write voltage that is supplied by selecting a predetermined memory cell from the plurality of memory cells. A plurality of write lines for writing data, a first write voltage for selecting one of the write lines and writing data in the selected memory cell, and the first write voltage A write selection circuit for generating a second write voltage lower than the voltage, and the first and second write signals according to the switching signal.
Second switching circuit for selecting and supplying one of the write voltages to the selected write line, a read line for reading the data of each memory cell, and a first logic threshold voltage. A first sense amplifier circuit for amplifying an input voltage having a second logic threshold voltage and a second sense amplification circuit for amplifying an input voltage having a second logic threshold voltage lower than the first logic threshold voltage. A first switching circuit and a third switching circuit for switching the data on the read line by the switching signal and inputting the data to one of the first and second sense amplifier circuits. Power supply voltage, write voltage, and first sense amplifier circuit are selected to write and read data in the selected memory cell, and the second power supply voltage and write voltage are used during operation check after UV erase assembly. And select the second sense amplifier circuit The data of the selected memory cell is written and read, and the memory cell in the written state is determined as the non-written state by the first sense amplifier circuit and determined as the written state by the second sense amplifier circuit. A semiconductor memory circuit having a threshold voltage within a range.