JPH0815274B2 - Data transmission system and data transmission method between a plurality of devices - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system and a data transmission method for mutual communication between a plurality of devices, and more particularly to a voice communication between a plurality of terminals in a private telephone exchange system or other local networks. An improved system and method for transmitting and receiving digital data, including data, to and from each other.

<< Outline of the Invention >> The present invention is configured by connecting a plurality of devices by a transmission / reception transmission line. Each device has multiple time
Create a slot. One of these time slots is for a synchronization signal, the other one is for a control signal, and the remaining time slots are for data transmission / reception assigned to each device. Further, each of the devices includes a transmitting / receiving means for transmitting / receiving a signal or data when the gate is opened,
A storage unit for storing a usage state map of the data receiving time slot and a searching unit for searching an empty time slot in the map are provided.

As a result, the data transmission is ensured by using the vacant channel even when the number of devices for data transmission / reception time slots or more is connected.

《Prior art and its problems》 There are so-called star-type network system, loop-type network system, etc. in the data transmission system between a plurality of devices, but in each case, the main control device is for connection and communication between the devices. Since it is necessary, the configuration of the main controller itself becomes complicated, and the total transmission line becomes long,
There is a drawback that equipment costs are high.

Therefore, in order to solve such a drawback of the conventional system, the present applicant has filed a Japanese Patent Application No. 60-293249 dated December 27, 1985.
Proposed a new data transmission system between multiple devices.

That is, it is composed of a plurality of devices connected to each other by a transmission / reception transmission line and means for transmitting a synchronization signal at a constant cycle. Each device is a plurality of time slots divided by a number larger than the number of devices within the above-mentioned fixed period on the basis of the synchronization signal, and each time slot is used for transmitting and receiving a signal. The time length and the maximum transmission delay time of the signal between devices are included. One of these time slots is for synchronizing signals, the other is for transmitting / receiving control signals, and the remaining time slots are for receiving data devices. Means for creating such a time slot, a first gate opened in synchronization with the synchronization signal time slot, a second gate opened in synchronization with the control transmission / reception time slot, and It has a third gate opened in synchronization with a data transmission / reception time slot corresponding to the device, and means for transmitting / receiving a signal required when each gate is opened.

Such a data transmission system between a plurality of devices,
For example, it is configured by connecting n terminal devices 1 to n having a line interface I / F having a function of transmitting a synchronization signal to a transmission / reception line, and does not require a main controller.

However, in such a data transmission system between a plurality of devices, since the number of channels formed for connection, that is, the number of data transmission / reception time slots and the number of devices are the same, it is difficult to increase the number of devices to be connected. There are points to be improved.

<< Object of the Invention >> The present invention has been made under such circumstances, and it is possible to form more channels than the number of connectable channels of each device due to time slot restrictions. It is an object of the present invention to provide a data transmission system and a data transmission method for mutually increasing a plurality of devices.

<< Structure and Effect of the Invention >> In order to achieve such an object, a mutual data transmission system between a plurality of devices according to the present invention includes a plurality of devices that are mutually connected by a transmission / reception transmission line. In a mutual data transmission system between devices, each device is formed by being divided into a plurality of parts within a fixed period, and includes a time length for transmitting and receiving a signal and a maximum transmission delay time between the devices. Time slots in which one of these time slots is for synchronizing signals, the other one is for transmitting / receiving control signals, and the remaining time slots are for transmitting / receiving data corresponding to the respective devices. Time slot creating means for creating, a first gate opened in synchronization with the synchronization signal time slot, and synchronization with the control transmission / reception time slot A second gate that is opened by the user, a third gate that is opened in synchronization with the data transmission / reception time slot, a transmission / reception unit that transmits / receives a signal or data when the gate is opened, and a data reception unit. It is characterized by comprising: storage means for storing a time slot use state map; and search means for searching for an empty time slot in the map.

In addition, a method of mutually transmitting data between a plurality of devices according to the present invention is a method of mutually transmitting data between a plurality of devices, which comprises a plurality of devices mutually connected by a transmission / reception transmission line. A plurality of time slots that are formed by being divided into a plurality of parts within a cycle of and that include a time length for transmitting and receiving a signal and a maximum transmission delay time of the signal between devices, and one of these time slots is Creating a time slot for synchronizing signals, another one for transmitting / receiving control signals, and each remaining time slot for transmitting / receiving data corresponding to each device; and synchronizing with the time slots for synchronizing signals. A second gate opened in synchronization with the control transmission / reception time slot, and a second gate opened in synchronization with the control transmission / reception time slot A third gate to be opened, a step of transmitting and receiving a signal or data when the gate is opened, a step of storing a usage state map of a time slot for data reception, an empty time slot in the map And a step of searching for.

According to the present invention, each device has a usage status map by monitoring the connection status of other devices connected to the transmission / reception transmission line, and when each device transmits data, Since a free channel is searched from the map and a connection channel is formed based on the free channel data, data transmission with the number of devices equal to or more than the number of data transmission / reception time slots of each device becomes possible.

<< Description of Examples >> Examples of the present invention will be described below.

FIG. 1 schematically shows a specific configuration of a data transmission system and a data transmission method according to the present invention.

In the figure, the same P devices 1 to P (1,2, ..., i, ..., k, ..., n, ..., P) are provided on the two transmission / reception line 1 by the two-wire multi-drop system. Are interconnected by
Each of the devices 1 to P is, for example, a terminal or a telephone controlled by a computer. Each of the devices 1 to P is equipped with a line interface (I / F).
/ F has a built-in function to send out a sync signal.

For example, as shown in FIG. 2, the device 1 sends the synchronization signal S on the transmission / reception line 1 at a constant time interval T and divides the cycle T into, for example, (n + 2) smaller than the number of devices. (N + 2) consecutive time slots TSx (x is s, c, 1, 2,
,, i, ..., k, ..., n).

The synchronization signal S has a specific bit pattern as will be described later, and each of the devices 2 to P has means for forming the time slot TSx based on the detection of the synchronization signal S. , The series of time slots TSx in each of the devices 2 to P have a phase delay of the propagation time of the signal with respect to that in the device 1.

The first time slot TSs in the time slot TSx is a synchronization channel for establishing synchronization between the devices 1 to P, and the above-described synchronization signal S is the time slot TSx.
It is transmitted and received on TSs.

The second time slot TSc is a control channel for connecting or disconnecting at least two devices among the devices 1 to P, and the control signal Dc is transmitted / received in this time slot TSc. The content of the control signal Dc will be described later.

In this time slot TSc, for example, one device addresses another one device to send a connection request, and in the subsequent time slot of the synchronization T, the corresponding other device connects to another device. When the completion is answered, these two devices are connected to each other and communication is possible. In order to disconnect the two devices in the connected state, a disconnection request is issued instead of the connection request and the response is made.

The other time slots TS1 to TSn are data channels for data transmission and reception, and are time zones for transmitting data between the devices 1 to P. For example, when device i and device k are connected and transmit to each other, time slot TS
At i, device i sends out a data signal Di which device k receives, and at time slot TSk device k sends a data signal Dk which device i receives. This enables full-duplex communication of data signals and bidirectional simultaneous voice communication.

Each of these signals S, Dc, D1 to Dn has the same number of bits, for example, 10 bits, and has a time length of τb. A guard time .tau.g is provided in each time slot so that the signals transmitted from the devices 1 to P do not overlap each other on the transmission / reception line 1 due to the delay due to the propagation time. The symbol τd is the maximum propagation delay time between the two devices with the longest transmission distance.

FIG. 3 shows the transmission / reception timing of signals between two devices and the bit configuration of each signal from the device i to the device k.
An enlarged view of how Di is transmitted is shown.

The data signal Di is transmitted at the transmitting device in synchronization with the start of the time slot TSi, but the propagation delay time changes depending on the distance between the communicating devices. -Although it arrives in the slot TSi, the phase of the reception timing changes in the time slot TSi and becomes asynchronous.

To address this, the data signal Di is
Start bit ST before d8, stop bit after d8
It is formed by adding each SP, and is called an asynchronous system. Therefore, if the data bit is composed of 8 bits, the data signal Di will be 10 bits.

Signals other than the data signal Di, that is, the synchronization signal S and the control signal Dc also have the same bit configuration of the start-stop synchronization method.

FIG. 4 shows an example of a specific bit pattern of the synchronization signal S, in which all the data bits d1 to d8 are 1,
A start bit ST and a stop bit SP are added before and after this bit string.

There are various formats of the control message sent / received by the control signal Dc and the data message sent / received by the data signal Di, but as an example, HDLC (high level
What is called a data link control) is used.

As shown in FIG. 5, the HDLC freilleme type has a start flag (F) field, an address (A) field,
Control (C) field (8 bits each), information (I) field of arbitrary number of bits, 16-bit check (frame check sequence; FCS) field, and 8
It consists of a bit end flag (F) field.

The start and end flag fields identify the start and end of the frame. The start flag starts checking for a transmission error by a CRC (cyclic redundancy check) method, and the end flag ends.

The address field is used to specify the address of the transmission partner device. For example, when device i communicates with device k, the address of device k is set in the address field of the control message sent from device i to device k. When the device k responds to this control message, the address of the device i is set in the address field of the response control message.

When data transmission / reception is performed between both devices after the connection with the devices i and k is completed, the address field of the data transmission follows the rules of the HLDC procedure.

The control field calls from the own device to the other device,
It is used for the corresponding classification corresponding to the call from the partner device to the own device.

The information field is different between the control message and the data message. In the control message, as shown in Fig. 6, the information field is always
It consists of 16 bits. That is, the first 8 bits b11
~ B18 indicates the address of the own device, of the following 8 bits, the first bit B21 is a connection request, the second bit B22 is an open request (connection disconnection), the fifth bit B25 is a connection completion, and the sixth bit is a sixth bit.
Bit B26 indicates completion of opening, and seventh bit B27 indicates busy (communication). Since the address of the own station is included in the information field, the partner device can know the time slot position to be received corresponding to this address.

In the data telegram, data to be transmitted is embedded in the information field, and the number of bits changes depending on the length of the data.

In the check field, the result of arithmetically calculating the numerical value expressed by all the binary bits in the frame by the CRC method for error checking is set. The receiving side performs the same calculation and compares it with the value of the sent inspection field to check whether a transmission error or the like has occurred.

Then, as described above, the control signal Dc and the data signal Ci include the start bit ST and the stop bit SP.
Although it has a 10-bit configuration, for example, the control message is
Since it consists of 64 bits, as shown in FIG.
By dividing the control signals Dc1 to Dc8 and continuously transmitting them over eight cycles, one control message is transmitted and received.

FIG. 7 shows one configuration example of one of the above-mentioned devices 1 to P.

The MPU 5 is for performing transmission data creation, reception data decoding, connection control, communication processing of the upper CPU, etc., as well as the control described below.

The MPU 5 has a ROM 7 storing a program for operating the MPU 5, data required for control such as the numbers of the respective devices 1 to P, data to be transmitted, and RAM 9 storing received data,
Interface with upper CPU 11, time slot TSx
Channel specification register 13, which specifies each channel of
Transmit / receive buffer 15, 17, transmit / receive buffer 1 for data signal Di
9,21 are connected to each other via various buses.

Further, the RAM 9 has an area for storing a map as shown in FIG. That is, it has addresses (addresses) 1 to n corresponding to the number of channels of the system, and the addresses are assigned to one time slot TS1 to STn. For example, when one frame is assigned to n channels, address 0 is time slot TS0, address 1 is time slot TS1, and address n is time slot TSn.

Under the control of the MPU5, the connection state of the device is analyzed, and when it is found that the time slots TSi and STk are used, the i and k addresses of the RAM9 become "1", and when they are released, "0" It will be.

The sync signal detection circuit 23 detects the sync signal S shown in the specific bit pattern of FIG. 4 described above, and includes, for example, an AND circuit to which 8-bit data d1 to d8 are input, and a time slot is generated. Connected to circuit 25.

The time slot generation circuit 25 time-divides (n + 2) time slots TSx within the period T described above by the detection signal from the synchronization signal detection circuit 23 under the control of the MPU 5.
Is generated and output to the time control 27. That is, the number of data channels in the time slot is less than the number of devices.

The channel control register 13 controlled by the MPU 5 is connected to the time control 27, and the logical sum of the output signal from the time slot generation circuit 25 and the control signal output from the channel control register 13 according to the instruction of the MPU 5. AND circuit that outputs the gate control signals G1 to G8
Is generated. That is, the gate control signals G1 to G6 are output at the channel timing when the output signal from the time slot generation circuit 25 and the channel designating signal from the channel designating register 13 match, and the gate 2 which will be described later is operated.
9,35,37,41,45,47 are opened and closed.

The synchronization signal detection circuit 23 is bus-connected to a demodulation circuit 31 via a gate 29. The demodulation circuit 31 converts a Manchester code or the like from the transmission / reception line 1 into an NRZ signal, and a media interface 33. Are connected to the transmission / reception line 1.

The control signal reception buffer 17 and the data signal reception buffer 21 are also bus-connected to the demodulation circuit 31 via the gates 35 and 37.

The sync signal generation circuit 39 controls the sync signal S under the control of the MPU 5.
Is generated and is connected via a gate 41 to a modulation circuit 43 for converting an NRZ code into a Manchester code. The modulation circuit 43 is connected to a transmission / reception line 1 via a media interface 33.

The control signal transmission buffer 15 and the data signal transmission buffer 19 are connected to the modulation circuit 43 via gates 45 and 47.

Input side point A of the demodulation circuit 31 and output side B of the modulation circuit 39
The carrier detection circuit 49 connected to the point detects whether or not data is transmitted / received in each time slot TSx, and is bus-connected to the MPU 5.

Further, the carrier detection circuit 49 has a signal collision detection circuit for detecting the presence or absence of a data signal from this device and a data signal from another device to detect a signal collision on the transmission / reception line 1. Therefore, when the signals collide on the transmission / reception line 1, the detection signal is transmitted to the MPU 5.

Next, an example of the operation of the data transmission system of the present invention will be described based on the flowcharts shown in FIGS.

When the power is turned on and the device is turned on, the MPU5 initializes the peripheral circuits in step 100 as shown in FIG. 9, and sends an address data request command in order to receive the address data of the device from the host CPU. -Output through the interface 11. The address data received from the host CPU is stored in the RAM 9 and used for data transmission with other devices.

In the following step 101, the presence / absence of the synchronization signal S from the other device on the transmission / reception line 1 is determined by reading the register in the carrier detection circuit 49 or the like. Step 101
When NO is NO, in step 102, the MPU 5 outputs the synchronization signal S from its own device, so that the MPU 5 outputs the channel designation register 13
The gate control signal G2 is output from the time control 27 by the input of this command, and the gate 41 is opened to output the sync signal S from the sync signal generating circuit 35, and the process returns to step 101.

At this time, although not shown, it is determined whether or not the synchronization signal S has a signal collision at the time of output on the transmission / reception line 1, and if there is a collision, data output is stopped for a certain period of time.

If step 101 is YES, step 103 is executed, the data of the carrier detection circuit 49 is searched to determine whether or not the control channel is used, and if NO, a data signal is output to the control channel. And the wait state is executed in step 104 and step 1
Move to 03.

If YES at step 103, the MPU 5 goes to R at step 105.
Receives current map data from other devices using the control channel to create a map in AM9.

That is, any other device is selected, the map data request information is stored in the control signal transmission buffer 15 and the control signal transmission command is given, and the time control 27 outputs the open signal of the gate control signal G4, and the control signal. A map data request signal is placed on the control channel and output from the transmission buffer 15 onto the transmission / reception line 1.

The selected other device sends the map data in the RAM 9 using the control channel.

Next, the device receiving the channel map data creates a map in the RAM 9 in its own device, but there is a possibility that an error may occur in the data from one location. The map data is requested, and it is determined whether or not they match. If YES, the map is input as if they match. If NO, then the map is returned to step 105 and this is repeated.

Next, the procedure during standby and when there is a connection request from another device to the own device will be described with reference to FIG.

During standby, the MPU 5 gives a control data signal command to the channel designation register 13 to open the gate 35 and put it in the input state regardless of whether the control channel has data.

In step 200, the MPU 5 monitors the carrier detection circuit 49 to determine whether or not data is output to the control channel from another device. If NO, the process returns to step 200. When step 200 is YES, the MPU 5 inputs the data from the control signal reception buffer 17 and stores it in the RAM 9 in step 201, and analyzes the received data stored in the RAM 9 after inputting all the data.

Then, in step 202, which channel the device is using for transmission / reception is stored in the channel map area in the RAM 9 as a connection state map, and in step 203, the MPU 5 sets the address A in FIG. It is determined whether the address is In the case of NO, the process returns to step 200 to just enter the control channel map to enter the standby state again, and in the case of YES, step 204 notifies the upper CPU of the connection request.

Next, in step 205, the MPU 5 notifies the upper CPU that there is a connection request, and then determines whether or not there is data that can be connected from the upper CPU, and if YES, step 206 is executed. In step 206, the MPU 5 gives a control data signal command to the channel designation register 13 which has created connectable data according to the frame, opens the gate 45 and outputs the connectable data on the control channel on the transmission / reception line 1.

Although not shown, when outputting data to the transmission / reception line 1, the MPU 5 checks the presence / absence of a signal collision on the transmission / reception line 1 via the carrier detection circuit 49, and if the collision occurs, the data is output. It stops sending and receiving of, waits for a certain period of time, and restarts.

Further, in step 207, since the MPU 5 inputs / outputs the data of the channel designated by the partner device, the transmission / reception channel is given to the channel designation register 13 to check the timing of the channel to be used from the time control 27 and the gate 37, 47 of An open signal is output and data is input / output. In the following step 208, the MPU 5 notifies the upper CPU that the connection is completed and data can be transmitted / received, and the connection processing is ended.

On the other hand, if step 205 is NO, the process moves to step 209 to create unconnectable data according to the frame, and gives a control data transmission command to the channel designation register 13,
The gate 45 is opened, the data is output to the control channel on the transmission / reception line 1, and the map internally created in step 210 is modified and the process ends.

Next, the procedure for outputting a connection request from the own device to the partner device will be described with reference to FIG.

In step 300, the presence / absence of a connection request from the host CPU is discriminated. If NO, the process returns to the original step. If YES, step 3
At 01, the MPU 5 receives the connection information such as the address of the partner to be connected from the upper CPU and stores it in the RAM 9.

Next, in step 302, the MPU 5 refers to the map created in the RAM 9 in its own device and searches for the presence or absence of an empty channel.
If NO, move to step 312 and determine that connection is not possible
Notify the PU.

There are two or more empty channels and step 302 is YES.
In this case, in step 303, connection data is created with the configuration shown in FIG. The information field contains channel data created by the device and channel data created by the other party.

In the following step 304, it is confirmed whether or not the control channel is vacant. If YES, the MPU 5 reads the carrier detection circuit 49 in order to output the connection data in step 305, and sends the control data command to the channel designation register 13. To output data on the transmission / reception line 1.

If step 304 is NO, it is determined in step 310 whether or not the control channel is not vacant within a certain time. If YES, the process returns to step 304, and if YES, the process moves to step 312 and the higher order. Notify the CPU.

In step 306, the MPU 5 creates a channel map of its own device, and in the following step 307 it is determined whether or not the connection with the partner device is completed, and if YES, the channel data to be used in the channel designation register 13 is specified in step 308. Designate and notify the upper CPU that the connection is completed in step 309.

When step 307 is NO, the process moves to step 311 to receive the connection impossible data and correct the channel map, and at step 312 the upper CPU is notified that the connection is impossible, and the process ends.

 Next, the connection release procedure will be described with reference to FIG.

The disconnection can be performed from either side between the two devices, receiving the data of the device that previously output the data on the control channel.

In step 400, it is determined whether the transmission between the devices has ended, and NO
If yes, return to step 400; if yes, step
Move to 401. In step 400, the MPU 5 receives a disconnection signal from the upper CPU to create disconnection data, and in step 402, it is checked whether or not the control channel is free for output to the control channel.

If step 402 is NO, the process moves to step 403 and wait processing is executed, and if it is YES, a control output command is output to the time control 27 to output release data at step 404 and control is performed. The data is output from the signal transmission buffer 15.

In the following step 405, it is determined whether or not a disconnection confirmation signal is transmitted from the partner device, and in the case of NO, the process proceeds to step 407 and whether or not the disconnection confirmation signal is transmitted within a fixed time. If the determination is NO, the process returns to step 405, and if the determination is YES, it is recognized that an abnormality has occurred, and error processing is performed in step 408. If YES in step 405, in step 406, the MPU 5 corrects the map stored in the RAM 9 in the own device and ends the processing.

It goes without saying that the present invention can be applied to general data transmission and voice transmission.

As described above, according to the data transmission system and the data transmission method for a plurality of devices of the present invention, each device has a connection status map by monitoring the connection status of the transmission / reception combined transmission line, , The empty channel data is output and the connected channel is formed. Therefore, it is possible to transmit data with more devices than the number of channels (the number of time slots for data transmission / reception) of each device, and the number of connected devices. Can be easily increased.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a data transmission system and a data transmission method between a plurality of devices according to the present invention, and FIG. 2 is a time chart showing a timing relationship of the entire system according to the present invention. FIG. 3 is a diagram showing a signal transmission / reception timing between two devices and a bit configuration of each signal, FIG. 4 is a diagram showing a specific bit pattern of a synchronization signal, and FIG. 5 is a format for forming a transmission / reception message. 6 and 6 are diagrams for explaining a signal transmission system, FIG. 7 is a block diagram showing an embodiment of a data transmission system between a plurality of devices according to the present invention, and FIG. 8 is a RAM in FIG. 9 to 12 are flow charts showing the operation of the data transmission system of the present invention shown in FIG. 7. 1 …… Transmit / receive line 5 …… MPU 7 …… ROM 9 …… RAM 13 …… Channel designation register 15 …… Control signal transmission buffer 17 …… Control signal reception buffer 19 …… Data signal transmission buffer 21 …… Data signal Receive buffer 23 …… Synchronous signal detection circuit 25 …… Time slot generation circuit 27 …… Time control 29,35,37,41,45,47, …… Gate, 31 …… Demodulation circuit 33 …… Media interface 39 ...... Synchronization signal generation circuit 43 …… Modulation circuit 49 …… Carrier detection circuit

Claims (6)

[Claims] 1. A mutual data transmission system between a plurality of devices comprising a plurality of devices connected to each other by a transmission / reception transmission line, wherein each device is formed by being divided into a plurality of parts within a certain period. And a plurality of time slots including a time length for signal transmission / reception and a maximum signal transmission delay time between devices, one of these time slots for synchronization signal and the other one for control signal transmission / reception And a remaining time slot, time slot creating means for creating a time slot for data transmission / reception corresponding to each device, and a first gate opened in synchronization with the sync signal time slot. A second gate opened in synchronization with the control transmission / reception time slot, and a third gate opened in synchronization with the data transmission / reception time slot. A transmission / reception means for transmitting / receiving a signal or data when the gate is opened; a storage means for storing a usage state map of a data reception time slot; and a search for searching an empty time slot in the map. A mutual data transmission system between a plurality of devices, comprising: 2. A data transmission system for mutual communication between a plurality of devices according to claim 1, further comprising map creating means for creating a usage status map of data reception time slots. . 3. A data output means for outputting data to the transmission / reception combined transmission line on condition that an empty time slot is detected, the data output means being further provided. A data transmission system for mutual communication between a plurality of devices according to item 2. 4. A method for mutual data transmission between a plurality of devices, comprising a plurality of devices connected to each other by a transmission / reception transmission line, wherein each device is formed by being divided into a plurality of parts within a certain period. And a plurality of time slots including a time length for signal transmission / reception and a maximum signal transmission delay time between devices, one of these time slots for synchronization signal and the other one for control signal transmission / reception And a time slot in which each of the remaining time slots is for data transmission / reception corresponding to each device, a first gate opened in synchronization with the synchronization signal time slot, and the control A second gate opened in synchronization with the transmission / reception time slot, a third gate opened in synchronization with the data transmission / reception time slot, and the gate opened And a step of transmitting and receiving signals or data, a step of storing a usage state map of a data reception time slot, and a step of searching for an empty time slot in the map. A method of mutually transmitting data between a plurality of devices. 5. The method for transmitting data between a plurality of devices according to claim 4, further comprising the step of creating a usage status map of the time slot for data reception. 6. The method according to claim 4, further comprising the step of outputting data to said transmission / reception transmission line on condition that an empty time slot is detected. A method of mutually transmitting data between a plurality of devices according to the item.