JPH081594B2 - Firmware change system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware changing system in a data processing device. The functions of one or more devices in a data processing system are often implemented by firmware. That is, these devices have a microprocessor and a ROM, and the software that determines the fixed functions of these devices is written in the ROM in advance.

[0002]

2. Description of the Related Art Since firmware is a kind of software, it may be required to change the firmware in order to upgrade the firmware or fix bugs. In a large-scale, general-purpose data processing device, etc., a service processor provided with a magnetic disk device for storing magnetic firmware is provided, and when the system is powered on or restarted, the above-mentioned firmware is processed by the service processor. The data is read from the magnetic disk and stored in the RAM in the plurality of devices in the data processing system. That is, the service processor controls the firmware change or modification.

However, in a relatively small data processing system or a relatively small device such as an interface adapter of a peripheral device, the firmware is written in the ROM in advance, and when changing or modifying the firmware, It was necessary to replace the ROM itself.

[0004]

By the way, in order to replace the ROM, the system must be stopped, and especially when the firmware of a large number of devices has to be changed, and the devices have a wide range. If they are distributed, the amount of work for ROM replacement becomes enormous.

Further, since the device does not always operate normally after the change of the firmware (program data) due to a bug in the change data of the firmware, the conventional ROM alone is used. In such a case, there is a problem that the ROM needs to be replaced again. Therefore, the present invention can be applied to a case where a data processing device requiring a firmware change is distant, or a plurality of data processing devices requiring a firmware change are distributed over a wide range. Provides a firmware change system that allows easy and high-speed firmware change, and facilitates reversion to an old version of firmware even when changed data does not operate normally. The purpose is to

[0006]

FIG. 1 shows the basic configuration of the present invention. In FIG. 1, 1 is a data processing device, 2 is change data supply means, 3 is a processor, 4 is execution program holding means, 5 is fixed program data storage means, 6 is change data storage means, and 7 is fixed program data load. Means, 8 is execution program changing means, 9 is changed data transferring means, 10 is transfer command receiving means, 1
Reference numeral 1 is a change data holding means, 12 is a transfer command issuing means, and 13 is a change data transfer path.

Of these, the most basic configuration of the present invention is a firmware changing system for changing the firmware of the data processing device 1, which includes a processor 3,
It comprises an execution program holding means 4, a fixed program data storage means 5, a changed data storage means 6, a fixed program data loading means 7, and an execution program changing means 8.

Here, the processor 3 executes the program. The execution program holding means 4 holds the data of the program executed by the processor 3. The fixed program data storage means 5 stores fixed program data. The change data storage unit 6 stores change data for changing the fixed data, and the change data can be written from outside the data data processing device 1.

The fixed program data loading means 7 reads the fixed program data from the fixed program data storage means 5 and loads the fixed program data into the execution program holding means 4. The execution program changing means 8 changes the program data held in the execution program holding means 4 with the change data held in the change data storage means 6.

In addition to the above most basic structure,
It can have the following additional configurations. The fixed program data includes a plurality of partial programs respectively corresponding to the fixed program data loading unit 7 and the execution program changing unit 8, and the fixed program data loading unit 7 and the execution program data loading unit 8 are , Respectively, can be realized by the execution of the plurality of program parts by the processor 3.

It is possible to have a change data supply means 2 which is provided outside the data processing device 1 and supplies change data to be stored in the change data storage means 6. The change data supply means 2 has a change data holding means 11 for holding change data to be stored in the change data storage means 6 and a transfer command issuing means 12 for issuing a transfer command to the data processing device 1. However, the firmware changing system has a change data transfer path 13 from the change data holding means 11 to the change data storage means 5, and the data processing device 1 transfers data for receiving the transfer command. The firmware changing system further includes a command receiving unit 10, and when the transfer command receiving unit 10 receives the transfer command, the firmware changing system stores the change data in the change data holding unit 1.
Change data that is read from the first data transfer unit 1, transferred from the change data holding unit 11 to the change data storage unit 6 via the change data transfer path 13, and writes the change data to the change data storage unit 6. A transfer means 9 may be included.

The change data includes a plurality of versions of change data, and the firmware changing system specifies the program data held in the execution program holding means 4 with respect to the execution program changing means 8. Has a change version command means for instructing to change according to the change data up to the version,
When the execution program changing means 8 receives the instruction about the version, the execution program changing means 8 changes the program data held in the execution program holding means 4 in order from the old version to the new version by the change data up to the specific version. You can

The change data of the plurality of versions is
The change data storage means 6 is divided into a plurality of blocks corresponding to the plurality of versions and arranged in order from the old version to the new version, and the change version command means stores the change data up to the specific version. The version can be ordered according to the number of blocks including.

Each block corresponding to each version includes an address of each data to be changed, new data of the address of the version, and data of the address of the version that is one version level older than the version. And the execution program changing means 8 including
Changes the data in the execution program holding means 4 in order from the old version to the new version, and the execution program changing means 8 changes the old version of each address before changing the data in the execution program holding means 4. Data and the execution program holding means 4
In the case where it is determined by the comparing means that compares the data of the same address in the above-mentioned step and the data of the old version of each address and the data of the same address in the execution program holding means 4 are not equal, It is possible to have an abnormal stop means for stopping the changing process.

Each block corresponding to the change data includes information indicating the corresponding version, and the execution program holding means 4 has an area showing the version of the change received by the program data held by itself, The execution program changing means 8 includes the contents of the area indicating the version of the received change based on the information indicating the corresponding version every time the program data of the execution program holding means 4 is changed by the change data of each block. Can be updated.

Before the program data of the execution program holding means 4 is changed by each block corresponding to each version, the execution program changing means 8 stores the contents of the area indicating the version of the received change in the block. It is possible to have a version confirmation means for confirming whether or not the version change data indicates the version to be changed.

[0017]

According to the most basic structure of the present invention, fixed program data, that is, program data of version 0, is always stored in the program data storage means 5. The change data for changing the fixed data is stored in the change data storage means 6. Here, the change data storage unit 6 is configured so that the contents can be written from the outside.

Therefore, when loading the firmware, first, the fixed program data loading means 7 loads the change data stored in the fixed program data storage means 5 into the execution program holding means 4,
The program data loaded in the execution program holding means 4 is changed by the execution program changing means 8 by the change data stored in the change data storage means 6. Then, this change data can be rewritten from the outside.

Therefore, in any case, at a minimum,
Since the fixed program data of version 0 is stored in the fixed program data storage means 5, if there is an abnormality in the operation of the apparatus after the change, the fixed program data loading means 7 causes the fixed program data loading means 7 to execute the executed program holding means again. The contents of 4 can be returned to the firmware without any change.

Further, since the change data in the change data storage means 6 can be rewritten from the outside, the contents of the change data storage means 6 can be appropriately changed from the outside when the operation of the apparatus after the change is abnormal. After rewriting to the version change data, the contents of the execution program holding means 4 are temporarily changed by the fixed program data loading means 7 described above.
After rewriting the fixed program data, the contents of the execution program holding unit 4 are rewritten by the contents of the changed data storage unit 6 by the execution program changing unit 8 to make the contents of the execution program holding unit 4 any version. be able to.

Further, the above [means for solving the problem]
According to the additional configuration of (1), the change data includes old data as well as new data of the address to be changed, and the execution program changing means 7 is added.
However, before rewriting the contents of each address of the execution program holding means 4, the contents written in each address of the execution program holding means 4 by the comparison means are compared with the old data included in the above-mentioned change data. By doing this, you can accidentally change the data at a different address,
When the data before the change is erroneously recognized or there is an error in the data before the change, the presence of the abnormality can be detected.

The functions of the above and / or the additional configurations will be understood from the above description of [Means for Solving the Problems].

[0023]

Embodiments [of a data processing system to which the present invention is applied
Example (FIG. 2) ] FIG. 2 shows a configuration of a distributed data processing system as an example of a data processing system to which the present invention is applied. The configuration of FIG. 2 illustrates a distributed data processing system having multiple branch offices spread over a wide area, which may be used, for example, in banks, credit companies, insurance companies, chains of supermarkets, and the like. Communication control processing device CC in the configuration of FIG.
For the change of firmware in P21 or 29,
The present invention is applied.

In FIG. 2, 17 and 27 are host computers, 18 and 28 are databases, 19 and 29 are communication control processing devices, 20 and 30 are auxiliary storage devices, 21, 22, and 23 are network processors, and 24 is maintenance. Center, 25 is terminal device, 26
Is the switch system and 27, 28, and 29
Is a transmission path.

The network processors 21 to 23 and the transmission lines 27 to 29 form a backbone network, and the network processors 21 to 23 are provided in each node of the network. However, although there are many nodes other than those shown in the actual backbone network, they are omitted in FIG. These nodes are provided at the locations of the above-mentioned branches and the like.

Host computer 17, database 1
8, communication control processing device 19, and auxiliary storage device 20
Configures one information center to manage, for example, information about customers in a certain area. Similarly, the host computer 27, the database 28, the communication control processing device 2
9 and the auxiliary storage device 30 constitute another information center and manage, for example, information about customers in other regions. The communication control processing device 19 or 29 is provided between the backbone network and the host computer of the upper level, and controls communication via the backbone network of the host computer of the upper level. As is well known, the functions of the communication control processing device are, for example, data format conversion, data link establishment and release, transmission line monitoring, error detection, data buffering, host computer and the communication control processing device. It includes data transfer between and.

In the configuration of FIG. 2, the maintenance center 24 is connected to one of the above network processors and the switch 26 is also connected to one of the same network processors, but these are on separate processors. May be connected. The terminal device 25 is provided in each branch, for example, and is connected to the transmission line of the backbone network via the exchange 26. With such a configuration, for example, an operator in front of one terminal device
The information center can be accessed and information can be obtained through the terminal device, the exchange 26, and the backbone network.

[ Configuration Example of Communication Control Processing Device (FIG. 3) ] FIG. 3 shows a configuration example of the communication control processing device in the embodiment of the present invention. In FIG. 3, 31 ₁ and 31
₂ is a common memory, 33 ₁ , 33 ₂ , 38 ₁ , and 3
8 ₂ is a bus handler, and 34 ₁ and 34 ₂ are, for example,
I / O devices such as auxiliary storage devices, 35 is a line switching circuit, 36 ₁ , 36 ₂ , 36 ₃ and 36 ₄ are adapters, 37 is a transmission line, 40 ₁ , 40 ₂ , and 40 ₃
Are processors, 41 ₁ and 41 ₂ are system buses, and 42 ₁ and 42 ₂ are I / O buses.

The communication control processing device of FIG.
The communication control processing device has a coupled multiprocessor configuration and the above-described function of the communication control processing device is provided by a plurality of processors 40 ₁ ,
₂ and 40 ₃ . Common memory 3
1 ₁ and 31 ₂ are the plurality of processors 40 ₁ ,
Shared by 40 ₂ and 40 ₃ . Common memories 31 ₁ and 31 ₂ , system buses 41 ₁ and 41
₂ , I / O buses 42 ₁ and 42 ₂ , bus handler 33
₁ and 33 ₂ , bus handlers 38 ₁ and 38 ₂ , adapters 36 ₁ and 36 ₂ , adapters 36 ₃ and 36
_The reason why the ₄ etc. are in a pair configuration is to make the device into a redundant redundant configuration, and only one of these pairs is activated under the control of any of the above processors. It is used after being converted. For example, the line switching circuit 35
The adapter 36 under control of any of the processors.
Connecting line 37 towards the activated among ₃ and 36 _4. The line 37 is connected to the network processor 21 of FIG. 2, for example. In this case, the adapters 36 ₃ and 36 ₄ function as line interface devices between the processors 40 ₁ , 40 ₂ , and 40 ₃ and the line 37, respectively. Adapters 36 ₁ and 36 ₂
Processors 40 ₁ , 40 ₂ , and 40 _{3, respectively}
And an I / O device 34 ₁ and 34 ₂ as an interface circuit. In this embodiment, the adapters 36 ₁ , 36 ₂ , 36 ₃ , and 36 ₄ correspond to the data processing device 1 of FIG. 1, and the processors 40 ₁ , 4
0 ₂ and 40 ₃ are the change data supply means 2 of FIG.
To realize.

[Configuration example of adapter (Fig. 4)] Figure 4
Showing a configuration example of an adapter in the communication control processor of No. 3
Is. In FIG. 4, 42_i(I = 1 or 2) is
I / O bus 42 above₁And 42 ₂ Indicates any of the above.
In addition, 36_j(J = 1 to 4) is the above adapter 3
6₁, 36₂ , 36₃, And 36_FourIndicates either
You. Further, in FIG. 4, 50 is a bus controller, 5
1 is MPU, 52 is RAM, 53 is ROM, 54 is EE
The PROM 55 is a device controller or a line
Interface and 56 is a local bus
It

The MPU 51 controls the overall operation of the adapter 36 _j and corresponds to the processor 3 in the configuration of FIG. The RAM 52 is used as a main storage area (work area) of the MPU 51, and a program executed by the MPU 51 is expanded in the RAM 52. RAM52 is
It corresponds to the execution program holding means 4 in FIG. ROM5
3 stores fixed program data as version 0 data, and the fixed program data storage means 5 of FIG.
Corresponding to. Processors 40 ₁ , 40 ₂ , and 40
Any one of the _three can write change data to the EEPROM 54 with the assistance of the MPU 51, as described later. This change data is used to change the program data loaded in the RAM 52.

The program data of version 0 includes a partial program for initial program loading. This partial program reads version 0 program data from the ROM 53 and stores it in the RAM 5
RAM52 and the first routine to transfer and load
The program data loaded in the
And a second routine for making changes according to the change data stored in.

When the adapter 36 _j is powered on,
Alternatively, when the adapter receives a command for initial program loading, as described below, the MP
The control of U51 shifts to the start address of the first routine of the ROM 53, and the first routine is executed.
Further, when the change data is stored in the EEPROM 54 and the change processing of the program data is instructed by any of the processors 40 ₁ , 40 ₂ , and 40 ₃ , in the adapter 36 _j , the second MPU 51 described above is used. Is executed.

The device controller or line interface 55 has a local bus 56 and an I / O, respectively.
It functions as an interface between the O-device 34 ₁ or 34 ₂ or an interface between the local bus 56 and the line 37. Bus controller 50
Functions as an interface circuit between the I / O bus 42 _i and the adapter 36 _j . Bus controller 50
The functions of: are processors 40 ₁ , 40 ₂ , and 40 _3.
Command from any of the following; M of the received command
Transfer to the PU 51; any of the processors 40 ₁ , 40 ₂ , and 40 ₃ and the I / O device 34 ₁ or 34
₂ or buffering of data transferred to / from the line 37; buffering of modified data transferred between any of the processors 40 ₁ , 40 ₂ and 40 ₃ and the EEPROM 54; processors 40 ₁ and 40 ₂ , And 40 ₃ obtains an access right to a memory (not shown) included in any of them; change data from the memory included in any of the processors 40 ₁ , 40 ₂ , and 40 ₃ to the bus controller 50 Transfer of the modified data from the bus controller 50 to the EEPROM 54. The transfer of the modified data is performed by DMA transfer. That is, the bus controller 50 has a function as a DMA controller. Processor 40 _1, 40 ₂ described above, and, the access to the memory comprising any of the 40 _3, change of the processor 40 _1, 40 _2, and, from the memory comprising any of 40 ₃ to the bus controller 50 This is performed when data is transferred.

[0035]Transfer processing of change data to adapter (Figure
5)In the distributed data processing device of FIG. 2, R of FIG.
Program for changing program data in AM52
Ram data from the maintenance center 24
Via the network of the communication control processor CCP.
Rossa 40₁, 40 ₂ , And 40₃To one of
Sent. The transferred change data is temporarily stored in this process.
It is stored in the RAM in the storage system. Receive change data
Then, the above processor sends this changed data to the adapter 3
6_iProcessing as shown in FIG. 5 for forwarding to
To execute. FIG. 5 shows the adapter 36_iChange data to
Processor 40 for sending₁, 40₂ , And 4
0₃It is a flowchart which shows the process by either.
Processor 40₁, 40₂ , And 40₃Change the
Data transfer to the adapter, or
Is the data processing load on the processor after this request.
When the load is reduced, the process of FIG. 5 can be performed.

In step 101 of FIG. 5, the processor issues an adapter state transition instruction to the adapter. Then, in step 102, it is determined whether or not the adapter state transition instruction is normally completed. When it is determined in step 102 that the execution of the instruction did not end normally, the process proceeds to step 109 and abnormal end processing is performed. When it is determined in step 102 that the instruction has been normally executed, step 10
Process 3 is performed. When it is determined that the process of step 102 is normally completed, the process proceeds to step 109.
When it is determined that the process of step 102 is normally completed, the process proceeds to step 103. The adapter state transition instruction is first received by the bus controller 50 in the adapter, and then the bus controller 50 sends an interrupt signal corresponding to the adapter state transition instruction to the MPU 51.
Send to. In response to this interrupt signal, the MPU 51
Performs a process of transitioning to a state in which the adapter can receive change data, and when this process ends, returns a ready signal to the processor of the communication control processing device. This ready signal indicates that the adapter has transitioned to a state in which it can receive change data. In step 103,
When the processor receives this ready signal, the process proceeds to step 104 and issues a transfer instruction to the adapter. Details of this transfer processing will be described later.

In step 105, it is determined whether the transfer of the changed data has been completed normally. If the transfer is not completed normally, the process proceeds to step 109 and abnormal end processing is performed. When the transfer is normally completed, the process proceeds to step 106 and an adapter processing restart command is issued to the adapter. This adapter processing restart signal is first received by the bus controller 50 in the adapter, and the bus controller 50 MPs an interrupt signal corresponding to this adapter processing restart signal.
Send to U51. In response to this interrupt signal, MPU5
1 shifts the adapter to the normal processing state and returns a completion signal to the processor of the communication control processing device. This completion signal indicates that the adapter has transitioned to the normal processing state. In step 107, it is determined whether the adapter processing restart instruction has been executed normally. When the above completion signal is not received, the processor proceeds to the processing of step 109 and performs abnormal termination processing. When the completion signal is received, the processor ends the process of FIG.

[Of change data stored in EEPROM
Format (FIG. 6) ] FIG. 6 shows E in the configuration of FIG.
It is a figure which shows the example of a format of the change data stored in EPROM. As shown on the left side of FIG. 6, the EEPROM 54 having the configuration of FIG. 4 includes management data, a plurality of changed data blocks 1 to N, and an empty area. The change data of the plurality of blocks corresponds to a plurality of versions of the change data (that is, a plurality of changes). That is, the change data block 1 corresponds to the first change (revision 1), the change data block 2 corresponds to the second change (revision 2), ... It corresponds to N changes (revised N).

As shown in the upper right part of FIG. 6, the area of the management data is a fixed value "FPDT (ASCCI code)", and whether or not the EEPROM 54 is open (not protected) for the writing process (closed). ) Or not (“00” indicates that the EEPROM 54 is protected, and “01” indicates the EEPROM 5).
4 is not protected), the identification number PM-ID of the processor instructing the adapter, the number N'of modified data blocks to be used for modification, EEPRO
It includes the size of the empty area of M54, the size of the written area of the EEPROM 54, and the checksum of the data in all management data and changed data blocks in the EEPROM 54.

As shown in the lower right part of FIG. 6, each modified data block includes a header area, a modified data area, and an end mark.

[For the header area of the modified data block,
Format (FIG. 7) ] FIG. 7 shows an example of the format of the header area of the modified data block of FIG.
As shown in FIG. 7, the header area has a fixed value "D".
BLK (ASCCI code) ", including the current version of the program data held in the RAM 52 of the adapter that should be modified by the modification data, the size of the modification data block, and the checksum of the data in the modification data block .

[ Unit in Change Data Block (see FIG. 8)
And FIG. 9) ] In each of the above-mentioned change data blocks, the change data is included in a plurality of units. 8 and 9 show two types of each unit of change data stored in the EEPROM 54 of FIG. In the type of unit of FIG. 8, each unit contains the address in RAM 52, the new (after change) data and the old (before change) data at that address. On the other hand, a unit of the type of FIG. 9 contains the address of the modified data and two new (modified) data (new data 0 and new data 1) corresponding to the address. Each unit also includes information about the above type (indicating which type it is).

[ End Mark (FIG. 10) ] FIG. 10 shows an example of the end mark. In this example, the end mark is "FFFFFFFF".

[0044]I / O command format
(Figure 11)FIG. 11 shows the I / O in the embodiment of the present invention.
It is a figure which shows the general format of an instruction (command).
It The I / O command is a process of the communication control processing device shown in FIG.
Service 40₁, 40₂ , And 40₃To adapter 3
6₁, 36₂ , 36₃, And 36_FourIssued to
Be done. The format of FIG. 11 is the processor 40₁, 4
0 ₂ , And 40₃To I / O bus 42₁And 42
₂ Via any of the adapters 36₁, 36₂ , 36₃,
And 36_FourFor all I / O commands issued to
Used in The format of Fig. 11 is I / O
Number ADP-N indicating the adapter for which the decree is issued
O. , A code OPECODE indicating the type of instruction, and
And AOPD address. I / O instruction is in the adapter
When the instruction is to be performed by the MPU 51 of
Is a code that indicates the type of instruction.
DOP. AOPD is an adapter operation described later.
Is an abbreviation for the Aation Descriptor.
The dress is the same as the one included in the processor (not shown).
Adapter operation discretion in memory
The start address of the area where the
It

[ Format of AOPD (FIG. 12) ] FIG. 12 shows the adapter operation descriptor A.
1 illustrates an example of an OPD format. 12
AOPD is a command code CMDCODE indicating the type of processing requested by the I / O instruction, and a data count DATA COUNT indicating the number of bytes of the changed data.
T, start address of change data storage area described later, I /
It includes a function code FNC CODE indicating the detailed mode of processing requested by the O instruction, and the number N'of blocks of change data to be used for changing program data.

When the above AOPD is used for a transfer instruction of change data from the processor to the adapter, the above "command code CMDCODE" is set to a code indicating the "change data transfer instruction", and the above "change data storage" is set. The area "start address of area" indicates the start address of the area in the memory of the processor in which the change data as shown in FIG. 13 described later is held. Then, in the above-mentioned "Number of blocks of change data to be used N '", up to which block of the change data of a plurality of blocks already stored in the EEPROM 54 is changed to the program data on the RAM 52. You can specify the watermark. That is, by this designation, as will be described later, it is possible to designate that the program data on the RAM 52 is subject to a change up to an arbitrary block among the change data of a plurality of blocks stored in the EEPROM 54. Thus, when the processor detects that an adapter is not working properly with some version of firmware, the processor can, for example, instruct it to revert to an older version.

As will be described below, when the processor gives an initial program loading instruction to the adapter using the formats of FIGS. 11 and 12 already after the modified data has been transferred to the EEPROM 54 in the adapter. , Above "command code CMD
“CODE” is set to a code indicating “initial program loading instruction”, and the area of “start address of change data storage area” may be all “0”.
Also at this time, in the above-mentioned "number of blocks of changed data to be used N '" column, EEPRO has already been set.
It is possible to specify up to which block among the change data of a plurality of blocks stored in M54, the program data on the RAM 52 is changed.

[Example of function code (Fig. 1
3)13] FIG. 13 shows a modified version of the EEPROM 54 of the adapter.
Function code related to the process of writing data
It shows a typical example. It's shown in Figure 13.
Sea urchin processor 40₁, 40₂ , And 40₃What
Somehow, (the previously written data was cleared
After) write new change data to EEPROM 54.
When requesting and, the function code FNC
 CODE is “00”. Processor 40₁, 40
₂ , And 40₃Is stored in the EEPROM 54.
Write change data in addition to the change data written to
Function code when requesting
FNC CODE is “01” or “02”. Step
Require processor to close EEPROM 54
Function code FNC COD
E is “03”. The processor uses the EEPROM 54
Clear and close, and initialize the management data.
When requesting, use function code FNC C
ODE is “04”. And the processor manages
Change data block specified in the data area
Block format, old and new data version
Number consistency and checksum normality
When requesting the check of
The de FNC CODE is “05”.

[For the data in the changed data storage area of the RAM 52 ]
Format (FIG. 14) ] FIG. 14 shows an example of a format of a change data storage area stored in the memories of the processors 40 ₁ , 40 ₂ , and 40 ₃ of the communication control processing device. As described above, the start address of this area is designated by AOPD in FIG. Further, as shown in FIG. 14, the format of the change data storage area is the same as the format of the change data in the EEPROM 54 shown in FIG.

[ Process for Transferring Change Data by Processor ( FIGS. 15, 16 and 17) ] FIGS. 15 and 1
6 and FIG. 17 are flowcharts showing the processing for causing the processor to transfer the changed data to the adapter.

In step 301, the processor
Store AOPD in its own memory. here,
Function code FNC CODE in AOPD
Are set to "00" and "01". then,
In step 302, the processor stores the modified data in memory. In step 303, the processor issues an IAD instruction. Here, the IAD instruction is an instruction in which the OPECODE is set to "IAD". In FIGS. 15 to 17, what is indicated by “A” and “B” is the relationship with the processing in FIGS. 18 to 21 performed by the processor corresponding to the processing in these figures.

In step 304 of FIG. 15, it is determined whether the end interrupt signal is received. As described below with reference to FIG. 21, when the execution of the IAD instruction is completed, the adapter returns an end interrupt signal to the processor. If it is determined in step 304 that the end interrupt signal has been received, the process proceeds to step 305 in FIG. In step 305, the processor
Determine if there is more modified data to transfer to the adapter. When it is determined in step 305 that the changed data to be transferred to the adapter is further included, the process proceeds to step 306. If it is determined in step 305 that there is no further change data to be transferred to the adapter, the process proceeds to step 311 in FIG.

In step 306, the processor stores the function code FNC in its memory.
The AOPD whose CODE is set to "02" is stored. Then, in step 307, the additional change data is stored in the memory. Next, in step 308, the processor issues an IAD instruction to cause the adapter to transfer additional modified data.

In step 309, it is determined whether the end interrupt signal is received. When it is determined in step 309 that the end interrupt signal has been received, the process proceeds to step 310, and it is determined whether the processor further has change data to be transferred to the adapter. When it is determined in step 310 that there is more change data to be transferred to the adapter, the process proceeds to step 306. If it is determined in step 305 that there is no further change data to be transferred to the adapter, the process proceeds to step 311 in FIG.

In step 311 of FIG. 17, the processor stores in its memory the AOPD with the function code FNC CODE set to "03". Then, the IAD command for closing the EEPROM 54 is issued to the adapter. Then, when the end interrupt signal is received in step 313, FIG.
~ The process of Fig. 17 is ended.

[ Changed data transfer processing by adapter (Fig.
18 to 21) ] FIGS. 18 to 21 are flowcharts showing a process for the adapter to transfer the changed data to its own device. The process of FIG. 18 to FIG. 21 is step 4
00, processors 40 ₁ , 40 ₂ , and 4
0 ₃ issued IAD command to the adapter to any of the adapter is started by receiving. In step 401, the MPU 51 reads the AOPD from the memory of the processor that issued the IAD command via the bus controller 50. here,
The address of AOPD is written in the IAD instruction as shown in FIG. Read AOP
D is transferred to the adapter by the DMA function of the bus controller 50. In step 402, the function code FNC CODE in the above AOPD.
Is determined, the function code FN
If C CODE is “00”, step 4 in FIG.
03, if the function code FNC CODE is "01" or "02", step 4 of FIG.
If the function code FNC CODE is “03” in 06, the process proceeds to step 410 in FIG.

In step 403 of FIG. 19, MP
U51 reads the contents of the changed data storage area (FIG. 14) in the memory of the processor. Here, the start address of the changed data storage area is indicated in AOPD (FIG. 1).
2). Then, the read contents are transferred by the DMA function of the bus controller 50 from the memory of the processor to the bus controller 50, and from the bus controller 50 to the EEPROM 54 of the adapter. That is, in this embodiment, the modified data transfer path 13 of FIG. 1 is either the I / O bus 42 ₁ or 42 ₂ .
It is realized by the bus controller 50 and the local bus 56, and the data transfer means 9 of FIG. 1 is realized by the bus controller 50 and the MPU 51.

The above-mentioned transferred change data is EEPR.
In the OM 54, it is written in an area subsequent to the area of the management data transferred and stored previously (step 40).
4). Then, the process proceeds to step 405, and EEPRO
Update the management data in M54. In this update process, the "number of blocks of change data N'to be used for change" in the AOPD (FIG. 12) is the EEPROM 54.
Is written in the management data area (FIG. 6) in the file, the status is set to the “open” state, the identification number of the processor that issued the IAD instruction is stored as PM-ID, and the newly transferred change data is stored. Correspondingly EEPRO
The sizes of the empty area and the written area of M54 are updated. Then, the process proceeds to step 411 to send an end interrupt signal to the processor.

In step 406, the MPU 51
Reads the contents of the changed data storage area. even here,
The start address of the changed data storage area is shown in AOPD (FIG. 12). Then, the read contents are read from the memory of the processor to the bus controller 50 by the DMA function of the bus controller 50, and from the bus controller 50 to the EEPROM of the adapter.
54. The transferred change data is EEP
In the ROM 54, the data is written in an area subsequent to the area of the change data previously transferred and stored (step 40).
7). Then, the process proceeds to step 408, and it is determined whether the function code FNC CODE of AOPD is “01” or “02”. Function code FNC
When CODE is “01”, the process shifts to step 405. Function code FNC C
When the ODE is “02”, the process proceeds to step 409. In step 409, the MPU 51 determines that E
The management data stored in the EPROM 54 is updated.
In this update process, "the number N'of blocks of change data to be used for change" in the AOPD (FIG. 12).
Is written in the management data area (FIG. 6) in the EEPROM 54, and the status remains the “open” state, but the EEP corresponds to the newly transferred change data.
The sizes of the empty area and the written area of the ROM 54 are updated. When the function code FNC CODE is "02", it indicates that the change data is transferred from the same processor as the original processor to which the change data was transferred first. Therefore, the identification number of the processor that issued the IAD instruction is PM-. The ID remains unchanged. Then, the process proceeds to step 411 in FIG. 21 to send an end interrupt signal to the processor.

In step 410 of FIG. 20, MP
The U51 updates and stores the management data in the EEPROM 54. Here, the “number of blocks of change data N ′ to be used for change” in the AOPD (FIG. 12) is EE.
The data is written in the management data area (FIG. 6) in the PROM 54, the status is “closed”, the number of changed data blocks, the size of the empty area of the EEPROM 54, the size of the written area, and the changed data are stored. The checksum of the data in the reserved area is stored (calculated). Then, move to step 411 of FIG. 21,
Send an end interrupt signal to the processor.

[ Outline of IPL processing in adapter (Fig.
22) ] When any one of the processors 40 ₁ , 40 ₂ , and 40 ₃ issues an initial program loading (IPL) instruction to the adapter, the adapter executes the processing of FIG. Figure 22 shows the initial program loading (IPL) in the adapter.
It is a flowchart of a process. In the processing of FIG. 22, the adapter is transferred from the processor (via the bus controller 50).
It is started by receiving an initial program loading (IPL) command. As described above, when the initial program loading (IPL) instruction includes the "number of blocks of change data N'to be used for change N '" by the AOPD, although not shown, the adapter first sets this value. Write in the management data area. Then, the processing shifts to the processing in FIG.

In step 201 of FIG. 22, RO
In order to read the fixed program data (version 0 program data) of M53, the control of MPU51 is as follows.
The process moves to the head address of the fixed program data area of the ROM 53. Then, this fixed program data is stored in the RAM 52. And step 202
In MPU 51, the MPU 51 stores "the number N'of changed data blocks" in the management data stored in the EEPROM 54.
Is read out, and it is determined in step 203 whether N'is 0 or not. That is, it is determined whether or not the number of changed data blocks designated to be used for changing the program data on the RAM 52 is zero. If it is determined that N'is equal to 0, the process of FIG. 22 ends. If it is determined that N'is not equal to 0, the routine proceeds to step 204, where the processing of FIGS. 23 to 25 is executed to change the program data in the RAM 52 with the change data in the EEPROM 54.

[ Detailed Procedure for Changing Program Data (see FIG. 2
3 to FIG. 25) ] In FIGS. 23 to 25, the adapter has its own R
9 is a flowchart of a detailed procedure for changing the program data in the AM 52 with the change data in the EEPROM 54.

In step 501 of FIG. 23, it is determined whether the checksum of the management data area is normal. If it is determined that this checksum is not normal, FIG.
The process of FIG. 25 ends. If it is determined that the checksum is normal, the process proceeds to step 502. In step 502, the MPU 51 stores the number N'of changed data blocks to be used for changing the program data in the register provided therein. As described above, the number N'of changed data blocks to be used for changing the program data is set in the "number N'of changed data blocks to be used" area of the AOPD (FIG. 12), and the changed data transfer instruction is issued. Alternatively, it is supplied to the adapter from the processor of the communication control processing unit by the issuance of the initial program loading command, and is stored in the management data area in the EEPROM 54. As mentioned above, when the processor gives the initial program loading instructions to the adapter using the format of FIGS. 11 and 12, already after the modified data has been transferred to the EEPROM 54 in the adapter, The area of the "start address of the changed data storage area" may be all "0", and at this time, in the above-mentioned "number of changed data blocks N'to be used N '" column, it is already stored in the EEPROM 54. Of the change data of a plurality of blocks, the RAM 52
It is also possible to newly set whether to apply to the above program data and instruct the adapter.

Next, in step 503, the MPU
51 sets “1” as the variable M. Then, in step 504, the MPU 51 determines that the EEPROM
From 54, the change data of the number of blocks equal to the above variable M is read. Then, in step 505, it is determined whether the checksum included in the header of each changed data block is correct. If it is determined that the checksum is incorrect, the processing of FIGS. 23 to 25 ends (abnormal end). When the checksum is determined to be correct in step 505, the process proceeds to step 506, and the value of “current version” in the header area (FIG. 7) is displayed in the RAM 52 of the adapter and is currently held in the RAM 52. It is determined whether it is equal to the version value of the program data. As will be described later, when the program data in the RAM 52 is changed by the change data block stored in the EEPROM 54, the version value corresponding to the change data block is written in a predetermined area of the RAM 52. If it is determined in step 506 that the value of the "current version" of the header area (FIG. 7) is not equal to the value of the version of the program data currently held by the RAM 52, the processing of FIGS. 23 to 25 ends. (Abnormal termination). If it is determined in step 506 that the value of the "current version" in the header area (FIG. 7) is equal to the value of the version of the program data currently held by the RAM 52, the process moves to step 507 and the changed data block concerned. Read the change data of the first (first) unit of the.

In step 508, the type of read unit is determined. This type is "0
If it is determined to be 0 ", the process proceeds to step 509. Alternatively, if it is determined that the type is" 01 ", the process proceeds to step 511. In step 509, the MPU 51 performs the above process. The data corresponding to the address of the unit is read from the RAM 52 as "current data", and in step 510 it is determined whether it is equal to "old data" included in the unit.
Here, if it is determined that they are not equal, the processing in FIGS. 23 to 25 ends (abnormal end). If it is determined in step 510 that they are equal, the process proceeds to step 511.

In step 511, the MPU 51
Reads the change data of the next unit. Then, in step 512, it is determined whether the end mark is detected. When the end mark is detected in step 512, the process proceeds to step 513, and when the end mark is not detected, the process returns to step 508 to process the next unit.

In step 513, the MPU 51
Reads again the contents of the first (first) unit of the modified data block from the EEPROM 54. Then, in step 514, the MPU 51 determines that the RAM
At 52, the program data having the same address as the address of the unit is rewritten with the change data of the unit. Then, the process proceeds to step 515 to read the change data of the next unit of this change data block. In step 516, it is determined whether the end mark has been detected. Step 51
If the end mark is detected in step 6, step 517
If the end mark is not detected, the process returns to step 514 to process the next unit.

In step 517, the MPU 51
Rewrites the "current version" display of the program data in the RAM 52 described above with the "new version" information in the header. And step 51
At 8, the variable M is incremented by 1. Next, in step 519, the above-mentioned variable M
, It is determined whether or not it has become equal to the number N ′ of blocks of the changed data to be changed. If they are equal, then FIG.
25. The processing of FIG. 25 is completed, and if they are not equal to each other, the processing shifts to the processing of step 504 in order to make a change with the change data of the version.

[ Others ] As described above, according to the configuration of the present invention, the firmware can be changed easily and at high speed. In addition, for example, as in the configuration of FIG. 2, the firmware change data can be transferred to a distant device via a communication network to change the firmware. it can. Furthermore, for example, the processor in the communication control processing device of the above embodiment can easily cause the plurality of adapters to change the firmware.

Another advantage of the present invention is that once the modified program data does not work properly,
The firmware can be reverted to the old version again. For example, in the above-described embodiment, the processor 40 ₁ , 4 indicates that the operation of the adapter becomes abnormal after the program data is changed up to a certain version number.
If either 0 ₂ or 40 ₃ is detected, the processor can instruct the adapter to change a smaller number of versions of program data to revert the firmware to the older version. This instruction sets the function code FNC CODE to "0.
After issuing the IAD instruction set to 3 "(FIGS. 13 and 20), an initial program loading (IPL) instruction may be issued, or as mentioned above, the change in the AOPD should be made. It may also be possible to issue an initial program loading (IPL) instruction in which the number N'of changed data blocks is set to a smaller number, thus instructing the adapter to change the program data of a smaller number of versions. You can then revert to the old version of the adapter firmware.

[0072]

As described above, according to the firmware changing system of the present invention, even if the data processing device requiring the firmware change is located far away, or the firmware changing is requested. Even if multiple data processing devices are distributed over a wide range, the firmware can be easily and quickly changed, and even when the changed data does not operate normally, the old version of the firmware can be changed. The effect is that it can be easily restored.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a configuration example of a distributed data processing system to which the present invention is applied.

FIG. 3 is a diagram showing a configuration of a communication control processing device in the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an adapter in the communication control processing device according to the embodiment of the present invention.

FIG. 5 is a flowchart showing processing by a processor for transferring change data to an adapter.

6 is a diagram showing an example of a format of change data stored in an EEPROM having the configuration of FIG.

7 is a diagram showing an example of a format of a header area in the change data stored in the EEPROM in the configuration of FIG.

8 is a diagram showing one type of each unit of change data in the change data stored in the EEPROM in the configuration of FIG. 4. FIG.

9 is a diagram showing one type of each unit of change data in the change data stored in the EEPROM in the configuration of FIG. 4. FIG.

FIG. 10 is a diagram showing an example of an end mark.

FIG. 11 is a diagram showing a general format of an I / O instruction (command) according to the embodiment of the present invention.

FIG. 12: Adapter operation descriptor AOP
It is a figure which shows an example of the format of D.

FIG. 13 is a diagram showing an example of a function code.

14 is a diagram showing an example of a format of a change data storage area in a RAM in each of a plurality of processors in the communication control processing device in FIG.

FIG. 15 is a flowchart showing processing by a processor for transferring change data to an adapter.

FIG. 16 is a flowchart showing processing by a processor for transferring change data to an adapter.

FIG. 17 is a flowchart showing processing by a processor for transferring change data to an adapter.

FIG. 18 is a flowchart showing processing by the adapter for transferring change data to the adapter.

FIG. 19 is a flowchart showing processing by an adapter for transferring change data to the adapter.

FIG. 20 is a flowchart showing processing by an adapter for transferring change data to the adapter.

FIG. 21 is a flowchart showing processing by the adapter for transferring change data to the adapter.

FIG. 22 is a flowchart showing a process of initial program loading in the adapter.

FIG. 23 is a flowchart showing a process of loading change data into a ROM in the adapter by the adapter.

FIG. 24 is a flowchart showing a process of loading change data into a ROM in the adapter by the adapter.

FIG. 25 is a flowchart showing a process of loading change data into a ROM in the adapter by the adapter.

[Explanation of Codes] 1 ... Data processing device 2 ... Change data supply means 3 ... Processor 4 ... Execution program holding means 5 ... Fixed program data storage means 6 ... Change data storage means 7 ... Fixed program data loading means 8 ... Execution program change Means 9 ... Change data transfer means 10 ... Transfer command receiving means 11 ... Change data holding means 12 ... Transfer command issuing means 13 ... Change data transfer path 17, 27 ... Host computer 18, 28 ... Database 19, 29 ... Communication control processing device 20, 30 ... Auxiliary storage device 21, 22, 23 ... Network processor 24 ... Maintenance center 25 ... Terminal device 26 ... Switch 31 ₁ , 31 ₂ ... Common memory 33 ₁ , 33 ₂ , 38 ₁ , 38 ₂ ... Bus handler 34 ₁ , 34 ₂ ... I / O device 35 ... Line switching circuit 36 ₁ , 36 ₂ , 36 ₃ , 36 ₄ ... Adapter 37 ... Transmission line 40 ₁ , 40 ₂ , 40 ₃ ... Processor 41 ₁ , 41 ₂ ... System bus 42 ₁ , 42 ₂ ... I / O bus 50 ... Bus controller 51 ... MPU 52 ... RAM 53 ... ROM 54 ... EEPROM 55 ... Device controller or line interface 56 ... Local bus

Claims (8)

[Claims] 1. A firmware changing system for changing the firmware of a data processing device (1), for holding a processor (3) for executing a program and data of the program executed by the processor (3). An execution program holding means (4), a fixed program data storage means (5) for storing fixed program data, and change data for changing the fixed data, which are external to the data processing device (1). From the change data storage means (6) capable of writing the change data, the fixed program data is read from the fixed program data storage means (5), and the fixed program data is stored in the execution program holding means (4). Fixed program data loading means (7) for loading, and the execution program The program data held in the holding means (4) in, possess an execution program change means (8) to change by changing the data held in the change data storing means (6), corresponding to the respective versions Each block is changed
Address of each data and the address of the version.
New data and version
Data of the address of the old version by one bell
The execution program changing means (8) includes
The data in the RAM holding means (4) is updated from the old version.
The execution program changing means (8) changes the data in the execution program holding means (4).
Before updating, the data of the old version of each address
And the same program in the execution program holding means (4).
The comparing means for comparing the data of the dress and the old version of each address by the comparing means.
In the execution program holding means (4).
It is determined that the data of the same address is not equal
Sometimes, an abnormal stop means for stopping the change process is provided.
A firmware changing system characterized by: 2. The fixed program data includes a plurality of partial programs respectively corresponding to the fixed program data loading means (7) and the execution program changing means (8), and the fixed program data loading means ( 7. The firmware changing system according to claim 1, wherein the execution program data loading means (7) and the execution program data loading means (8) are respectively realized by execution of the plurality of program parts by the processor (3). 3. A change data supply means (2) provided outside the data processing device (1) for supplying change data to be stored in the change data storage means (6). Firmware change system. 4. The change data supply means (2) includes a change data holding means (11) for holding change data to be stored in the change data storage means (6), and the data processing device (1). And a transfer command issuing unit (12) for issuing a transfer command, wherein the firmware changing system includes a change data transfer path (13) from the change data holding unit (11) to the change data storage unit (5). ), The data processing device (1) includes transfer command receiving means (10) for receiving the transfer command, and the firmware changing system includes the transfer command receiving means (10). When the transfer command is received, the change data is read from the change data holding means (11), and the change data is stored in the change data holding means (11). A change data transfer means (9) for transferring the change data from 1) to the change data storage means (6) through the change data transfer path (13) and writing the change data in the change data storage means (6). Item 3. The firmware changing system according to item 3. 5. The change data includes change data of a plurality of versions, and the firmware changing system is held by the execution program holding means (4) with respect to the execution program changing means (8). It has a change version command means for instructing to change the program data by the change data up to a specific version, and when the execution program changing means (8) receives the instruction about the version, the execution program holding means. The firmware changing system according to claim 1, wherein the program data held in (4) is changed in order from the old version to the new version by the change data up to the specific version. 6. The change data of the plurality of versions includes:
The change data storage means (6) is divided into a plurality of blocks corresponding to the plurality of versions and arranged in the order of the old version to the new version, and the changed version command means stores the plurality of blocks up to the specific version. The firmware change system according to claim 5, wherein the version is commanded according to the number of blocks containing change data. 7. Each block corresponding to the change data includes information indicating a corresponding version, and the execution program holding means (4) sets an area showing a version of a change received by the program data held by itself. The execution program changing means (8) has the execution program holding means (4) according to the change data of each block.
7. The firmware changing system according to claim 6, wherein the contents of the area indicating the version of the received change are updated based on the information indicating the corresponding version every time the program data is changed. 8. The execution program changing means (8) comprises:
Before changing the program data of the execution program holding means 4 by each block corresponding to each version,
9. The firmware changing system according to claim 8, further comprising version confirmation means for confirming whether or not the content of the area indicating the version of the received change indicates the version to be changed by the change data of the version of the block.