JPH0816894B2 - Direct memory access controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a DMA controller having a data buffer memory inside, and a memory controller for the purpose of changing the burst transfer time by making the number of effective bytes variable. A memory address register that holds the address and a count address for counting the number of transfer bytes
A register, a data buffer memory for temporarily storing transfer data, a valid byte limit register for limiting the valid byte count of the data buffer memory, and a memory buffer for accessing the data buffer memory.
By providing a pointer, the number of valid bytes in the data buffer memory is a block of data for burst DMA transfer, and the number of valid bytes is variable, so that the burst transfer time can be changed.

[Industrial applications]

The present invention is a DM having an internal data buffer memory.
A control device (direct memory access control device). DMA transfer is indispensable in the field that requires high-speed data transfer with I / O devices such as control computers.

[Conventional technology]

FIG. 6 is a block diagram of a conventional DMA control method. In the figure, 1 is a DMA controller, 2 is a memory, 3 is an I / O device, 4 is a central processing unit, 11 is a memory address register, and 12 is a byte count register.

As shown in FIG. 6, the conventional DMA control system has a DMA controller 1 having a memory address register 11 for holding a memory address and a count register 12 for counting the number of transfer bytes, Memory 2 and I / O
It is composed of a device 3 and a central processing unit 4.

In the conventional example of this type, when the central processing unit 4 sets the memory address and the number of transfer bytes to the DMA control unit 1 and activates it, the transfer is continued until the value of the count register 12 becomes zero. . At this time, a method of continuously using the bus (burst transfer method) or DM for one word
Generally, the bus is released every time A transfer is performed (cycle steal transfer system).

[Problems to be Solved by the Invention]

The former method enables fast and efficient transfer because it takes a short time to control the bus.
On the other hand, since the bus is continuously used for a long time, there is an adverse effect on the real-time property of the entire system, such as a delay in response to an interrupt request during that time.

The latter method has no adverse effect on real-time performance,
There is a drawback that the time required for controlling the bus control becomes too long.

The present invention was created in view of this point,
It is an object of the present invention to provide a DMA control method in which the burst transfer time can be changed by making the number of effective bytes variable.

[Means for solving the problem and its action]

FIG. 1 is a block diagram showing a DMA control device of the present invention. In the figure, 1 is a DMA controller, 11 is a memory address register (MAR), 12 is a byte count register (BCR), 13 is a valid byte limit register, and 14 is a memory pointer register (MPR). , 15 is a data buffer memory, and 17 and 18 are data buses. The DMA controller 1 has a memory address register 1
1, a byte count register 12, a valid byte number limit register 13, a memory pointer register 14, a data buffer memory 15, and the like. The memory address register 11 holds an address for accessing the memory connected to the data bus 17. The byte count register 12 counts the number of transferred bytes. The data buffer memory 15 temporarily stores transfer data. The effective byte number limit register 13 is for limiting the effective byte number of the data buffer memory 15. The memory pointer register 14 holds an address for accessing the data buffer memory 15.

As an example, the operation in the case of DMA transfer from the I / O device to the memory will be described. The data input from the I / O device to the DMA control device 1 via the data bus 18 are sequentially stored in the data buffer memory 15 at the address indicated by the memory pointer register 14. When the amount of data in the data buffer memory 15 reaches the number of bytes indicated by the valid byte limit register 13, the data in the data buffer memory 15 is addressed by the address bus 16 via the data bus 17. It is transferred one after another by burst transfer to the memory address to be singed. In this case, if the value of the valid byte number limit register 13 is increased, the number of bytes stored in the data buffer memory at one time is increased, so that the burst transfer time becomes longer, and conversely, if it is made smaller, the burst transfer time becomes shorter. The value may be selected according to the system. The value of the valid byte limit register 13 can be rewritten by the central processing unit 4.

〔Example〕

FIG. 2 is a block diagram of a configuration example of a hardware mechanism for detecting an excess of the number of valid bytes. In the figure, 19
Is a decoder, 20 and 21 are AND circuits, and 22 is an OR circuit.

A valid byte of the memory pointer register 14 is selected by using a signal obtained by decoding the value of the valid byte limit register 13 by the decoder 19. For example, the AND circuit 20 becomes “true” when the number of valid bytes exceeds 2 ^m bytes.
The D circuit 21 becomes "true" when the number of effective bytes of 2 ^{m-L + 1} is exceeded, and the output of the OR circuit 22 becomes "true". For example, when performing DMA transfer from I / O device to memory,
Each time the data from the I / O device is stored in the data buffer memory 15, the value of the memory pointer register 14 is incremented, and if the output of the OR circuit 22 becomes “true”, the data buffer memory 15 Burst transfer of data stored in memory to memory. This operation count register
Repeat until 12 becomes zero. Transfers from memory to I / O devices can be controlled as well.

FIG. 3 is a diagram showing a configuration example of a sequencer used in the present invention. In the figure, 23 is a counter, 24 is a microcode memory, and 25 is a multiplexer.

Although not shown in FIG. 1, the sequencer of FIG. 3 exists in the DMA control device 1 and controls each unit of the DMA control device 1. The counter 23 normally increments the count value by 1, but when the branch address input control signal is on, the branch address of the read microcode is set in the counter 23. The microcode of the address designated by the counter 23 is read from the microcode memory 24. The multiplexer 25 checks whether or not the branch condition specified by the content of the branch condition selection unit of the read microcode is satisfied, and if the specified branch condition is satisfied, the branch address input control is performed. Turn on the signal.

FIG. 4 is a diagram showing a processing flow when data is transferred from the I / O to the memory. Note that these processes are performed under the control of the sequencer.

The central processing unit activates the DMA controller (DMAC) and I / O devices.

I / O device requests data to DMA controller
Wait until DREQ is turned on.

The DMA controller selects the data register port of the I / O device to transfer data from the I / O device to the data buffer memory.

The DMA controller checks whether or not the number of bytes of data in the data buffer memory exceeds the number of valid bytes, and if yes, returns to and if no, returns to.

The DMA controller issues a request to acquire the system bus.

If you get the bus data buffer memory →
Transfers data to memory. (It continues until the data buffer memory becomes empty.) Transfer count (synonymous with byte counter register)
Check if is zero. If No, the process returns to.

FIG. 5 is a diagram showing a processing flow when data is transferred from the memory to the I / O. Note that these processes are performed under the control of the sequencer.

The central processing unit activates the DMA controller and I / O device.

The DMA controller issues a request to acquire the system bus.

When the bus is acquired, the data is transferred from the memory to the data buffer memory.

The DMA controller checks whether or not the number of bytes of data in the data buffer memory exceeds the number of valid bytes, and if yes, returns to and if no, returns to.

I / O device requests data to DMA controller
Wait until you turn DREQ on.

The DMA controller selects the data register port of the I / O device to transfer data from the data buffer memory to the I / O device.

The process of, is repeated until the data buffer memory becomes empty.

It is checked whether the transfer counter is "0", and if No, the process returns to.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, the data transfer between the memory and the data buffer memory and the data transfer between the data buffer memory and the I / O device are performed on different data buses. Since it is performed, the memory can be released to the CPU side during the latter data transfer between the data buffer memory and the I / O device.
The bus load on the bus can be reduced. Further, according to the present invention, the value of the valid byte number limit register can be set according to the characteristics of the system. For example, in a system that emphasizes real-time performance, the setting value of the effective byte count limit register is reduced, and in a system that emphasizes performance, the setting value of the effective byte count limit register is increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a DMA control device of the present invention, FIG. 2 is a block diagram of a configuration example of a hardware mechanism for detecting an excess of the number of effective bytes, and FIG. 3 is a configuration example of a sequencer used in the present invention. FIG. 4 is a block diagram showing the processing flow when transferring data from the I / O to the memory. FIG. 6 is a diagram showing the processing flow when transferring data from the memory to the I / O. FIG. 6 is a diagram showing a conventional DMA control method. 1 ... DMA control device, 2 ... memory, 3 ... I / O device, 4
...... Central processing unit, 11 …… Memory address register, 12 …… Byte count register, 13 …… Effective byte limit register, 14 …… Memory pointer register, 15 …… Data buffer memory , 17 and 18 …… Data bus, 19 …… Tegoda, 20 and 21 are AND circuits, 22 …… OR
circuit.

Claims (2)

[Claims] 1. A data buffer memory capable of temporarily storing transfer data for continuous transfer, a first bus for transferring data between the memory and the data buffer memory, and an I / O. A second bus for transferring data between the device and the data buffer memory, a valid byte number limit register for limiting the valid byte number of the data buffer memory, and a data buffer memory A memory pointer that holds the access address, a comparison circuit that compares the value of the valid byte limit register with the value of the memory pointer, and a transfer byte of the data transferred between the control means, the I / O device, and the memory. A count register for counting the number; and, when the data is transferred from the I / O device to the memory, the control means sends the data from the step S1 I / O device. The received data in the data buffer
If the output of the comparison circuit indicates that the value of the memory pointer does not exceed the value of the valid byte limit register, the process of step S1 is performed. If the output of the comparison circuit indicates that the value of the memory pointer exceeds the value of the valid byte limit register, the data transfer from the I / O device to the data buffer memory is stopped. Then, in step S3, a bus acquisition request for data transfer between the memory and the data buffer memory is performed in step S3. If the bus is acquired, the process proceeds to step S4, and in step S4 data buffer -Burst transfer all data stored in memory to memory and refer to the value of the count register in step S5 to instruct by the central processing unit. Check whether the data for the number of transfer bytes that has been transferred is transferred from the I / O device to the memory, and if not,
The control means performs control for performing a series of processes such as returning to the process of step S1. A bus acquisition request for transfer is made, and if the bus can be acquired, the process proceeds to step S2 ′, and step S2 ′ increments the value of the memory pointer each time data is written to the data buffer memory, When data is burst-transferred from the memory to the data buffer memory, and the output of the comparison circuit indicates that the value of the step S3 ′ memory pointer register does not exceed the value of the valid byte limit register, Return to the processing of step S2 ′,
If the output of the comparison circuit indicates that the value of the pointer register exceeds the value of the valid byte number limit register, the data transfer from the memory to the data buffer memory is stopped and step S4 ' In step S4 ', the data in the data buffer memory is transferred to the I / O device, and in step S5', if the data buffer memory is empty, step S6 '.
If the data buffer memory is not empty, the process returns to step S4 ', and the data for the number of transfer bytes designated by the central processing unit is referred to by referring to the value of the count register in step S6'. From memory I /
A direct memory access control device characterized by performing a control for performing a series of processes of checking whether the data has been transferred to the O device and, if not, returning to the process of step S1 ′. 2. The burst data transfer time between the memory and the data buffer memory and the data transfer time between the data buffer memory and the I / O device are adjusted by adjusting the value of the valid byte limit register. The direct memory access control device according to claim 1, wherein the direct memory access control device is adjustable.