JPH0817030B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a first-in first-out (FIFO) memory, a register is provided between a storage unit (cell matrix) and a data output to read data from the cell matrix to a data output. By reading the storage contents of the cell matrix to the register in advance by the preceding read instruction clock, the reading speed is increased.

[Industrial applications]

The present invention relates to a semiconductor memory device, that is, a FIFO memory, in which a register is added to an output section to perform prefetching.

[Prior Art] A conventional FIFO memory will be described with reference to FIGS. 4 and 5. Reference numeral 1 denotes a dual-port MOS static type memory cell array. As shown in FIG. On the other hand, the write side word line WL (W) and the read side word line WL (R) are connected, and the write side bit line BL (W), ▲ ▼ (W) and the read side bit line are connected.
BL (R) and ▲ ▼ (R) are connected. In the write operation, the write side word line WL (W) is selected by the write row decoder 2-W and the write driver 3-W, and the write side bit line BL (W) and ▲ ▼ (W) are set in the write column decoder 4-. It is selected by W and the write gate 5-W, and as a result, the input data Din is written in the selected memory cell MC via the write amplifier 7. The write pointer 8 gives an address to the write row decoder 2-W and the write column decoder 4-W. The write pointer 8 counts the write clock W after receiving the write reset signal ▲ ▼ (W), This count value is i (i
= 0, 1, ...), the memory cell at address i of the memory cell array 1 is selected. In the write pointer 8, CL is a clear terminal and CK is a clock terminal.

On the other hand, in the read operation, the read side word line WL
(R) is read row decoder 2-R and read driver 3
-R, the read side bit lines BL (R) and ▲ ▼ (R) are selected by the read column decoder 4-R and the read gate 5-R. As a result, the data of the selected memory cell MC is sense amplifier 6 Is sensed by and output as output data Dout via the latch / read amplifier 10. It is the read pointer 9 that gives an address to the read row decoder 2-R and the read column decoder 4-R. The read pointer 9 counts the read clock after receiving the read reset signal ▲ ▼ (R). When the count value is j (j = 0, 1, ...), the memory cell at address j of the memory cell array 1 is selected. In the read pointer 9, CL is a clear terminal and CK is a clock terminal.

In FIG. 5, transistors Q _W and Q _W ′ represent one bit of write gate 5-W, and transistors Q _R and Q W
Q _R 'represents one bit of read gate 5-R, SA represents a 1 bit of the sense amplifier 6.

[Problems to be solved by the invention]

The read operation of FIG. 4 will be described in detail with reference to FIG. 6. A read reset signal ▲ ▼ (R) not shown.
At the (j-1) th low level of the read clock after the reception of, the output RP of the read pointer 9 (starting from address 0) indicates the address (j-1), and therefore the selection unit (2-R .About.5-R) executes the access operation of the memory cell at the address (j-1), and as a result, the output data Dout becomes as shown in the figure. Next, when the read clock rises at time t ₁ , the read pointer 9 counts up by +1 at time t ₂ after the time T _A, and its output RP changes from address (j-1) to address j. Then, the selection unit at time _{t 3 (2-R~5-R} ) moves to the access operation of the memory cell of the j address, also performed sensing operation during which the output data Dout at time t ₄ is the j address It indicates the stored contents. In this case, the cycle time T _CYC is T _{CYC to} T _A + T _B + T _C (1) where T _A is the time from the rise of the read clock to the determination of the output RP of the read pointer 9 and T _B is the selection unit (2 -R to 5-R) until the read data sensing is completed, T _C is the time between the sensing completion and the output data Dout is determined through the read amplifier 10, and the access time T _AC is determined by T _{AC to} T _B + T _C (2).

As described above, there is a problem that the read time of the FIFO memory is long.

Therefore, it is an object of the present invention to provide a FIFO memory that speeds up the read operation.

[Means for solving problems]

The means for solving the above problem is shown in FIG. In FIG. 1, the storage unit is of a dual port type in which addresses 0, 1, ..., N-1 are assigned, and therefore,
A writing operation and a reading operation can be performed in parallel with respect to the storage unit. The write operation is performed by the write pointer means. That is, the write pointer means is reset by the write reset signal ▲ ▼ (W), counts the write clocks after receiving this write reset signal, and when the count value is i (i is 0, 1, ... The input data Din is written in the address i of the storage unit. On the other hand, the read operation is performed by the read pointer means. That is, the read pointer means reads out the stored contents of address 0 of the storage section at the same time when it is reset by the read reset signal ▲ ▼ (R), for example, its rising edge,
The rising edge of the read clock is counted together with the rising edge of the read reset symbol, and when the counted value is j (j also changes to 0, 1, ...), the stored contents of the address (j + 1) of the storage unit are read out. It is a thing. Then, the data read by the read pointer means is temporarily stored in the register, and the register sends the stored data as output data Dout each time the read clock is received.

[Action]

According to the above means, the read pointer means reads the data of the address preceding the data to be originally output and stores it in the register. Therefore, when the next read command is input, the data to be output is not the storage unit but the data read in advance from the register as the output data.

[Embodiment] FIG. 2 is a block circuit diagram showing an embodiment of a FIFO memory according to the present invention, in which an AND circuit 11 and a register 12 are added to the elements of FIG. That is, with the addition of the AND circuit 11, the read pointer 9
The read reset signal ▲ ▼ (R) acts not only as a reset signal for the read pointer 9 but also as a read clock. Therefore, the output RP of the read pointer 9 in FIG. 2 is the read pointer 9 in FIG. Will be +1 ahead of the output RP of, that is, 1
The read operation is preceded by the read cycle. On the other hand, the data read from the memory cell array 1 is once stored in the register 12 and then sent as output data Dout. That is, the read data from the memory cell array 1 is delayed by one read cycle. After all, in the same read cycle, the FIFO memory of FIG. 2 is also replaced by the FIFO memory of FIG.
The memory also reads the stored contents of the same address, but in the FIFO memory of FIG. 2, the read data Dout
Since the data already read from the memory cell array 1 to the register 12 is output, the read cycle itself can be shortened. The read operation of the FIFO memory shown in FIG. 2 will be described below.

Referring to FIG. 3, the read clock signal (j-
1) When the address is at the low level, the read pointer 9 also counts the read reset signal ▲ ▼ (R) as the read clock, so its output RP indicates the address j, and accordingly, the selection unit (2-R to 5). -R) executes the access operation of the memory cell at address j, and as a result, the output data Dout becomes as shown in the figure. Next, when the read clock rises at time t ₁ , the read pointer 9 becomes + at time t ₂ after the time T _A.
Count up 1 and output RP from address j (j +
1) Change to address. Then, at time t _{3, the} selection section (2-R
.About.5-R) shifts to the access operation of the memory cell at the address (j + 1), and the sense operation is also performed during that time. At this time,
In parallel the register in response to the falling of the read clock
12 moves to transfer mode. That is, at time t ₄ , the data (j) in the register 12 is transmitted as the output data Dout via the read amplifier 10. After that, at time t ₅ , the operations of the selection units (2-R to 5-R) and the sense amplifier 6 are completed, and the stored contents of the memory cell at address (j + 1) are written in the register 12. Therefore, in this case, the cycle time T _CYC is determined by T _{CYC to} T _A + T _B (3), and the access time T _AC is T _{AC to} T _C ′ (4) where T _C ′ is the read clock. Register from the fall of
It is decided by the time to complete 12 transfer modes.

In this way, the cycle time T _CYC and the access time T _AC are reduced from the above equations (1) to (4).

In the above-described embodiment, the write pointer 8 and the read pointer 9 are reset separately.
The reset signals may be simultaneously reset.

〔The invention's effect〕

As described above, according to the present invention, the read cycle time and the read access time can be shortened by performing the preceding read, and therefore the read speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block circuit diagram showing an embodiment of a FIFO memory according to the present invention, and FIG. 3 is a timing for explaining the circuit operation of FIG. FIG. 4 is a block circuit diagram of a conventional FIFO memory, FIG. 5 is a detailed circuit diagram of the memory cell array of FIG. 4, and FIG. 6 is a timing diagram for explaining the circuit operation of FIG. . 1 …… Memory cell array, 2-W, 2-R …… Row decoder, 3
-W, 3-R …… Word driver, 4-W, 4-R …… Column decoder, 5-W, 5-R …… Gate, 6 …… Sense amplifier, 7 ……
Write amplifier, 8 ... Write pointer, 9 ... Read pointer, 10 ... Latch / read amplifier, 11 ... AND circuit, 12 ... Register.

Claims (1)

[Claims] 1. A memory cell array having a plurality of memory cells, word lines and bit lines, a row decoder for selecting the word lines, and a column decoder for selecting the bit lines.
A register that holds data transferred from the memory cell selected by the row decoder and the column decoder and sends out the held data in response to a read clock signal; and a read reset signal that is reset by a read reset signal. And a read pointer that sequentially generates an address to the column decoder and the row decoder by counting the read clock signal, and the read pointer also counts the reset signal, so that the memory is read at the i-th read clock signal. A semiconductor characterized in that a memory cell at address (i + 1) of a cell array is selected, data is transferred to an output register, and data already transferred to the register is read from the register to an output terminal. Storage device.