JPH0817035B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor memory device,
The present invention relates to a divided word line type semiconductor memory device having an improved operation speed.

[Prior Art] A divided word line method is used to shorten the access time and the current consumption of a semiconductor memory device. In the divided word line system, a front word line provided over a plurality of memory array blocks is provided separately from the word line connected to the memory cells. The word line can be selected for each memory array block by taking the logical product of the block selection signal for selecting the memory array block and the front word line signal.
Therefore, the number of memory cells selected by one access can be reduced, and high speed operation and low power consumption of the semiconductor memory device can be achieved.

Generally, the same polysilicon as the gate of the transistor is used for the word line, and the aluminum wiring provided in the layer different from the bit line is used for the front word line. Therefore, there is stray capacitance between the bit line and the front word line. Since there is stray capacitance, it is necessary to take measures to prevent adverse effects on operation.

FIG. 3 is a circuit diagram showing an example of a dynamic random access memory (hereinafter referred to as DRAM) using a conventional divided word line system. Referring to FIG. 3, this DRAM
Includes two memory array blocks 1 and 2, a front word line RGSL provided over memory array blocks 1 and 2, and a row decoder 3 connected to front word line RGSL. The row decoder 3 is composed of a NAND circuit and an inverter.

For example, in the memory array block 1, one word line WL0 to which the memory cell M is connected is provided for one front word line RGSL. An NMOS transistor 11 is connected between the front word line RGSL and the word line WL0, and an NMOS transistor 12 is connected between the word line WL0 and the ground. The gates of the transistors 11 and 12 are connected so as to receive the block selection signals B0 and ▲ ▼, respectively. On the other hand, the memory array block 2 also has a similar circuit configuration, and B1 and ▲ ▼ are given as block selection signals.

In operation, the row decoder 3 causes the X address signal X0
To Xn, only one of the 2 ⁿ preword lines RGSL is selectively brought to a high level.
Therefore, when word line WL0 of memory array block 1 is selected, high level block select signal B0 is applied, and transistor 11 is turned on in response to this signal B0. As a result, the word line WL0 is brought to a high level,
The memory cell M is accessed.

FIG. 4 is a circuit diagram showing another example of the DRAM using the conventional divided word line system. Referring to Figure 4, this DR
In AM, two word lines are provided for one front word line RGSL. For example, memory array block 1
In, a word line WL00 and WL01 are provided, and a NAND gate 13 and an inverter for selectively activating them are provided.
14 are connected. One input of the NAND gate 13 is connected to the front word line RGSL, and the other input is a block selection signal.
B0 and X address signal X0 or the signal of the logical product of ▲ ▼ are connected. On the other hand, the memory array block 2 also has a similar circuit configuration.

In operation, for example, when word line WL00 in memory array block 1 is activated, high-level AND signal B0X0 is applied. As a result, only word line WL00 is selectively brought to a high level.

[Problems to be Solved by the Invention] In the DRAM shown in FIG. 3, one front word line RGSL is used.
Letting C be the parasitic capacitance generated between the bit line 10 and one bit line 10, the total parasitic capacitance becomes (total number of word lines) × C, which is a considerably large value. Further, since the front word line and the word line are connected only by the NMOS transistor, the voltage level of the word line at the high level is reduced from the level of the power supply voltage by the threshold voltage of the transistor, As a result, the driving capability of the memory cell is reduced. In addition, bringing the word line to a high level through the NMOS transistor causes the transistor (eg, 11) to be turned off as the voltage level at the drain of the transistor rises. As a result, the speed at which the voltage level of the word line rises becomes slower than when a PMOS transistor is used.

In the DRAM shown in FIG. 4, since two word lines are provided for one front word line, the total parasitic capacitance generated between the front word line and the bit line is (word The total number of lines) x C x 1/2, which is reduced. Moreover, since the voltage level of the word line also rises to the power supply voltage level, the above delay is small, but the NAND gate 13 and the inverter
14 causes a delay and prevents high speed operation.

The present invention has been made to solve the above problems, and an object thereof is to quickly activate and deactivate a divided word line in a semiconductor memory device using the divided word line system. .

[Means for Solving the Problems] A first semiconductor memory device of the present invention is a divided word line type semiconductor memory device, each corresponding to a plurality of memory cells arranged in a matrix and each row. A plurality of memory array blocks each including a divided word line and a bit line provided corresponding to each column, and the divided word lines are grouped in pairs to form pairs. A front word line corresponding to each pair of divided word lines of the array block and commonly provided to the plurality of memory array blocks, corresponding to each memory array block, and each of the corresponding memory array blocks. First and second signal transmission line pairs provided commonly to one and the other of the divided word line pairs, and provided corresponding to one of the divided word line pairs of each memory array block, respectively. Is connected between a corresponding divided word line and a front word line corresponding to the divided word line, and each input electrode is connected to one and the other of the first signal transmission line pair corresponding to the divided word line. A first transmission gate including a first transistor of a first conductivity type and a second transistor of a second conductivity type, a first transmission gate provided corresponding to each first transmission gate, and a corresponding first transmission A first conductive type transistor connected between a divided word line corresponding to a gate and a line of ground potential, the input electrode of which is commonly connected to the input electrode of the first transistor of the corresponding first transmission gate. No. 3 transistor, each divided word line pair of each memory array block are provided corresponding to the other divided word line and its divided word line. Is connected between the pre-word line corresponding to the line,
Each input electrode is connected to one and the other of the second signal transmission line pair corresponding to the divided word line, respectively.
A second transmission gate including a fourth transistor of the conductivity type and a fifth transistor of the second conductivity type, the second transmission gate being provided corresponding to each second transmission gate, and corresponding to the corresponding second transmission gate. A sixth transistor of the first conductivity type, which is connected between the divided word line and a line of ground potential, and whose input electrode is commonly connected to the input electrode of the fourth transistor of the corresponding second transmission gate, According to an address signal given from the outside, any one of the plurality of front word lines, one of the plurality of memory array blocks, and one of the memory array blocks. A selection circuit for selecting the first or second pair of signal transmission lines, and a selection circuit selected by the selection circuit. An activation signal for activating the divided word line is applied to the storage word line, and the first or second transmission gate is provided to the first or second signal transmission line pair of the selected memory array block. It is characterized in that a signal generation circuit for providing a selection signal for making the third transistor or the sixth transistor non-conductive is provided.

A second semiconductor memory device of the present invention is a divided word line type semiconductor memory device, each of which has a plurality of memory cells arranged in a matrix and divided words provided corresponding to each row. A plurality of memory array blocks each including a line and a bit line provided corresponding to each column, and the divided word lines are grouped in pairs to form a pair;
A preword word line corresponding to each divided word line pair of each memory array block and provided in common to the plurality of memory array blocks, provided corresponding to each divided word line pair of each memory array block, An inverter that outputs an inversion signal of a signal applied via the front word line corresponding to the corresponding pair of divided word lines, the divided word line of each memory array block corresponding to each memory array block First and second signal transmission lines provided in common to one and the other of the pair, provided corresponding to one of the divided word line pairs of each memory array block, each corresponding divided word line and its divided It is connected between the first signal transmission lines corresponding to the word lines, one input electrode of which is connected to the front word line corresponding to the divided word lines, and the other input voltage is connected. A first transmission gate including a first transistor of a first conductivity type and a second transistor of a second conductivity type for receiving an output of an inverter corresponding to the divided word line, corresponding to each first transmission gate Connected between the divided word line corresponding to the corresponding first transmission gate and the ground potential line, and its input electrode is connected to the input electrode of the first transistor of the corresponding first transmission gate. A third transistor of the first conductivity type that is commonly connected, is provided corresponding to the other of the divided word line pairs of each memory array block, and each corresponds to the corresponding divided word line and the corresponding divided word line. Two signal transmission lines, one input electrode of which is connected to the word line corresponding to the divided word line, A second transmission gate, which includes a fourth transistor of a first conductivity type and a fifth transistor of a second conductivity type, the other input electrode receiving the output of the inverter corresponding to the divided word line, each second transmission gate. A fourth transistor of the corresponding second transmission gate, which is provided corresponding to the transmission gate and is connected between the divided word line corresponding to the corresponding second transmission gate and the ground potential line. A sixth transistor of the first conductivity type commonly connected to the input electrode of the first conductivity type, a front word line of any one of the plurality of front word lines, and a plurality of memories according to an externally applied address signal. Any one of the array blocks and the first or second memory array block A selection circuit for selecting a signal transmission line and a pre-word line selected by the selection circuit are made conductive with the first and second transmission gates and made non-conductive with the third or sixth transistor. And a signal generation circuit for giving an activation signal for activating the divided word line to the first or second signal transmission line of the selected memory array block. I am trying.

[Operation] In the first semiconductor memory device of the present invention, a pair of divided word lines is provided corresponding to each front word line in each memory array block, and each divided word line corresponds to each other. A transmission gate for charging and a transistor for discharging, which include a pair of transistors having different conductivity types, are provided. Further, first and second signal transmission line pairs are provided corresponding to one and the other of the divided word line pairs of each memory array block. Then, a selection signal is given to the transmission gate and the input electrode of the transistor from the selected signal transmission line pair, the transmission gate becomes conductive and the transistor becomes non-conductive, and the selected word line is divided from the selected word line through the transmission gate. An activation signal is applied to. In this way, the activation signal is applied to the divided word lines via the transmission gates, so that the level of the activation signal is prevented from lowering. Further, since a pair of divided word lines is provided for each front word line in each memory array block, the number of front word lines is reduced and the total parasitic capacitance associated with the front word lines is reduced. Also,
Since the activated divided word line is discharged and inactivated through the discharging transistor, it is necessary to separately provide an inactivation signal for deactivating the activated divided word line to the divided word line. There is no. As a result, the division word lines are activated and deactivated at high speed.

Further, in the second semiconductor memory device of the present invention, a pair of divided word lines are provided corresponding to each front word line in each memory array block, and are electrically connected to each other corresponding to each divided word line. A transmission gate for charging and a transistor for discharging including a pair of transistors of different types are provided. Further, first and second signal transmission lines are provided corresponding to one and the other of the divided word line pairs of each memory array block, respectively.
An inverter is provided corresponding to each divided word line pair.
Then, a selection signal is applied from the selected front word line and the inverter to the transmission gate and the input electrode of the transistor, and an activation signal is applied from the selected signal transmission line to the divided word line via the transmission gate. In this way, the activation signal is applied to the divided word lines via the transmission gates, each front word line is provided with a pair of divided word lines in each memory array block, and the divided word lines are discharged. Since it is discharged and inactivated through the transistor for use in memory, the division word lines can be activated and deactivated at high speed as in the first semiconductor memory device.

[Embodiment of the Invention] FIG. 1 is a circuit diagram of a DRAM using a divided word line system showing an embodiment of the present invention. Referring to FIG.
This DRAM has two memory array blocks 1 and 2
And a front word line RGSL provided over the memory array blocks 1 and 2, and a row decoder 3 connected to the front word line RGSL. For example, in the memory array block 1, one front word line RGSL is connected to two word lines WL00 and WL01 connected to the memory cell M.
And are provided. Pre-word line RGSL and word line WL00 are connected via transmission gate 15. Transmission gate 15 is a PMOS transistor and NM
It consists of parallel connection of OS transistors. The gates of the two transistors forming the transmission gate 15 are connected to receive the signals {circle around (1)} and B0X0. NMOS transistor between word line WL00 and ground
16 are connected. The gate of transistor 16 is a signal ▲
▼ connected to receive.

Similarly, for the word line WL01, the transmission gate 17 is connected between the front word line RGSL and the word line WL01, and the NMOS transistor 18 is connected to the word line WL01.
Connected between 01 and ground. The gates of the two transistors that make up the transmission gate 17 are signals And B0 ▲ ▼ to receive the signal from the gate of transistor 18. Connected to receive. The memory array block 2 has the same circuit configuration.

In operation, the front word line RGSL is brought to a high level by the row decoder 3 when, for example, the word line WL00 is activated. The high level signal B0X0 and the low level signal ▲ ▼ are given, and the transmission gate 15 is turned on. Therefore, the word line WL00 is brought to a high level by the voltage from the front word line RGSL via the transmission gate 15.

Since the pre-word line RGSL and the word line WL00 are connected by the transmission gate 15, the voltage level of the pre-word line signal is not lost and the word line WL00
Given to. Therefore, the driving capability of the memory cell can be sufficiently obtained. Also, the speed at which the voltage of the word line WL00 rises to a high level does not slow down.

Since two word lines WL00 and WL01 are provided for one front word line RGSL, the total parasitic capacitance generated between the front word line RGSL and the bit line 10 is (word (Total number of lines) × C × 1/2, and it is possible to prevent adverse effects due to parasitic capacitance.

FIG. 2 is a circuit diagram of a DRAM using a divided word line system showing another embodiment of the present invention. Referring to FIG. 2, the difference from the DRAM shown in FIG. 1 lies in that the voltage for activating the word line is the block selection signals B0 and X.
It is supplied by an AND signal of the address signal X0 or ▲ ▼, and the front word line signal is used for switching control of the transistor. That is, for example, in the memory array block 1, the word line WL00 is transmitted via the transmission gate 15 to the signal B0X0.
Connected to receive. Transmission gate
The gates of the transistors that make up 15 are connected to receive the preword line signal and the signal inverted by inverter 10. Further, the gate of the NMOS transistor 16 connected between the word line WL00 and the ground is connected to the front word line RG.
Connected to SL.

In operation, when the pre-word line RGSL is activated and goes low, the high level AND signal B0X0 voltage provided via the transmission gate 15 brings the word line WL00 to a high level. Similar to the case of the DRAM shown in FIG. 1, the voltage level of the signal B0X0 is applied to the word line WL00, and the same effect can be obtained.

[Effects of the Invention] As described above, in the first and second semiconductor memory devices of the present invention, the pair of transistors whose activation signals for activating the divided word lines are different in conductivity type from each other. Since it is applied to the divided word lines through the transmission gates including it, the activation signal level is prevented from lowering. Further, since a pair of divided word lines is provided for each front word line in each memory array block, the number of front word lines is reduced and the total parasitic capacitance associated with the front word lines is reduced. Further, since the activated divided word line is discharged and inactivated through the discharging transistor, it is not necessary to separately provide an inactivation signal to the divided word line. Therefore, division word lines are activated and deactivated at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a DRAM using a divided word line system showing an embodiment of the present invention. FIG. 2 is a circuit diagram of a DRAM using a divided word line system showing another embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a DRAM using a conventional divided word line system. FIG. 4 is a circuit diagram showing another example of the DRAM using the conventional divided word line system. In the figure, 1 and 2 are memory array blocks, 3 is a row decoder, 10 is a bit line, M is a memory cell, RGSL is a front word line, and WL00 to WL11 are word lines.

Claims (2)

[Claims] 1. A divided word line type semiconductor memory device, each of which corresponds to a plurality of memory cells arranged in rows and columns, a divided word line provided corresponding to each row, and each column. A plurality of memory array blocks in which the divided word lines are grouped in pairs to form a pair, the divided word lines corresponding to each divided word line pair of each memory array block, and A front word line commonly provided to a plurality of memory array blocks, a first word line corresponding to each memory array block, and each of which is commonly provided to one and the other of divided word line pairs of the corresponding memory array block. The first and second signal transmission line pairs are provided corresponding to one of the divided word line pairs of each memory array block, and each of them corresponds to the corresponding divided word line and the divided word line. A first word line connected between the input word electrodes and each input electrode corresponding to the divided word line.
A first transmission gate including a first transistor of a first conductivity type and a second transistor of a second conductivity type connected to one and the other of the pair of signal transmission lines, and corresponding to each first transmission gate Connected between the divided word line corresponding to the corresponding first transmission gate and the ground potential line, and its input electrode is connected to the input electrode of the first transistor of the corresponding first transmission gate. A third transistor of the first conductivity type commonly connected, provided corresponding to the other of each divided word line pair of each memory array block, each corresponding to a corresponding divided word line and the divided word line. A second word line connected between the input word electrodes and each input electrode corresponding to the divided word line.
A second transmission gate including a fourth transistor of a first conductivity type and a fifth transistor of a second conductivity type connected to one and the other of the pair of signal transmission lines, and corresponding to each second transmission gate Connected between the divided word line corresponding to the corresponding second transmission gate and the ground potential line, and its input electrode is connected to the input electrode of the fourth transistor of the corresponding second transmission gate. A sixth transistor of the first conductivity type that is commonly connected, one of the plurality of front word lines, and one of the plurality of memory array blocks according to an externally applied address signal. Of the memory array block and the first or second signal transmission line pair of the memory array block are selected. A select circuit and an activation signal for activating the divided word line to the front word line selected by the select circuit, and the first or second signal transmission line of the selected memory array block. A semiconductor memory device comprising: a pair of signal generation circuits that provide a selection signal for turning on the first or second transmission gate and turning off the third or sixth transistor. 2. A divided word line type semiconductor memory device, each comprising a plurality of memory cells arranged in a matrix, divided word lines provided corresponding to each row, and corresponding to each column. A plurality of memory array blocks in which the divided word lines are grouped in pairs to form a pair, the divided word lines corresponding to each divided word line pair of each memory array block, and A pre-word line commonly provided to a plurality of memory array blocks, provided corresponding to each divided word line pair of each memory array block, and given via the pre-word line corresponding to the corresponding divided word line pair An inverter that outputs an inverted signal of the generated signal, corresponding to each memory array block and provided in common to one and the other of the divided word line pairs of the corresponding memory array block. First and second signal transmission lines, which are provided corresponding to one of the divided word line pairs of each memory array block, each corresponding divided word line and a first signal corresponding to the divided word line. Connected between the transmission lines,
A first transistor of a first conductivity type, one input electrode of which is connected to a front word line corresponding to the divided word line, and the other input electrode of which receives the output of the inverter corresponding to the divided word line; Second of second conductivity type
A first transmission gate including a transistor, the first transmission gate is provided corresponding to each first transmission gate, and is connected between a divided word line corresponding to the corresponding first transmission gate and a ground potential line, and its input A third transistor of the first conductivity type, whose electrode is commonly connected to the input electrode of the first transistor of the corresponding first transmission gate, is provided corresponding to the other of each pair of divided word lines of each memory array block. And each connected between the corresponding divided word line and the second signal transmission line corresponding to the divided word line,
A fourth transistor of a first conductivity type, one input electrode of which is connected to a front word line corresponding to the divided word line, and the other input electrode of which receives an output of the inverter corresponding to the divided word line; Fifth of the second conductive type
A second transmission gate including a transistor, the second transmission gate is provided corresponding to each second transmission gate, and is connected between the divided word line corresponding to the corresponding second transmission gate and the ground potential line, and its input A sixth transistor of the first conductivity type whose electrode is commonly connected to the input electrode of the fourth transistor of the corresponding second transmission gate, among the plurality of pre-word lines according to an externally applied address signal A preselection word line, a selection circuit for selecting any one of the plurality of memory array blocks, and a first or second signal transmission line of the memory array block, and The first and second transmission gates are connected to the front word line selected by the selection circuit. To conduct,
Further, the selection signal for turning off the third or sixth transistor is given, and the divided word line is activated by the first or second signal transmission line of the selected memory array block. A semiconductor memory device comprising a signal generation circuit for providing an activation signal.