JPH0817038B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device including a sense circuit using a MOS transistor.

[Technical background of the invention and its problems]

In recent years, high integration of integrated circuits such as MOS semiconductor memory and miniaturization of elements have been rapidly advanced.

In a MOS type semiconductor memory, a sense circuit that uses a pair of MOS transistors to detect a minute potential difference by utilizing the difference in conductance is often used, for example, in an address buffer.

FIG. 4 shows the basic configuration of such a sense circuit. First
The MOS transistor Q ₁ and the second MOS transistor Q ₂ of
The sources are commonly connected and the drains and gates are cross-connected to each other. The difference in the potentials at the gates, that is, the nodes N ₁ and N ₂ is calculated by using the difference in conductance between the MOS transistors Q ₁ and Q _2. It is designed to detect.

FIG. 5 shows a layout example of such a sense circuit on a semiconductor substrate. 51 and 52 are MOS transistors Q ₁ and Q, respectively
_{The second} gate electrode is usually formed of a polycrystalline silicon film. 53 and 54 each of the MOS transistors Q _1, the drain to become n ⁺ -type layer of Q _2, 55 is an n ⁺ -type as a common source. n ⁺ type
53, 54 and 55 are usually formed in a self-aligned manner by using ion implantation using the gate electrodes 51 and 52 as a mask.

By the way, at present, MOS semiconductor memory has a gate length of 2μ.
Although the miniaturization is progressing to about m, it is about to be reduced to about 1 μm in the near future. When the gate length is shortened in this way, hot carriers are generated due to the high electric field in the vicinity of the drain, and these are injected into the gate insulating film, causing variation in the characteristics of the MOS transistor. This is called the so-called hot carrier effect, and has been found to be a serious problem in the reliability of MOS integrated circuits. One effective method for solving this problem is to adopt an LDD structure or a GDD structure in which a low impurity concentration layer is provided on the channel region side of the source and drain regions of a MOS transistor.

FIG. 6 shows an LDD structure MOS transistor. 61 is p-type
63 is a Si substrate, 63 is a gate electrode made of a polycrystalline silicon film formed on the substrate via a gate oxide film 62, and 67 and 68 are n ⁺ type layers serving as a source and a drain,
These are formed by performing ion implantation in a state (not shown) in which the self-aligned insulating film 64 is selectively formed on the side wall of the gate electrode 63 by leaving the side wall by reactive ion etching (RIE). At the ends of the channel regions of the n ⁺ type layers 67 and 68, ion implantation is performed using the gate electrode 63 as a mask to form n ⁻ type layers 65 and 66 having a low impurity concentration.

When the sense circuit as shown in FIGS. 4 and 5 is constructed by using the MOS transistor having the LDD structure or the GDD structure, if the gate length of the MOS transistor becomes shorter than the current one, Such problems will become more serious. As described above, the source and drain regions are formed by ion implantation using the gate electrode as a mask. In order to prevent the channeling phenomenon on the substrate, the ion implantation is performed at a predetermined angle (7) with respect to the substrate surface. °) Tilt is done. This is shown in FIG. 67 is the ion implantation direction. When the source and drain n ⁻ type layers 65 and 66 are formed by such ion implantation, an offset of a distance d as shown in the figure is provided between the n ⁻ type layer 65 and the gate electrode 63 on the side shaded by the gate electrode 63. Occurs. Impurities diffuse in the thermal process after the offset occurs, but the impurity distribution is unavoidably asymmetric between the source and the drain. As a result, the parasitic resistance becomes larger on the side where the offset occurs than in the ideal case shown in FIG. As is well known, a MOS transistor has a small transconductance when the source parasitic resistance is large. That is, in the structure as shown in FIG. 7, the source and drain are not symmetrical, and the characteristics differ when the offset side is used as the source and the drain. Therefore, when the sense circuit shown in FIG. 4 is constructed in the conventional layout as shown in FIG. 5, a characteristic imbalance occurs between the paired MOS transistors Q ₁ and Q ₂ . As a result, the sense sensitivity to the potential difference is greatly deteriorated. This deterioration in sense sensitivity becomes greater as the element becomes finer.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device having a sense circuit that solves the above problems.

[Outline of Invention]

The gist of the present invention is to pay attention to the gate bias dependence of the asymmetry of the transistor drain current, and to operate at the optimum operating voltage.

When the first and second MOS transistors forming the sense circuit are affected by the inclination of the implantation direction in the ion implantation process for forming the source and drain, the source and drain parasitic resistances become unbalanced, resulting in the drain current. The values show different values depending on the direction of the current, and FIG. 2 shows the gate bias dependence of the degree of the imbalance.

According to this measurement result and the two-dimensional simulation result, the unbalance has a very large degree of gate bias dependency, and when the sense amplifier is operated in the B area, the unbalance is large and the area of the gate bias is lower. Then, it turns out that the degree of imbalance is quite low.

Here, the B region is V _GS V _T + 0.4V (V _T : threshold value of MOS transistor) and the A region is V _GS <V _T + 0.4V.

By performing the sense amplifier operation in the area A, the sense circuit is prevented from deteriorating the sense sensitivity due to imbalance.

FIG. 3 shows an example of actual measurement of the sense sensitivity when operated in the regions A and B respectively. Sense sensitivity is improved 4 to 5 times. Such an effect is particularly large when the gate length is 1 μm or less.

Example of Invention

Examples of the present invention will be shown below. In this embodiment, a transistor is inserted between the gate terminal of each of the transistors Q ₁ and Q ₂ forming the sense amplifier circuit, and the drain terminal of the opposite transistor commonly connected to this gate terminal and the capacitance C _B. It has been configured. By inserting in this position, the transistor will change from capacitance C _B to transistor Q ₁ , Q
_{It functions} as a barrier transistor that acts as a barrier to the flow of current into the gate and drain terminals of ₂ .

FIG. 1 shows an embodiment in which a barrier transistor is introduced in the sense amplifier circuit. Figure 1 in a transistor having a gate terminal connected to the lower bit line potentials of the drain terminal potential is high bit lines of the transistors Q _1, Q ₂ are opposed to connect, after lowered simultaneously phi _S and sense start The loci of the drain voltage V _DS and the gate voltage V _GS are shown over time. The point to be noted in FIG. 1 is how high V _GS (peak) rises after φ _S is lowered.

Drain and capacitance C _B of Q ₁ and Q ₂ that form the sense amplifier
Since a barrier transistor is introduced between and, the common source φ _S is lowered, and when starting the sensing operation, the gate of one transistor of Q ₁ and Q ₂ and the drain of the transistor opposite to this transistor Since the potential and the gate potential of the opposing transistor follow φ _S well enough, as shown in the figure, when there is no barrier, and when there is a barrier compared to ○, ● indicates the peak of V _GS is less than 1V. And can be operated in the low V _GS region. Since the conductance of a MOS transistor is finite, if Φ _S is pulled down at a certain speed, there will be a difference between the drain and Φ _S.
In the example in which the barrier transistor is not provided in FIG. 1, since the charge flows directly from the bit line capacitance CB to the drain portion of the sense amplifier, a large amount of the charge cannot be discharged, and a peak of V GS = 2V is generated. On the other hand, when a barrier transistor is provided, the inflow of charges is limited by this barrier transistor, and the drain voltage is suppressed to a low value, which is about 1 V at peak. Thus, the drain potential follows Φ _S well.

As a result, Q ₁ and Q ₂ could be operated in the region of V _GS <V _T + 0.4V. Then, in this region (corresponding to the region A in FIG. 2), the transistors Q ₁ and Q ₂ of the sense amplifier are
As shown in FIG. 3, the sense amplifier is 4 to 5 times larger than the case where it is operated in the vicinity of the V _GS peak (corresponding to the region B in FIG. 2) indicated by the circle in FIG. It was possible to improve the sense sensitivity of.

The reason why the sensitivity can be improved in this way is considered as follows. The introduction of the barrier transistor suppresses the current flowing into the transistors Q ₁ and Q ₂ . The potential drops of Q ₁ and Q _{2 along with} the different source-side parasitic resistances are both reduced, and the difference between them is reduced.

By reducing the difference in the amount of potential drop in this way, the degree of imbalance between the transistors Q ₁ and Q ₂ is also reduced, and the sense sensitivity can be improved 4 to 5 times.

[Brief description of drawings]

1, 2, and 3 are characteristic diagrams for explaining the present invention, FIG. 4 is a diagram showing a basic configuration of a sense circuit using MOS transistors, and FIG. 5 is a pattern of a conventional sense circuit. Layout diagram, FIG. 6 is a diagram showing the LDD structure of the MOS transistor, and FIG. 7 is a diagram for explaining the influence of the inclination in the ion implantation direction on the transistor characteristics.

Claims (3)

[Claims] 1. A source / drain region having an LDD structure,
Moreover, at least two first MOS type transistors exhibiting asymmetry in the drain current value are used, and the magnitude of the voltage applied to the gate electrodes of these two transistors is determined by the magnitude of the drain current flowing through these two transistors. A semiconductor device comprising a sense circuit for detecting by means of: a drain part of at least these two transistors;
A semiconductor device, which is connected to different nodes via S-type transistors. 2. By the inserted MOS transistor,
A voltage applied between the gate and the source of the MOS transistor of the sense circuit is limited by limiting or blocking the electric charge flowing into the drain portion of the MOS transistor of the sense circuit from the wiring. 2. A semiconductor device according to claim 1. 3. The voltage limit value is larger than the threshold value of the MOS transistor of the sense circuit, and the source / drain potential of the MOS type transistor is set to 1 V or less. The semiconductor device described.