JPH0817241B2 - Thin wire field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is characterized by having two or more operating layers each having a common ohmic electrode and a common gate electrode and having a narrow operating width. The present invention relates to a field effect transistor called a transistor, that is, a thin wire, a quantum wire, a one-dimensional wire, a pseudo one-dimensional wire field effect transistor, or the like.

(Prior art) In recent years, Molecular Beam Epitaxy
y; MBE) and Atomic Layer Epitaxy;
ALE) and other epitaxial growth techniques, as well as controlling the film thickness on an atomic layer basis, resulting in interface disturbances of 1 or 2
It is possible to fabricate a high-quality heterostructure in which the atomic layer is suppressed. Further, it has become possible to form a high mobility two-dimensional electron gas system on a hetero interface by selectively adding impurities. On the other hand, due to the demand for integration and speeding up of semiconductor devices, miniaturization of devices has been called for, and the processing technology for them has been greatly developed. Already 1 / 4μ at mass production level
M-class gate processing is being performed, and at the research level, fine processing below 0.1 μm is possible.

High-speed device elements have been manufactured by the above crystal growth technology and microfabrication technology, and their element characteristics have been improved. In particular, a two-dimensional electron gas field effect transistor having a selective doping structure as a two-dimensional device element has already been widely put into practical use due to its dramatic high-speed characteristics and noise characteristics. With the above technique, it is possible to form an electron system of a lower dimension. When making a fine wire with a diameter of about de Broglie's wavelength, high mobility may be expected,
Research and elucidation of the conduction phenomenon of the one-dimensional system and further application to devices have been attempted.

Several structures have been proposed as semiconductor devices to which one-dimensional quantum wires are applied. For example, YC Chang et al. Applied Physics Letters
tters) Vol.47, page 1324 is the one proposed. Figure 3 is shown as Fig.1. As shown in Fig. 3 (a), Al _X1 Ga with different Al composition
_1-X1 As / Al _X2 Ga _1-X2 As GaAs well layer on the side of the superlattice structure,
Re-grown the Al _X3 Ga _1-X3 As barrier layer to form Al _X1 Ga _1-X1 As / GaAs / Al
_X3 Ga _1-X3 As, Al _X2 Ga _1-X2 As / GaAs / Al _X3 Ga _1-X3 As We use the difference in the energy levels of the quantum wells,
One-dimensional thin lines are formed in the buffer layer. FIGS. 3 (b) and 3 (c) show the energy level structure when viewed on the xy plane and the zx plane, respectively. In addition, DB Rensch et al.
Some are shown in Volume 34, page 2232. What is shown in Fig. 4 is the one published as Fig.1. Focused ion beam (FIB) parallel to the source and drain directions on a GaAs substrate without impurities
In this way, a plurality of Si ions are ion-implanted in a thin line shape to form a conductive layer. In addition to this, an example in which a conductive layer is pseudo-one-dimensionalized by applying a gate voltage to a GaAs / AlGaAs selectively doped structure field effect transistor in which a stripe-shaped gate is formed by interference exposure has been announced. . In all of these examples shown above, an improvement in the total conductance was confirmed, and it can be said that the effectiveness of the field effect transistor of the quantum wire structure is shown.

(Problems to be Solved by the Invention) The simplest method for obtaining a thin-line pseudo one-dimensional motion layer is 2
It is to divide the dimensional electron gas layer into several fine parts by mesas. Then, a common gate electrode is formed on each operation layer. In that case, the most serious problem is that the contact portion between the two-dimensional electron gas layer and the metal of the gate electrode is increased in the mesa edge, and the contact area is substantially increased. This causes an increase in gate leak and a reduction in breakdown voltage. In the case of an ordinary selective doping structure two-dimensional electron gas field effect transistor, since there are few such places, there is almost no problem in operation, but for a field effect transistor of the structure considered here, The problem is serious, and when using a GaAs wafer with a normal active layer instead of a two-dimensional electron gas layer structure,
In the case where a two-dimensional electron gas structure using a material system such as GaAs / InAlAs system is used, this gate leak and low breakdown voltage are major defects in the operation of the device.

(Means for Solving Problems) In the thin wire field effect transistor of the present invention, the operating layer is divided into two or more thin wire portions by the mesa, and the ohmic electrode common to each portion of the operating layer is formed, Further, in the field effect transistor characterized in that a gate electrode common to each of the operation layers is formed, an insulating film is formed at each mesa edge portion of the operation layer.

Further, the method of manufacturing a thin-line field effect transistor having the structure of the present invention comprises a step of crystal-growing an operating layer on a semi-insulating semiconductor substrate, and etching the operating layer to form two or more operating portions. A step of forming separately, a step of forming an ohmic electrode at a position sandwiching the operating portion, a step of forming an insulating film on the operating layer, and a step of etching the insulating film in a direction perpendicular to the substrate by directional etching. In addition, the method further includes a step of forming a side wall of an insulating film on the edge portion of each operation layer and a step of forming a common gate electrode for each operation portion.

(Function) The object of the present invention, in a field effect transistor using a two-dimensional electron gas as an operating layer, is that the gate electrode metal and the two-dimensional electron gas layer, which is an active layer, are brought into contact with each other in the mesa edge portion, and various problems occur. To avoid. Although the mesa is the easiest and surest method for forming a channel of a thin wire structure, in the thin wire field effect transistor having a large number of active portions, the gate leakage and the low leakage are as described above. Problems such as pressure resistance will arise. Therefore, an insulating film is formed in the mesa edge portion in order to avoid contact between the two-dimensional electron gas layer and the gate electrode metal in the mesa edge portion. The insulating film prevents the gate from directly contacting the electronic layer, and as a result, the above problems do not occur.

(Example) Hereinafter, the structure of a field effect transistor of the present invention and a method for manufacturing the same will be described in detail with reference to the drawings.

1 (a) and 1 (b) show an embodiment of the field effect transistor of the present invention. Non-doped GaAs layer 2, high-concentration AlGaAs layer 3, high-concentration GaAs layer 4 on semi-insulating GaAs substrate 1.
In the semiconductor substrate which is laminated and grown in this order, the above three layers are etched into fine lines as shown in FIG. 1 (a). Etching here stops midway through the undoped GaAs layer 2. High concentration AlGa of the non-doped GaAs layer 2
A two-dimensional electron gas layer 5 is formed at the interface on the As layer 3 side, but side walls 9 of an insulating film are formed on both side surfaces thereof. Although the gate electrode 8 is formed in the direction perpendicular to the thin line direction with respect to the thin line-shaped operation layer, the two-dimensional electron gas layer 5 and the gate electrode 8 have the insulating film 9 interposed therebetween, so that direct contact is avoided. ing. As shown in FIG. 1B, the ohmic electrodes 6 and 7 are formed in parallel with the gate electrode 8 so as to sandwich the gate electrode 8.

Next, a manufacturing method according to the present invention for manufacturing such a field effect transistor will be described. Fig. 2 (a) ~
(E) is the schematic diagram. The non-doped GaAs layer 2 is grown on the semi-insulating GaAs substrate 1 with an appropriate thickness, and then the high-concentration AlGaAs layer 3 such as an AlGaAs layer 3 with a concentration of 3 × 10 ¹⁸ cm ^-2 is provided with an appropriate thickness, for example, 300Å. Then, a high concentration GaAs layer, for example, a GaAs layer 4 having a concentration of 3 × 10 ¹⁸ cm ^-2 is grown to an appropriate thickness, for example, 500Å. Next, mesa etching is performed with the intention of separating the elements, and a step of finely dividing a portion where a gate electrode is to be formed into two or more portions to form a thin linear operating layer is also performed. It should be done at the same time when the mesa is formed. The mesa needs to be formed by etching at least to a depth where the two-dimensional electron gas layer 5 will be formed. With this substrate structure, the depth reaches at least the non-doped GaAs layer 2.
It is necessary to form mesas by etching 800 Å or more. Through this step, the thin line portion 10 of the operating layer is formed. Subsequently, AuGe, Ni, and Au, for example, are stacked and deposited as the source electrode metal 6 and the drain electrode metal 7, and ohmic electrodes 6 and 7 are formed by high temperature alloying. Subsequently, the insulating film 9 is formed on the entire surface of the wafer in order to prevent the edge portion of the two-dimensional electron gas layer 5 exposed at the mesa edge portion of each operation layer from coming into contact with the gate electrode 8 to be formed later.
Are formed by, for example, a chemical deposition method. Here, an oxide film is used as the insulating film, and its thickness is set to, for example, 1000Å. Following the reactive ion etching using a gas for example, CF ₄ or the like in a direction perpendicular to the semiconductor substrate (Reactive Ion Eching; RI
Directional gas etching 11 such as E) is performed to completely remove the insulating film 9 on each operating layer. By this step, the sidewall 9 of the oxide film is formed on the side surface of each operation layer.
At this time, the side wall of the insulating film is prevented from exposing the edge of the two-dimensional electron gas layer. That is, it is necessary to set the thickness of the insulating film to a value according to the substrate structure. Then ohmic electrode 6,
The gate electrode 8 is formed between 7 and 7. First, a resist layer in which the gate electrode is patterned is formed on the substrate, and the exposed high-concentration GaAs layer 4 surface is treated, for example, with a mixed solution of ammonia and hydrogen peroxide. Using the as an etchant, recess etching is performed. By this recess etching, the high-concentration GaAs layer 4 corresponding to the cap layer is completely etched to expose the surface of the high-concentration AlGaAs layer 3, and further etching of this layer is performed to adjust the amount of current flowing between ohmic contacts. When the amount of current is adjusted to a desired value, the gate metal such as Ti / Pt / Au or TiAl is evaporated and lifted off to form the gate electrode 8. This completes the manufacturing process of the semiconductor device of the present invention.

Although the embodiments of the present invention have been described using specific materials and specific values, this is for easy understanding,
For example, it is not always necessary to use an oxide film as the insulating film, and the essential effect of the invention does not change even if it is an insulator, such as a nitride film. The same applies to the materials forming the ohmic metal and the gate metal.
Further, the two semiconductor layers forming the two-dimensional electron gas are not necessarily the undoped GaAs layer and the doped AlGaAs layer, and may be a combination of the undoped InGaAs layer and the doped InAlAs layer, for example. . However, in this case, the semiconductor substrate to be epitaxially grown also has a lattice matching material, and in this case, it is necessary to use an InP substrate or the like, and the ohmic electrode formation conditions such as the ohmic alloy temperature also need to be changed. That is, the substrate structure is not limited to a particular one.

(Effects of the Invention) In the present invention, the presence of the insulating film prevents the gate metal and the operating layer from directly contacting each other in the mesa edge, and therefore, there is no fear of gate leakage. Further, improvement of breakdown voltage can be expected. According to the present invention, by utilizing these advantages, it is possible to obtain a field effect transistor having a fine line structure, which is expected to have good pinch-off characteristics, high transconductance, and small noise.
Also, reactive ion etching (RI)
It is easy to form the side wall of the insulating film by utilizing the directional etching such as E), and it is possible to greatly simplify the process condition setting.

[Brief description of drawings]

1 (a) and 1 (b) are views showing the structure of a field effect transistor according to the present invention, and FIGS. 2 (a) to 2 (e) are views showing a method for manufacturing a field effect transistor according to the present invention. Process drawings, FIGS. 3A to 3C, and FIG. 4 are views for explaining a conventional quantum wire semiconductor device. 1 ... Semi-insulating GaAs substrate 2 ... Non-doped GaAs layer 3 ... High-concentration AlGaAs layer 4 ... High-concentration GaAs layer 5 ... Two-dimensional electron gas 6 ... Source electrode 7 ... Drain electrode 8 ... Gate electrode 9 ... Insulating film 10 ... Thin line part 11 ... Directional etching gas

Claims (2)

[Claims] 1. A thin wire field effect transistor, characterized in that an operating layer is divided by a mesa into two or more thin wire portions, and an ohmic electrode and a gate electrode which are common to the operating layers between the thin wires are formed. 2. The thin wire field effect transistor according to claim 1, wherein an insulating film is formed on a side wall portion of each mesa of the operating layer. 2. A step of crystal-growing an operating layer on a semi-insulating semiconductor substrate, a step of dividing the operating portion into two or more fine line portions by etching the operating layer, and dividing the operating portion. Direction of the ohmic electrode at a position sandwiched in the direction perpendicular to the direction, a step of forming an insulating film on the operating layer, and the insulating film is etched in the direction perpendicular to the substrate by directional etching to form the edge of the operating layer. A method of manufacturing a thin-line field effect transistor, comprising: a step of forming a side wall of an insulating film in a portion and a step of forming a common gate electrode for each operating portion.