JPH0817331B2 - Signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a signal processing method in a channel, and more particularly, to digitize an analog signal representing coded binary data transmitted through the channel. The present invention relates to processing of a sample value corresponding to an equalized one in a signal processing channel.

B. Prior Art and its Problems The trend toward higher densities and higher data rates has led to an excessive demand for signal detection processing in magnetic recording channels. Peak detection channels, which process one bit at a time for analog signals, are widely used in current magnetic recording and storage devices. With increasing density and data rate, the one-bit detection window in a typical peak detection channel becomes very small, limiting detection reliability. An alternative, partial response maximum likelihood (PRML) channel, is discussed in the paper below.

(1) Kabal et al, “Partial-Response Signaling”, I
EEE Trans.on Comm., Vol.COM-23, No.9, September 1975. (2) Forney, “Maximum-Likelihood Sequence Estima
tion of Digital Sequences in the Presence of Inter
symbol Interference ", IEEE Trans.on Info.Theory, vo
l.IT-18, No.3, May 1972. (3) Kobayashi, “Application of Probabilistic Dec
oding to Digital Magnetic Recording Systems ", IBM
J. Res. Develop., January 1971. (4) Nishimura et al, “A Design Method for Optimu
m Equalization in Magnetic Recording with Partial
Response Channel Coding ", IEEE Trans.on Mag., Vol.MA
G-19, No. 5, September 1983. (5) Forney, “The Viterbi Algorithm”, Proc.of the
IEEE, vol.61, No.3,3 / 73. In PRML channel characterized by polynomial (1-D) (1 + D), the frequency response requires sharp cutoff, and the frequency spectrum is the channel response in magnetic recording. Notch filter is needed because it is very different from that of.

“A Class of Partial Response Systems for Increa
sing Storage Density in Magnetic Recording ", HKTh
apar and AMPatel, IEEE Trans.Magnetics, Vol.MAG-2
3, No. 5, September 1987, pp. 3666-3668, describes the extended partial response maximum likelihood (EPRML) channel characterized by the polynomial (1-D) (1 + D) ^2. ing. In this signaling method, the signal spectrum resembles a typical magnetic recording channel transfer function. Desirably, it eliminates the need for Notch filters. However, in this channel, Viterbi type calculation for maximum likelihood detection becomes a limiting factor in terms of decoding speed and cost. In addition, P.RML and EPRML are very sensitive to mis-equalization or changes in signal shape due to component tolerances and non-linearities in the magnetic recording process caused by pulse asymmetries and congestion of write transitions to the media. Is.

Therefore, (1) the run length of the peak detection channel to control the congestion of write transitions on the media.
Uses limited (RLL) code, (2) uses sequence detection algorithms to avoid the complexity of Viterbi type computation, (3) removes the strict requirement for signal equalization, and tolerates non-linearity of magnetic recording process Therefore, there is a need for a signal processing method in which the detection process is tolerant of fluctuations in the signal waveform.

C. Means for Solving Problems According to the present invention, in order to meet the above requirements, (1, 7)
A method is provided for processing a sample value of an analog signal corresponding to binary data encoded with an RLL code such as a code in a signal processing channel. The coded analog input signal is converted by an analog-to-digital converter (ADC) into a sequence of digital sample values during successive clock times. The signal is equalized to accommodate a given analog shape, which can be done with a digital equalizer after the ADC or with an analog filter before the ADC. . Alternatively, both may be combined as shown later. The digital sample values are then decoded into coded binary data using a sequence detection algorithm. When the signal shape anomaly cannot be compensated for by the equalizer, it is preferably programmable so that the decoder can adjust the thresholds in the positive and negative phases of the decoder. If desired, the decoder can continue to be adaptive to accommodate variations in signal shape. The sample value processing method according to the present invention preferably comprises the following elements.

(1) When using channels, use a signaling method that processes (1,7) coded analog signals without the need for notch filters.

(2) Convert the analog input signal into a sequence of digital sample values corresponding to a given uniformized analog shape.

(3) Achieving near-optimal puff performance while avoiding Viterbi type computations is achieved by a state-dependent Luck-Ahed technique focusing on minimum distance and subsequent maximum likelihood error events.

(4) Use a programmable decoder that can adapt to variations in signal shape.

(5) During the rucksack-ahead processing, flag a decision that was previously suspected of being an error.

D. Example As shown in FIG. 1, the apparatus embodying the present invention comprises a signal processing channel. The signal processing channel includes a line 10 through which an analog read signal is supplied from a transducer. A transducer is a magnetic or optical read head, for example in a digital storage device. This read signal corresponds to the recorded (1,7) data sequence. Here, the (1,7) data sequence is a binary data sequence coded by using the (1,7) RLL code at the time of writing. The read signal passes through a preamplifier 11 having an AGC and a low bandpass filter 12. The output of the filter 12 is fed to the phase locked clock 13. The Phase Locks Clock 13 consists of a Phase Locked Loop (PLL) timing recovery circuit that includes a variable frequency oscillator (VFO). The parts up to this point of the apparatus may be the same as those used in a conventional peak detection channel using the (1,7) code.
The channel is preferably of the type called the EPRML channel characterized by the polynomial (1-D) (1 + D) ² . In EPRML signaling, the signal spectrum resembles a typical magnetic recording channel transfer function, which is desirable,
The notch filter required by a normal PRML channel, which is characterized by a polynomial of (1-D)) (1 + D), is unnecessary.

More specifically, the filter 12 and the equalizer 22 have sampled values of 0, 2, 4,
It operates to filter the read signal so that the pulse is given by 2,0. FIG. 2A shows a magnitude 2 write transition between the (+1) and (-1) levels of saturation magnetization. Corresponding scaling
The read response normalized by the factor is shown in Figure 2B.

In the environment described here, when (1,7) RLL code is used, the concentration of write transitions on the media is reduced to PRML or EP.
It is reduced to 2/3 of that when using the RML channel. The (1,7) chord acts as a trellis chord that gives the built-in redundancy a 2/3 rate. It is very tolerant of non-linearities in high density, high data rate magnetic recording channels.

Briefly, according to the present invention, a coded analog read signal output is provided from filter 12 to delay means 20. The delay means 20 is an Engineered Components Co
Product name PECL sold by mpany of San Luis Obispo
DL-28-01 Programmable Logic Delay Line type digital chip may be used. This allows the delay to be selectively adjusted in tenths of nanoseconds, depending on the clock speed. The delay means 20 provides a delay alignment between the analog signal and the clock signal input to the analog-to-digital converter (ADC) 21. The ADC 21 converts the analog input signal into digital sample values during successive clocks. These digital sample values may in some cases be equalized by the equalizer 22 (though depending on the characteristics of the filter 12). The digital sample value is then passed to the decoder 23. Positive and negative threshold constants are provided to the decoder 23 via lines 24 and 25, respectively. The decoder 23 decodes the digitized sample value after passing through the equalizer.
Applying the algorithm, under the control of clock 13, at successive clocks, the coded binary data is output on line 26 and, if appropriate, the pointer flag on line 27.

FIG. 3 shows the write and read waveforms and the sequence of associated data and sample values under the clock by clock 13 in a noise free environment. When the pulse shape is as shown in FIG. 2A and FIG. 2B, the sample value is set to a discrete value set {-4, -2, 0, +, according to the implementation of the decoder.
2 or +4}. However, since the actual sample contains anomaly of the signal and additional noise, the sampled value takes various non-integer values near the integer in the discrete value set.

The read clock is derived from the read signal 10 using a conventional peak detect circuit that drives the VFO of clock 13.
As mentioned above, the ADC 21 converts the analog signal to a digitized sample value during successive clocks under the control of the clock 13. Then, the digitized sample values are equalized by the equalizer 22.

Suppose y _i represents the digitized sample value corresponding to the ith clock. Then, as shown in FIG. 4, the current value of y _i is i = i in the current clock cycle.
Shown as y ₀ corresponding to ₀ . The decoder 23 iteratively processes these digitized and equalized sample values, receiving one new sample per clock time and 6-sample values in the track header. Therefore,
The decoder 23 receives y _{i + 6} while processing the previously received sample values and decodes y _i into the i th digit of the recording sequence. Note that the decoding process is state dependent. The state of the decoder 23 in the i-th clock cycle is three digit binary numbers a _i , b _i , c _i.
Is represented by Here, a _i , b _i , and c _i are (third bit) for the last three bit values in the i-th clock cycle.
Represents a binary logic level of write current (as shown in the figure). This gives you 6 possible states: 00
One of 0, 100, 110, 111, 011 and 001 is identified. (States 101 and 010 do not occur with the (1,7) coded data used in the EPRML channel.) Clock 13
In each cycle, the decoder 23 determines one digit of the recording (1,7) sequence and identifies the next decoder state for processing in the next cycle.

Decoding Algorithm Decoder 23 implements an algorithm using the equations shown in FIGS. 6 and 7. In this algorithm, the sample value currently being decoded is represented by y ₀ , which corresponds to clock cycle i = 0. The process is iterative and is driven by the read clock 13.

According to the invention, the decoder 23 is "state-dependent". That is, the current state a ₀ b ₀ c ₀ and the sample values y ₀ , y ₁ ,
Given y ₂ , y ₃ , and y ₄ , the decoder is a noise-free sample value Determine (following y ₀ ) and the next state a ₁ b ₁ c ₁ . Also, the decoder changes this state to the original recording (1,
7) Decode to 1 or 0 (presence or absence of magnetic transition) in the data sequence. The actual decision is based on the test results of the sample values given in the equations of FIGS. 6 and 7 as the decode 23 moves from one state to another. Note that the transition from one state to another is highly structural, and in various states the form of the equation is very simple and similar. States 110, 1 corresponding to the positive phase of the signal
00 and 000 (Fig. 6) are in a mirror image relationship with states 001, 011 and 111 (Fig. 7) corresponding to the negative phase of the signal, respectively. Mirror symmetry is characterized by the changing sign (positive and negative) for all sample values at corresponding locations in FIGS. 6 and 7.

The decoder 23 decisions are driven by the results of three basic checks: (i) baseline check, (ii) peak position check, and (iii) phase check. The results of these checks are expressed in the form of Boolean variables (see Figure 4). That is, A ₁ , A ₂ , B ₁ , and B ₂ for the baseline check, Q ₁ and Q ₂ for the peak position, and the Boolean variable p for the phase check, respectively. Where Q ₁ , Q ₂
Is a more detailed check function expressed by X ₁ , X ₂ , Y ₁ , Y ₂ , Z ₁ , and Z ₂ . Each check is a comparison of a special function of sampled values with a fixed threshold. Each threshold is read back (read
back) is strongly related to the shape of the signal and is represented by the correspondence constant defined by the right hand side of the corresponding test equation. In the test equations below, the threshold constants are sample values 0, 2, 4, 2, 0, ... And 0, −, as shown in FIG. 2B.
It corresponds to the nominal pulse shape with 2, -4, -2, 0.

(I) Baseline check (A ₁ , A ₂ , B ₁ and B ₂ ) Meaning of A ₁ = 1: (y ₀ + y ₁ ) + (y ₁ + y ₂ ) ≦ 4 (1) A ₂ = 1 Meaning: (y ₀ + y ₁ ) + (y ₁ + y ₂ ) ≦ 6 (2) Meaning of B ₁ = 1: (y ₀ + y ₁ ) + (y ₁ + y ₂ ) −y ₃ ≦ 4 (3) B ₂ = 1 means: (y ₀ + y ₁ ) + (y ₁ + y ₂ ) −y ₃ ≦ 6 (4) (ii) Peak position check Q ₁ and Q ₂ Is defined as follows.

The peak position check represented by the Boolean variables Q ₁ and Q ₂ is expressed as follows.

Here, Q ₁ = X ₁ + Y ₁ Z ₁ (8) Q ₂ = X ₂ + Y ₂ Z ₂ (9), and the meaning of X ₁ = 1: (y ₀ + y ₁ ) − (y ₂ + y ₃ ). ≦ -2 (10) meaning of _{X 2 = 1: (y 0} + y 1) - (y 2 + y 3) ≦ 0 (11) the meaning of _{Y 1 = 1: (y 0} + y 1) - (y 2 + y 3 ) ≦ 0 (12) Meaning of Y ₂ = 1: (y ₀ + y ₁ ) − (y ₂ + y ₃ ) ≦ 2 (13) Meaning of Z ₁ = 1: (y ₀ + y ₁ ) − (y ₂ + y ₃ ) + (Y ₃ + y ₄ ) ≦
-4 (14) Meaning of Z ₂ = 1: (y ₀ + y ₁ )-(y ₂ + y ₃ ) + (y ₃ + y ₄ ) ≦
-2 (15).

(Iii) Phase check (p) Meaning of p = 1: (y ₁ + y ₂ ) + (y ₂ + y ₃ ) ≦ −7 (16) The above test corresponds to the positive phase state of the signal c ₀ = 0.
This corresponds to the equation of FIG. 6 in the case of. For c ₀ = 1 the equation of FIG. 7 corresponding to the situation in the negative phase is subjected to the same test with different signs for all sample values.

The hardware of the decoder 23 is shown in FIG.
Registers 30-40 contain sample values y ₀ -y _{4 as shown.}
Holds each intermediate function value of. In each cycle, the contents of each of the registers 30-40 are five adder circuits 41-4.
As appropriate function values are generated through 4, 44a, move to subsequent registers in the direction of the arrow. The sign change blocks 45-49 change the sign of the input binary number (positive or negative) whenever the c ₀ bit in the status register 50 has the value "1". The outputs of the sign change blocks 45 to 49 are sent to the comparators 51 to 61, respectively. The outputs of the comparators 51-61 are the variables A ₁ ,
Formulas (1) to (4) for A ₂ , B ₁ , and B ₂ , variables X ₁ , X ₂ ,
It corresponds to the outputs of equations (5) to (15) for Y ₁ , Y ₂ , Z ₁ , and Z ₂ and equation (16) for the variable p, respectively.
The outputs of the comparators 51-61 are "1" or "0", which together with the state values a ₀ , b ₀ , c ₀ coming from the state register 50
Logic that implements the logic shown in the figure.
It is supplied to the block 62. The logic block 62 generates the data d ₀ corresponding to the state a ₀ b ₀ c ₀ and the erasure pointer according to the logic of section 1 in FIG. In addition, the block 62 follows the state 2 a ₁ b ₁ according to the logic of section 2 in FIG.
Generate c ₁ . This state value is provided to the state register 50 and becomes the current state value for subsequent clock cycles. The block 62 follows the “expected sample value” (that is, the maximum likelihood sample value) according to the logic of section 3 in FIG. Also decide.

The programmable or adaptive decoding decoder 23 structure provides considerable flexibility and adaptability to signal and noise environments. The shape of the analog read signal changes with the radius of the magnetic disk surface. Also,
The signal shape is also affected by the head geometry, which often manifests itself in the inevitable asymmetry of the positive and negative readback pulses. For example, such a signal shape abnormality is a filter.
It is not always possible to completely compensate with 12 or equalizer 22. At least attempting full compensation is not easy and uneconomical.

The decoder 23 provides means for compensating for such mis-equalization. For this purpose, the read response for positive and negative magnetic transitions is sampled at 0, α ₁ ,
Characterized by β ₁ , γ ₁ , 0 and 0, -α ₁ , -β ₂ , -γ ₂ , respectively (see Figure 2B). In other words,
[alpha] ₁ , [beta] ₁ , [gamma] ₁ ,-[alpha] ₂ ,-[beta] ₂ ,-[gamma] ₂ define the signal shape to allow non-linearity and small variations near the nominal sample value. Here, the nominal sample values are, as described above, α ₁ = α ₂ = 2, β ₁ = β ₂ = 4, and γ ₁ = γ ₂ =
It is 2.

In FIG. 9, the programmable values of the threshold constants for each test are shown by the general parameters α ₁ , β ₁ , γ ₁ , -α ₂ ,
It is expressed as a function of the signal shape given by −β ₂ and −γ ₂ . If the positive and negative readback signal shapes are asymmetric, then each of the threshold constants (FIGS. 6 and 7) for the corresponding test of the two phases of the decoder will not necessarily be equal.

In FIG. 9, the positive phase threshold constant is shown with a plus sign, and the negative phase threshold constant is shown with a negative sign. For example, the test corresponding to the Boolean variable A ₁ uses the constant K (A ₁ +) for the positive phase state (c ₀ = 0 state) and the constant K for the negative phase state (c ₀ = 1 state). (A ₁ −) is used.

Therefore, in FIG. 4, the comparator circuit corresponding to the Boolean variable A is supplied with two different values as constant operands, namely K (A ₁ +) and K (A ₁ −). Then, as shown in FIG. 5, the output has a condition of c ₀ =
It is selectively gated depending on whether 0 or c ₀ = 1. (In that case, the sign change block 45 is unnecessary. Eleven Boolean variables (ie, A ₁ , A ₂ , B ₁ , B ₂ ,
The comparison circuit for each of X ₁ , X ₂ , Y ₁ , Y ₂ , Z ₁ , Z ₂ , and p) is modified to accept two different values as constant operands, and the output is conditional c _0. = 0, c ₀ =
It is selectively gated depending on whether it is 1.

According to an important feature of the present invention, signal shape anomalies can be 12 or more.
When not compensable by a filter or equalizer such as 22, programmable decoder 23 provides a simple means of compensating for mis-equalization by adjusting the thresholds in the two phases of the decoder. Due to this flexibility, the decoder 23 exhibits almost optimal operating performance even if the readback signal is not ideally shaped. This is especially important in the disk file. This is because the programmability of the decoder can be used to change the threshold constant depending on the track or track band to obtain near-optimal puff performance for all tracks.

According to another feature of the invention, a programmable decoder
23 can also be used with a read signal that is partially equalized in the recording channel value, or even a read signal that is not at all equalized.

The programmability of the decoder 23 also makes it possible to continuously and adaptively adjust digital parameters in the decoder. More specifically, at the output of the decoder 23, the estimated sample value can be monitored in comparison with the received sample value. When a predetermined number of similar sample values are taken and averaged, the signal shape can be characterized in the form of parameters α ₁ , β ₁ , γ ₁ , -α ₂ , -β ₂ , and -γ ₂ . This information can be used to obtain the corresponding threshold constant (FIG. 9) and adapt the decoder to variations in signal shape.

Also, according to this improved decoder configuration, the threshold of the decoder can be easily checked through a large amount of tests, so adjust the threshold according to empirical results to cover a particular anomaly of the signal. Is also possible.

In particular, the preselected first threshold set corresponding to the baseline checks A ₁ , A ₂ , B ₁ , B ₂ is the loss bit and the excess bit due to abnormalities in the input analog signal associated with media defects. A _second preselected threshold set, used to control the bit error and corresponding to the peak position checks X ₁ , X ₂ , Y ₁ , Y ₂ , Z ₁ , Z ₂ , is A third preselected threshold set, used to control the peak shift error due to signal anomalies, and which corresponds to the phase check p, controls the propagation of the error in decoding the signal, and Used to generate a pointer to the error. Traditional Vi
The terbi decoder does not provide such flexibility.

It will now be appreciated that the improved method and apparatus comprises a decoder that implements a state-dependent look-ahead using a sequence detection algorithm. A suitable function of the equalized digital sample values is precomputed for a given number of bits currently prior to the bit,
The algorithm compares against various thresholds and then the digitized sample values are decoded into (1,7) coded binary data. The decoder is programmable and may be continuously adaptive to adjust digital parameters within the decoder. Finally, the benefits of partial response signaling are obtained without the need for Notch filters,
And the advantage of Viterbi decoding is the usual trellis
Obtained without the complexity of any type of Viterbi decoder.

E. Effect According to the present invention, it becomes possible to process the sampled value of the input analog signal coded by the RLL code in the EPRML channel without requiring complicated calculation.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a coded digital signal processing channel for implementing the present invention, FIG. 2A is an explanatory diagram of an example of a write transition, and FIG. 2B corresponds to the write transition of FIG. 2A. FIG. 3 is an explanatory view of a read response normalized by a scaling factor, FIG. 3 is an explanatory view of write / read waveforms and read sample values of (1, 7) coded data, and FIG. 4 is the present invention. FIG. 5 is a block diagram of an example of a decoder that implements the method of FIG.
FIG. 6 is an explanatory view of an example of a method of modifying the decoder in the figure into a programmable decoder, FIG. 6 is an explanatory view of an example of a decoding scheme for a positive phase in the decoder, and FIG. 7 is a decoding scheme for the same negative phase. FIG. 8 is an explanatory diagram of an example of a logical operation in the decoder, and FIG. 9 is an explanatory diagram of an example of a programming method in the decoder.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 25/49 A 9199-5K 25/497 9199-5K (56) Reference JP-A-58-137111 (JP, A) JP 58-155511 (JP, A) JP 58-9205 (JP, A) JP 63-7051 (JP, B2) JP 63-4270 (JP, B2) JP KO 63-4269 (JP, B2) JP-B 3-63859 (JP, B2) IEEE TRANSACTIONS ON MAGNETICS Vol. 24, No. 6, November 1988, NE W YORK, USpages 2539-2541 R.S. C. SCHNEIDER Sequence (viterbiquivalent nt decoding) 'IBM TECHNICAL DISC LOSSURE BULLETIN Vol. 30, No. 9, February 1988, ARMON NY, US pages 65-67 IBM CORP. 'Sequence decoder' IBM TECHNICAL DISC ROSURE BULLETIN Vol. 15, No. 6, November 1972, ARMMON NY, US pages 1924-1926 C.I. M. MELAS 'three level to two level digital code conversion with noi seimmunity'

Claims (1)

[Claims] 1. A method for processing digital values of coded binary data in a signal processing channel, wherein a state-dependent sequence of transitions from a current state to a subsequent state is repeated by successive clock cycles. A detection algorithm is used to pre-calculate a function formula that complies with the rules for decoding digital sample values for a given number of bits prior to the current bit, and the preselected one of the above function formulas is compared with the associated threshold and the comparison result A signal processing characterized in that a binary output is generated for each and the output is used in association with a state value corresponding to the current state to determine a state value for a subsequent state, each threshold being programmable. Method.