JPH0817413B2 - Communication control circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 5 and 6) Problems to be solved by the invention Means for solving problems (Fig. 1) Action Embodiment (a) Description of one embodiment (FIGS. 2, 3, and 4) (b) Description of another embodiment [Outline of the invention] [Outline] Elapse of final data guarantee time after completion of transmission of transmission data rear
In the communication control circuit for turning off the RS signal, by providing a dummy data generating circuit and a guarantee circuit for performing timing control for turning off the RS signal, it is possible to omit the need for guarantee control of final data by a program.

[Industrial applications]

The present invention relates to a communication control circuit for transmitting data by using RS (transmission request) -CS (transmission possible) control in data communication, and in particular, communication in which timing control of RS signal off to a line termination device can be executed in the circuit. Regarding the control circuit.

In order to perform data communication, it is required that the device efficiently perform data communication control.

[Conventional technology]

In order for the pair of communication devices 1a and 1b shown in FIG. 5 (A) to communicate using the telephone line 1, it is necessary to intervene the line termination devices 2a and 2b including a modem (modulator / demodulator). is there.

Such communication devices 1a and 1b are connected to the line termination devices 2a and 2b,
At the time of transmission, it issues an RS (transmission request) signal, after receiving a CS (transmission possible) signal, it issues an SD (transmission data) signal, while on the other hand, it receives a CD (carrier detect) signal and RD.
It is defined to receive the (received data) signal.

In this transmission control, to perform RS-CS control, the fifth
As shown in the figure (B), when the RS signal is turned on, the CS signal is turned on, data transmission is started, the last data is passed at the end of transmission, dummy data is added, and time T is passed from the last data. _The RS signal is delayed by ₀ and turned off.

That is, if the RS signal is turned off before the final data reaches the other end, the line terminating device stops operating, and the data cannot be guaranteed. Therefore, the final data reliably reaches the line terminating device. That guarantees the time and turns off the RS signal.

Therefore, conventionally, as shown in FIG. 6, the communication device 1a (1b)
Inside, the CPU 3 is provided with the communication control circuit 4 via the bus BUS, and the communication control circuit 4 is connected to the line terminating device 2a (2b). The transmission side of the communication control circuit 4 is a register for RS signals
It is composed of 40 and the transmission data buffer 41, manages the RS control signal of the register 40 by the program of the CPU 3, and sets the data to be transmitted to the transmission data buffer 41 one after another via the bus BUS, Send data.

Since the program manages the RS control signal set in the register 40, the program passes the last data at the end of transmission to the communication control circuit 4 and then the program monitors the timer or a dummy of a plurality of bytes next to the final data. The RS control signal is turned off by adding data and passing it to the communication control circuit 4.

[Problems to be solved by the invention]

As described above, in the related art, since the program needs to perform the guarantee process of the final data, the pre-process until the next data communication process cannot be performed without being aware of the guarantee process.

That is, even after the final data is transmitted, the process of creating and transmitting dummy data, turning off the RS signal, and confirming the off is imposed on the program, and there is a problem that the load of the program is heavy and the process cannot be moved to the next process early. Was also occurring.

An object of the present invention is to provide a communication control circuit capable of controlling transmission while reducing the load on a program.

[Means for solving problems]

 FIG. 1 is an explanatory view of the principle of the present invention.

In the figure, the same components as those shown in FIG. 6 are designated by the same symbols, and 42 is a guarantee circuit, which turns off the RS signal in response to the RS control signal of the register 40 being turned off. Timing control is provided, and 43 is a dummy data generation circuit, which is used by the guarantee circuit 42 to generate dummy data as a form of guaranteeing the final data.

[Action]

In the present invention, when the guarantee circuit 42 turns off the RS control signal of the register 40 by the program, the guarantee form process of the final data is performed, that is, the dummy data is generated, and thereafter,
The RS signal is turned off.

Therefore, if the program passes the final data and the RS control signal OFF to the circuit 4, it is not necessary to guarantee the final data, and the load is reduced.

〔Example〕

(A) Description of an Embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory view of main parts of FIG.

In the figure, the same components as those shown in FIGS. 1 and 5 are indicated by the same signals, 42a is a guarantee mode register, and the guarantee mode of the final data of RS OFF control is from the CPU3 (program). As shown in FIG. 3, a guarantee bit indicating whether or not the final data is guaranteed and a data (dummy data) to be transmitted next to the final data when guaranteeing the final data are set. Specify the dummy data to specify the sync code or mark pattern, and indicate whether to interrupt the program (CPU3) when the RS signal is turned off. To be done.

Reference numeral 42b is a final data guarantee circuit. When the RS control signal SRS of the register 40 is turned on (“0”) to off (“1”), the final data guarantee processing period date signal GS is set according to the contents of the guarantee mode register 42a. Is "low"("0"), and the guarantee process is performed in accordance with the contents of the guarantee mode register 42a during this period. 42c is an AND gate, and the logical product of the RS control signal SRS and the gate signal GS is calculated. That is, the one that issues the RS signal, 43a is the sync code generator, that sends the sync code according to the selected output of the final data guarantee circuit 42b, and 43b is the mark generator, the final data guarantee circuit 4
The mark is output according to the selective output of 2b.

44a is an OR gate, which takes the logical sum of the outputs of the transmission data buffer 41, the synchronization code generation unit 43a, and the mark generation unit 43b, and 44b is a transfer shift register, which shifts the output of the OR gate 44a at the specified transmission timing. And output as transmission data SD to the line terminating device 2a (2b), 45 is an output register, the RS signal which is the output of the AND gate 42c is set, and the program (CPU3) turns off the RS signal via the bus BUS. Is designed to be read.

 FIG. 4 is a diagram for explaining the operation of the embodiment of the present invention.

The program previously sets the guarantee form contents of FIG. 3 in the guarantee form register 42a. This set only needs to be set first and does not need to be set later, except for changes.

Next, the program passes the R of the input register 40 via the bus BUS.
When the S control signal SRS is turned on (“0”), since the gate signal GS is “1”, the RS signal changes from off “1” to on “0” and is transmitted to the line terminating equipment.

The program is from the line terminating equipment to CS
When the (transmission enabled) signal is detected to be on, transmission is started.

That is, the transmission data is set from the bus BUS in the transmission data buffer 41, and the line terminating device is output as the transmission data SD via the OR gate 44a and the transfer shift register 44b to perform transmission.

When ending the transmission of one message, the program passes the final data to the transmission data buffer 41, and then turns off the RS control signal SRS of the input register 40 via the bus BUS to “1”.

Since the RS control signal SRS of the input register 40 is turned off, the final data guarantee circuit 42b operates based on the preset contents of the guarantee mode register 42a after the final data is transmitted, and at the end of that operation. For line terminator
Turn off the RS signal.

That is, the final data security circuit 42b uses the byte counter,
Comprised of flip-flop and gate, RS control signal SRS
The content of the security mode register 42a is loaded by turning off the switch, and if the security bit is "1", the gate signal GS is set to "low" and the RS signal is kept on to "0" to ensure the security. Select either the sync code or the mark generation circuits 43a, 43b according to
Generating circuit 43 that prohibits the operation of 41 and selects the number of bytes to send 43
A synchronization code or mark is generated from a or 43b and is given to the line terminating device via an OR gate 44a and a transfer shift register 44b. When the byte counter detects that the dummy code has been transmitted for the number of transmission bytes, the final data guarantee process is completed, and the gate signal GS is set to "high"("1"). Therefore, the RS signal from the AND gate 42c is turned off "1" after the final data guarantee process is completed.

The output RS signal of the AND gate 42c is output to the output register 45.
Is set to Therefore, in the final data guarantee circuit 42b, the presence / absence of an interrupt in the guarantee mode register 42a has an interrupt (enabled).
If this is specified, an interrupt will be generated when this RS signal is turned off, but the program will read the RS signal of the output register 45 when the next transmission data is sent, even if no interrupt (disable) is specified. You can confirm that the RS signal is off.

On the other hand, if the security bit of the security mode register 42a is "0", security is not performed and the RS signal is immediately turned off by turning off the RS control signal SRS.

As described above, by presetting the guarantee form of the final data in the RS off control in the guarantee form register 42a, various guarantee form processes can be performed.

(B) Description of Other Embodiments In the above-mentioned embodiments, an interrupt is generated when the RS signal is turned off.
Since the CS signal is also turned off, the interrupt may be raised when the CS signal is turned off. If the guarantee form is fixed in advance, it is not necessary to provide the register 42a connected to the bus BUS.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, the program passes the final data to the communication control circuit, and the RS signal OFF control can be performed without performing the guarantee processing of the final data. As a result, the effect of reducing the equal load can be achieved, and more efficient data communication can be performed.
Further, by implementing the communication control circuit as an LSI, there is an effect that cost increase required for this can be minimized.

[Brief description of drawings]

 FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a structural diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a security mode register of FIG. 2, and FIG. Explanatory drawing, FIG. 5 is explanatory drawing of RS-CS control, and FIG. 6 is explanatory drawing of a prior art. In the figure, 4 ... Communication control circuit, 40 ... Input register, 41 ... Transmission data buffer, 42 ... Security circuit, 43 ... Dummy data generation circuit.

Claims (1)

[Claims] 1. A register (40) in which an RS control signal is set.
And a transmission data buffer (41) in which the data to be transmitted is set, and after the end of the final data guarantee time after the transmission of the transmission data has elapsed.
In a communication control circuit for turning off the RS signal, a dummy data generation circuit (43) and a security circuit for controlling the timing of turning off the RS signal in response to the turning off of the RS control signal of the register (40) (42) is provided, and after the guarantee circuit (42) transmits dummy data from the generation circuit (43) to perform a guarantee form process of final data,
A communication control circuit, characterized in that the RS signal is turned off.