JPH082022B2 - Oversampling type analog digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oversampling type analog-to-digital converter (hereinafter referred to as “oversampling type analog-digital converter”) that realizes high-precision conversion by performing conversion at a frequency extremely higher than the signal frequency. And a compact and highly accurate A / D converter suitable for an integrated circuit.

[Conventional technology]

When converting an analog signal to a digital signal, the conversion frequency (sampling frequency) is generally selected to be twice or more the input signal band, usually a little higher than twice. On the other hand, in the oversampling A / D converter, the number of sampling conversions is compared to the input signal band, and by setting it to a very high frequency, noise (quantization noise) generated when converting an analog signal into a digital signal is generated. ), The in-band component can be reduced, and highly accurate conversion can be performed.

Specifically, the signal power to noise power ratio (hereinafter referred to as S / N), which is a measure of noise characteristics, increases. The dust is due to the following reasons.

Quantum noise generated in the quantizer may be regarded as irregularly occurs, the sampling frequency of the oversampling A / D converter to 0 to F _S When f _S, the noise power is spread. Therefore, if the sampling frequency f _S is very large compared to the band of the input signal, the noise power in the band is very small and the actual sound generated outside the band is generally obtained by installing a filter in the subsequent stage. Can be removed.

Oversampling A / D converters can be classified into the prediction type and the noise shaping type, but the prediction / noise shaping type that combines the two types is SKTewksbury et.a.
l., “Oversampled Linear Predictive and Noise−Shap
ing Coder of Order N> 1 ", IEEE Trans, Circuit and Sy
stems, Vol. CAS-25, pp. 436-447, 1978, which enables further noise reduction.

Fig. 5 shows 1st-order prediction and 1st-order noise shaping A / D
The converter is shown. Input signal X applied to input terminal 21
The difference signal from the prediction signal obtained from the D / A converter 25 is the adder 2
It is obtained in 3, integrated by the integrator 24, and the integrated output is quantized by 1 bit in the quantizer 26. The quantized 1-bit digital signal is delayed by one sample by the delay circuit 29 and then integrated by the integrator 28 to obtain the output signal Y at the output terminal 22. The prediction signal is a sum signal obtained by adding the signal delayed by one sample in the delay circuit 29 and the output signal Y in the adder 20 to an analog signal by a digital-analog converter (hereinafter abbreviated as D / A converter) 25. It is obtained by converting to.

In FIG. 5, Q represents the noise generated in the quantizer 26. The transfer functions of the input signal X and the noise signal Q of the first-order prediction / first-order noise shaping A / D converter are as shown in the following equation.

Y (Z) = Z ^-1 X (Z) + Z ^-1 (1-Z ^-1 ) Q (Z) ......
(1) As shown in equation (1), it can be seen that the noise signal is differentiated and shaped in the high frequency range. The step size of the local D / A converter 25 in the feedback loop is determined by considering amplitude overload and slope overload. The smaller the step size, the better the S / N, but it is necessary to increase the number of bits to prevent amplitude overload. Furthermore, if the step size is made small, it becomes impossible to follow the change of the input signal, and gradient overload occurs. The condition that does not cause the gradient overload is that the step size of the local D / A converter is Δ, the number of bits is N, the sampling frequency is f _S , the band of the input signal is f _B ,
When the maximum amplitude is A, it is given by the following equation.

On the other hand, the logical equation of S / N is given by the following equation from equation (1). Therefore, when trying to obtain S / N equivalent to 14 bits, f _S = 1MHz,
When f _B = 4 kHz, Δ = 1/2 ⁵ is required. At this time, in order to prevent the gradient overload, from equation (2), N5.3 is satisfied, and Δ1 / 2 ^5.3 is satisfied.

[Problems to be solved by the invention]

Solving for f _B from equation (2) as delta = 1/2 ⁵ reversed in the above-described case f _B = 5.1kHz next, if more signals 5.1KHz is input slope overload occurs. An analog signal is input to the oversampling A / D converter, but a prefilter is installed in the previous stage to avoid aliasing. That is, although it is for removing signals above the Nyquist frequency, if the cutoff frequency is made as low as possible, gradient overload in the oversampling A / D converter can also be prevented. However, the cutoff frequency must be set to about 30 kHz even if the cutoff frequency is low in order not to deteriorate the amplitude transfer characteristic and the group delay characteristic in the band.
Therefore, it is necessary to prevent gradient overload even when a signal of about 30 kHz is input. This is because if the gradient overload occurs, an in-band component is generated and the discriminability of the in-band component is deteriorated. By the way, Fig. 6 shows the input and output waveforms when a 30 kHz signal is input, and Fig. 7 shows the output spectrum, and the simulation results. It can be seen from Fig. 6 that gradient overload is occurring. Further, it can be seen from FIG. 7 that the in-band component is generated due to the gradient overload.

[Means for solving problems]

An oversampling A / D converter of the present invention is an integrator that receives a difference signal between an input signal and a prediction signal as an input, a quantizer that quantizes an output voltage of the integrator into a digital signal, and the quantizer. Circuit that delays the digital signal of the digitalizer output, a digital integrator that integrates the output of this delay circuit, and a function that converts the sum signal of the output of this digital integrator and the output of the delay circuit described above into a prediction signal Which is composed of a local D / A converter and a monitor counter, and which controls the monitor counter by the output signal of the control circuit which is controlled by the digital signal of the quantizer output, depending on the state of the monitor counter. By changing the step size of the local D / A converter, the gradient overload can be suppressed and the in-band signal discrimination can be enhanced.

That is, the basic circuit of the present invention is shown in FIG. The input signal X applied to the input terminal 1 is subtracted from the prediction signal obtained as the output of the local D / A converter 5 by the adder 3, and this avoidance signal is integrated by the integrator 4 and then the digital signal by the quantizer 6. Is quantized into. This digital signal is delayed by the delay circuit 9 to 1
After being delayed by the sampling period, it is integrated by the integrator 8 and obtained as the output signal Y from the output terminal 2. Delay circuit 9
The output of is added to the output of the integrator 8 by the adder 10,
The D / A converter 5 produces a prediction signal. The step size of this prediction signal is adjusted by the output of the control circuit 7, which is controlled by the output of the quantizer 6. The quantization noise Q is the quantizer 6
It is the noise generated in.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, X indicates an input signal applied to the analog input terminal 1, and Y indicates an output signal generated at the digital output terminal 2. The integrator 4 is composed of an operational amplifier, a capacitor and a switch.
Is quantized into a digital signal by the quantizer 6, and delayed by the delay circuit 9 for one sampling period. The integrator 8 is composed of an up / down counter, counts up / down according to the logic state of the digital signal, and integrates the signal. Reference numeral 12 is a monitor counter, and the D / A converter 5 for converting into a digital signal and an analog signal has a capacitance array section.

The difference signal between the analog input signal X and the prediction signal is integrated by the analog integrator 4, and its output is digitized by the quantizer 6. Specifically, the quantizer 6 determines positive / negative by a comparator and outputs it as a 1-bit digital signal. This 1-bit digital signal is
The up / down counter and the monitor counter 12 as a digital integrator are delayed by one cycle by the delay circuit 9.
Is input to The output of the comparator of the quantizer 6 and the output of the delay circuit 9 are input to the monitor counter 12 only when they have the same logic, and when they have different logic, the state of the counter 12 is rewritten as follows. The first bit counted from the MSB is "1"
When it is, the countdown is 4; when the 1st bit is "0", when the 2nd bit is "1", the countdown is 2; when the 1st and 2nd bits are "0", the counter status is reset. Becomes "0001". Next, the input to the up / down counter of the integrator 8 differs depending on the state of the monitor counter 12. That is, it is input to the following position counting from the LSB of the up / down counter. Counting from the MSB of the monitor counter 12, when the first bit is "1", it is the fourth bit, when the first bit is "0", when the second bit is "1", the third bit is the first bit, When the 2nd bit is "0", it is input to the 1st bit.
The state of the up / down counter becomes a digital output, and at the same time becomes a switching logic of a switch of each weighting capacity of the capacity array section of the local D / A converter 5. It is obvious that the polarity can be switched by reversing the charge / discharge by these switches, and the polarity can be determined by the state of the up / down counter. The prediction signal is determined as described above.

In the circuit shown in FIG. 5, the up / down counter may be input from the LSB depending on the state of the monitor counter at the following position. When the 1st bit counted from the MSB of the monitor counter is "1", the 1st bit is "0", the 2nd bit is "1", the 3rd bit is the 1st bit, 2 1 when the 2nd bit is 1st bit, 2nd bit, 3rd bit is "0" when the 1st bit is "0" and 3rd bit is "1"
Enter in the bit.

〔The invention's effect〕

As described above, the present invention inputs the output of the delay circuit to the corresponding digit of the up / down counter based on the information of the monitor counter. In this way, the digital value input to this up-down counter is substantially weighted, solving the problem of step-size slope overload determined by the local D / A converter, and thus to the input signal. This has an exceptional effect of significantly improving the tracking sensitivity as compared with the conventional one. As a result, by controlling the step size of the local D / A converter of the first-order prediction first-order noise shaping A / D converter with the digital signal of the quantizer output, especially when a high frequency signal is input. Also has high in-band signal discrimination without causing gradient overload, and further has the effect of suppressing generation of in-band signals of relatively high power. According to the method shown in the modified example of this embodiment, the frequency at which the gradient overload occurs can be increased.

FIG. 3 shows an input waveform when a signal of 30 kHz is input in one embodiment of the present invention, and FIG. 4 shows an output spectrum. It can be seen from FIG. 3 that the gradient overload is suppressed, and from FIG. 4 that the generation of in-band components is considerably suppressed as compared with the conventional example shown in FIG.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic circuit of an oversampling A / D converter of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an oversampling A / D converter of the present invention.
Input / output signal waveform diagram when a 30 kHz signal is input to the D converter. Fig. 4 is a diagram showing the output spectrum. Fig. 5 is a block diagram of a conventional first-order prediction first-order noise shaping type A / D converter. FIG. 6 is a waveform diagram of input / output signals at the time of inputting a signal of 30 kHz in a conventional first-order prediction first-order noise shaping type A / D converter, and FIG. 7 is a diagram showing its output spectrum. 1,21 …… Input terminal, 2,22 …… Output terminal, 3,23,10,20 ……
Adder, 4,24 ... Analog integrator, 6,26 ... Quantizer,
7 ... Control circuit, 8, 28 ... Digital integrator, 9, 29 ...
Delay circuit, 5,25 ... Local D / A converter.

Continuation of the front page (56) Reference JP-A-61-19230 (JP, A) JP-A-54-40507 (JP, A) JP-A-61-177818 (JP, A) JP-A-56-90623 (JP , A) JP 62-26928 (JP, A) JP 63-217723 (JP, A) JP-B-4-39808 (JP, B2)

Claims (1)

[Claims] 1. An analog integrator that receives a difference signal between an input signal and a prediction signal, a quantizer that quantizes an output voltage of the analog integrator into a digital signal, and a digital signal output from the quantizer. And a digital integrator having an up / down counter that counts the output of the delay circuit, and a sum signal of the output of the digital integrator and the output of the delay circuit is input and converted into the prediction signal. In an oversampling type analog-to-digital converter composed of a local digital-to-analog converter having the function to perform, the logical output of the monitor counter and the quantizer is the same or different from the immediately preceding logical output. And a control circuit for controlling addition and subtraction of the monitor counter according to the state of the monitor counter. Oversampling analog-to-digital converter, characterized in that changing the step size of the local digital-to-analog converter performs weighting to the count value of the data.