JPH082027B2 - Predictive coding device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an encoding device for highly efficient encoding of image signals.

[Conventional technology]

Generally, a television signal or the like contains many redundant components of the signal itself, and the redundancy is suppressed by predictive coding such as ΔM or DPCM in order to reduce the amount of transmission information.

The predictive encoder is basically a difference circuit that takes a difference between an input signal and a prediction circuit output signal, a quantization circuit that quantizes the difference circuit output signal, and an input signal from the quantization circuit output signal. It is composed of a prediction circuit for prediction. When a television signal is encoded, the sampling frequency is as high as around 10 MHz, and it is necessary to process the differential code loop processing in the vicinity of 100 ns, and high speed processing is required for each processing circuit. The effect of reducing the amount of transmitted information by the differential encoding, that is, the effect of suppressing redundancy increases as the characteristics of the prediction circuit become closer to the shape of the spectrum of the input signal. However, since the input signal constantly changes, it is difficult to optimize the redundancy suppression effect for all input signals.

[Problems to be Solved by the Invention]

In the conventional method described above, when applying the optimum prediction method to the television signal, it is realized by using a high-speed element even in the predictive coding process, and in the case of the adaptive type with large power consumption, the loop processing time further increases, Even if it can be realized by using a high-speed element, the processing timing margin is reduced, and there is a problem in operation stability.

The present invention has been made in view of such a point,
An object of the present invention is to provide an adaptive predictive coding apparatus in which the time limit of the predictive coding loop process is increased by a factor of n when adaptive predictive switching of a plurality of predictive characteristics is used as the predictive characteristic of the predictive coding apparatus. It is to be realized.

[Means for solving the problem]

In order to achieve such an object, the predictive coding apparatus according to the present invention sequentially stores one line of an input signal and outputs n first storages at a read speed 1 / n times the write time. Circuit, and each of the output signals of these storage circuits, the n adaptive prediction circuits that perform predictive coding processing using adaptive prediction that switches the prediction characteristics, and the output signals of these adaptive prediction circuits, respectively. , N second storage circuits that output at a read speed n times as long as the write time, and the adaptive prediction circuit includes a difference between an output signal of the first storage circuit and an output signal of a plurality of prediction circuits described later. , A first switching circuit which selects one of the output signals of the difference circuit by a selection signal described later, and an adaptive prediction circuit which quantizes the output signal of the first switching circuit. Quantization times to output And a second switching circuit that selects and switches one of the output signals of the plurality of prediction circuits by a selection signal described later, and an addition that adds the output signal of the second switching circuit and the output signal of the quantization circuit. Circuit, a plurality of prediction circuits for predicting an input signal from the output signal of the adder circuit, and the output signals of the plurality of prediction circuits are selected by a given algorithm to determine the optimum prediction circuit output signal. A selection circuit that outputs a selection signal is provided, and a plurality of n parallel processings are performed as the predictive coding processing for the force signal.

[Action]

In the predictive coding apparatus according to the present invention, the prediction loop processing time limit is a multiple of n times that of the conventional method.

〔Example〕

FIG. 1 is a block system diagram showing an embodiment of the predictive coding apparatus according to the present invention. In FIG. 1, 1 is an input terminal, 2 and 6 are first memory circuits, 3 and 7 are adaptive prediction circuits, and 4 and 8
Is a second memory circuit, and 5 is an output terminal.

Next, the operation will be described. The speed of reading the input signal a from the input terminal 1 from the memory circuit 2 by one line of the television signal is half the writing time. When the writing of one line of the television signal in the memory circuit 2 is finished and the writing is stopped, the writing of the memory circuit 6 is started, and when the writing of the television signal of one line in the memory circuit is finished, the writing is performed again. Writing is performed alternately by the method of writing to the memory circuit 2, and the output signal b of the memory circuit 2 having a cycle twice that of the input signal a is sent to the adaptive prediction circuit 3.

The difference signal c output by processing the output signal b in the adaptive prediction circuit 3 is input to the storage circuit 4. In the memory circuit 4, reading is performed at a speed twice the writing time. The difference signal h output from the adaptive prediction circuit 7 is input to the storage circuit 8 in exactly the same operation as the adaptive prediction circuit 3, but the output signal d of the storage circuit 4 and the output signal e of the storage circuit 8 alternate. It is output, returned to the same cycle as the input signal a, and output to the output terminal 5 as the signal f.

FIG. 2 is a block system diagram showing the adaptive prediction circuit 3 of FIG. 1 in detail, and the application prediction circuit 7 has the same configuration.
In FIG. 2, 31 to 33 are difference circuits, 34 is a first switching circuit, 35 is a quantization circuit, 36 is a selection circuit, 37 is a second switching circuit, 38 is an addition circuit, and 39 to 41 are prediction circuits. Is.

Next, the operation will be described. The output signal b of the memory circuit 2 in FIG. 1 is output to the difference circuits 31, 32 and 33 by the prediction circuits 41, 40 and 39, respectively.
The output signal of the difference circuit 31, 32, 33 is selected by the switching circuit 34 by the selection signal of the selection circuit 36, and the selected signal is quantized by the quantization circuit 35. Is output to the storage circuit 4 of FIG. 1 as the output signal c of the adaptive prediction circuit 3. In addition, in the switching circuit 37, the output signal of any of the prediction circuits 41, 40, 39 selected by the selection signal of the selection circuit 36 and the output signal of the quantization circuit 35 are added by the addition circuit 38, and the addition circuit 38 The output signals of the predictor circuits 41, 40, 39 predict the input signals, and the predictor circuits 41, 4
The output signals of 0 and 39 are input to the difference circuits 31, 32 and 33, respectively. The selection circuit 36 outputs the output signal of the addition circuit 38 and the prediction circuit 39.
The difference between each of the output signals and the output signals of -41 is obtained, and the optimum prediction circuit output is selected.

FIG. 3 and FIG. 4 are signal explanation diagrams showing comparison of processing times. In FIGS. 3 (a) to 3 (c), the input signal a (FIG. 3 (a)) is parallel-configured with the adaptive prediction circuit of this embodiment, so that the processing of the adaptive prediction circuit is Y in the conventional configuration. _ns ,
Although not Na unless terminated by Z _ns, the output signal b of the storage circuit 2, 6, g (FIG. 3 (b), (c)) processing time limit 2 × Y _ns as, 2 × Z Doubles with _ns .

In FIGS. 4A to 4D, the input signal a (FIG. 4A) is divided into output signals b and g (FIGS. 4B and 4C) by the storage circuits 2 and 6, respectively. Then, the signals processed by the adaptive prediction circuits 3 and 7 are integrated again in the storage circuits 4 and 8 to output the output signal f (fourth
The format of the input signal a is output as shown in FIG.

In the above embodiment, the case where the adaptive prediction circuit and the storage circuit are two has been described, but the numbers thereof are not particularly limited.
Further, although the case where the number of prediction circuits and the number of difference circuits are three has been described, the numbers thereof are not particularly limited.

EFFECTS OF THE INVENTION As described above, according to the present invention, a plurality of adaptive prediction circuits are provided.
Since the number of input signals is expanded to n layers and the predictive coding process is performed in n parallel processes, the adaptive prediction loop processing time limit is increased to n times that of the conventional method, so that the speed of the constituent elements can be reduced. It is possible to reduce the power consumption, increase the timing margin of the circuit, and the like.

[Brief description of drawings]

FIG. 1 is a block system diagram showing an embodiment of the predictive coding device according to the present invention, and FIG. 2 is a block system diagram showing in detail an adaptive prediction circuit constituting the device of FIG. 1, FIGS. 3 and 4. The figure is a signal explanatory view showing a comparison of processing times. 1 ... input terminal, 2,6 ... first memory circuit, 3,7 ... adaptive prediction circuit, 4,8 ... second memory circuit, 5 ... output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nagao Fujimi 5-33-1, Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Toru Shibuya 2nd Raijin, Yoshioka, Miyawa, Kurokawa-gun, Miyagi Miya (56) References JP-A-61-208924 (JP, A) JP-A-61-177822 (JP, A) JP-A-1-235421 (JP, A) JP-B-3-66854 (JP, B2)

Claims (1)

[Claims] 1. An n number of first memory circuits that sequentially store one line of an input signal and output at a read speed that is 1 / n times the write time, and input the respective output signals of these memory circuits. And n adaptive prediction circuits that perform predictive coding processing using adaptive prediction that switches prediction characteristics, and output signals of these adaptive prediction circuits are respectively stored and output at a read speed n times the write time. A plurality of second storage circuits, the adaptive prediction circuit includes a plurality of difference circuits that take a difference between an output signal of the first storage circuit and output signals of a plurality of prediction circuits described below, and the difference circuits. A first switching circuit for selecting one of the output signals of the circuit by a selection signal described later;
A quantizing circuit that quantizes the output signal of the switching circuit of (1) to be the output of the adaptive prediction circuit; and a second switching circuit that selects and switches one of the output signals of the plurality of prediction circuits described below by a selection signal described below. An adder circuit for adding the output signal of the second switching circuit and the output signal of the quantizer circuit, a plurality of predictor circuits for predicting an input signal from the output signal of the adder circuit, and a plurality of predictor circuits. The output signal of the selected by the algorithm provided, and the selection circuit that determines the optimum prediction circuit output signal and outputs the selection signal,
A predictive coding apparatus in which the predictive coding process for the force signal is a plurality of n parallel processes.