JPH0820860B2 - Display control system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display technique and a technique particularly effective when applied to a control device for displaying digital image information. For example, display control in a CRT (cathode ray tube display) display device. The present invention relates to a technique effectively used for a device.

[0002]

2. Description of the Related Art For example, in order to display image information written in a storage device by a computer or the like on a CRT display device, the storage device is accessed to read the image information and the access interval is changed. It is necessary to create a synchronized signal. Such a series of processing operations is performed by, for example, a CPU (central processing unit) of a computer system.
However, the task of the CPU becomes large and the overall processing capability is significantly reduced. Therefore, the present inventors have previously proposed a dedicated display control device that independently performs the above-described processing operation, that is, management of the storage device and creation of a synchronization signal (model number HD68).
45, HD68A45, HD6845S, etc .: All are Hitachi.

This display control device is also called a so-called CRTC or the like, and in order to display image information stored in a storage device on a scanning type display device which constitutes a display screen by horizontal scanning lines and vertical frames, The storage device is provided with a scan counter that is stepped in a cycle based on the access timing of the storage device and in which the count content periodically circulates, and the storage device is accessed by address data created based on the count content of the scan counter. In addition, it has a function of individually generating a horizontal synchronizing signal and a vertical synchronizing signal based on the count content of the scan counter. This CRTC is made into a semiconductor integrated circuit, and is used by being connected to a system bus of a CPU as a peripheral device, for example. As a result, the CPU is freed from the troublesome task of display control both in terms of hardware and software, and the processing capability of the entire system can be improved.

[0004]

By the way, the inventor of the present invention uses a plurality of the CRTCs and causes the image information stored in each storage device managed by each CRTC to be displayed in a superimposed manner on one display screen. I considered that. However, it has been clarified by the inventor of the present invention that the same basic clock is given to each CRTC in order to do this. That is, in the CRTC, for example, a horizontal synchronizing signal and a vertical synchronizing signal are generated in order to cause a CRT display device to display. This synchronizing signal is generated by a scanning counter that counts a basic clock given from the outside. Here, even if a plurality of CRTCs generate the same periodic signal with reference to the same basic clock, the mutual phases of the synchronization signals do not always match. For example, if the count content of the scan counter in any one of the CRTCs is different from that of the other CRTC due to a malfunction due to noise or the like, the different state appears as a phase difference of the synchronization signal, and the state is restored thereafter. It continues without being done. As a result, the positional relationship of the superimposed images is disturbed,
Or the synchronization will be disturbed.

It is an object of the present invention to display a plurality of image information items managed by a plurality of CRTCs so that they can be superimposed on one display screen while maintaining a fixed positional relationship with each other. It provides technology.

Also, image information and C displayed on a display system having an independent synchronizing signal system such as a television system.
(EN) Provided is a display technology capable of displaying image information managed by an RTC on one display screen in an overlapping manner while maintaining a fixed positional relationship with each other.

The above-mentioned and other objects and novel features of the present invention will be apparent from the description at the outset of the main request and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, the count content of the scanning counter provided for generating a synchronizing signal in the CRTC is forcibly initialized to a constant content by a signal from the outside.

[0010]

According to the above-mentioned means, the phase difference between the sync signal in the CRTC and the external sync signal is corrected periodically or appropriately, so that a plurality of pieces of image information do not disturb the mutual positional relationship. Will be displayed overlaid on.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENT A typical embodiment of the present invention will be described below with reference to the drawings.

In the drawings, the same or corresponding parts are designated by the same reference numerals.

FIG. 1 shows an embodiment of a main part of a display control device according to the present invention.

The display control device 10 shown in FIG. 1 is also called a so-called CRTC. First, its outline will be described. The image information stored in the storage device is displayed on a display screen by horizontal scanning lines and vertical frames. In order to display on the scanning type display device constituting the above, the scanning counters C ₁ and C ₂ are stepped in a cycle based on the access timing of the storage device and the count contents are cyclically circulated.
Is provided. Count contents D of the scanning counters C ₁ and C ₂
The storage device is accessed by the address data Ad created based on ₁ and D ₂ . At the same time, the horizontal synchronizing signal Hs and the vertical synchronizing signal Vs are respectively generated based on the count contents D ₁ and D ₂ of the scanning counters C ₁ and C ₂ . The contents of the scan counters C ₁ and C ₂ are initialized to a constant value by a signal Ex provided from the outside.

[0015] Here, the scanning counter C _1, C ₂ is made from a second scan counter C ₂ Metropolitan synchronizing the first scan counter C ₁ and vertical frame synchronizing horizontal scan line, the first , The second scanning counters C ₁ and C ₂ are both initialized to constant count contents by a signal supplied from the outside.

In addition, the display control device 10 is configured as a semiconductor integrated circuit (LSI), and is configured to be used by being connected to a system bus of a CPU as a peripheral device, for example. As the display device, for example, an interlaced (interlaced) scanning CRT display device is used. The storage device is called a refresh memory or a video RAM (VRAM), and is usually RA.
M (random access memory) is used.

More specifically, referring to FIG.
In addition to the above-mentioned first and second scan counters C ₁ and C ₂ , the device shown in the figure has an access timing detection counter C ₀ , data comparison circuits CP ₀ , CP ₁ and CP ₂ , an address generation circuit 20. , An interlace control circuit 12, a pulse cutting circuit 14, a terminal switching circuit 16, and an AND gate G1. Although not shown, a control register group that can be written from outside is provided, and various operation modes of the display control device 10 can be set or selected according to the contents written in these register groups. There is. Control reference values R ₁ and R _{2 of} the data comparison circuits CP ₁ and CP ₂ and switching of the terminal switching circuit 16 Control signal R which defines an embodiment
_{4 and the} like are also set by the control register group.

The display controller 10 has a basic clock φ.
Is entered. The basic clock φ is synchronized with the clock of the system to which the display device 10 is connected, for example. This basic clock φ serves as a count input of the access timing detection counter C ₀ . The counter C ₀ is incremented by the basic clock φ, and when the count content D ₀ reaches the comparison reference value R ₀ of the data comparison circuit CP ₀ , it is reset and restarts counting from the initial value (0). Has become. That is, the count content D ₀ is cyclically circulated. Then, the pulse signal P ₀ output from the data comparison circuit CP _{0 for} each circulation cycle is stored in the storage device (RAM) in which image information is stored.
Is output to the outside as the access control signal CE. As a result, the storage device is accessed at regular intervals,
Pixel information for one word (for example, 8 bits or 16 bits) is read at each access timing.

Further, the pulse signal P ₀ serves as a count input of the first scanning counter C ₁ . The counter C ₁ is incremented by the input pulse signal P ₀ , and when the count content D ₁ reaches the comparison reference value R ₁ of the data comparison circuit CP ₁ , it is reset and restarts counting from the initial value (0). It is like this. That is, the count content D ₁ is cyclically circulated. Then, the pulse signal P ₁ output from the data comparison circuit CP _{1 in} each circulation cycle passes through the interlace control circuit 12 to CR.
It is output to the outside as a horizontal synchronizing signal Hs of the T display device. At this time, the circulation cycle of the _first scan counter C ₁ is
It corresponds to a period in which the image information for one horizontal scan is read from the storage device. That is, the comparison reference value R ₁ is set so that the count content D ₁ of the first scanning counter C ₁ returns to the initial value (0) when the image information for one raster is read.

The pulse signal P ₁ issued in each cycle of the first scan counter C ₁ becomes the count input of the _second scan counter C ₂ . This counter C ₂ is incremented by its input pulse signal P ₁ and its count content D ₂
There reaches the comparison reference value R ₂ of the data comparison circuit CP _2, is adapted to resume the counting being reset from the initial value (0). That is, this second scanning counter C
Also in ₂ , the count content D ₂ is cyclically circulated. Then, the pulse signal P ₂ output from the data comparison circuit CP _{2 in} each circulation cycle passes through the interlace control circuit 12 and the vertical synchronization signal V of the CRT display device.
It is output to the outside as s. At this time, the circulation cycle of the second scanning counter C ₂ corresponds to a period in which one field of image information is read from the storage device. That is, 1 / of the total number of rasters that make up the display screen
The comparison reference value R ₂ is set so that the count content D ₂ of the second scanning counter C ₂ returns to the initial value (0) when the image information corresponding to 2 is read. Then, every time the circulation cycle of the second scanning counter C ₂ is repeated twice, the image information for two fields, that is, one frame, is read out and displayed on the CRT display device in the interlaced mode. For example, when displaying on a normal television CRT display device, the vertical synchronizing signal Vs is generated about 60 times per second, and thereby a frame of 30 frames per second is generated.

The first and second scan counters C ₁ and C ₂
The count contents D ₁ and D _{2 of the above} are given to the address generation circuit 20. The address generation circuit 20 creates address data Ad for accessing the storage device based on the _two count contents D ₁ and D ₂ . As a result, the image information stored in the storage device is changed to the synchronization signal Hs,
The data is read in synchronization with Vs.

The interlace control circuit 12 inserts a dummy raster into the horizontal synchronizing signal Hs in order to perform so-called interlaced scanning, and the phase of the vertical synchronizing signal Vs is every other half horizontal scanning period. Scanning is performed by shifting only. Therefore, the interlace control circuit 12 has a function of discriminating an odd-numbered field period from an even-numbered field period. This function can be easily obtained by using, for example, a binary flip-flop stepped by a vertical synchronizing signal. Therefore,
From the interlace control circuit 12, for example, an odd field (or even field) detection signal Vi which is activated only during an odd field period (or even field period) can be obtained for each frame.

Here, the AND gate G ₁ calculates the logical product of the odd field detection signal Vi obtained from the interlace control circuit 12 and the pulse signal P ₂ issued in each cycle of the _second scan counter C _2. Then, only the odd-numbered vertical synchronizing signals are extracted. The odd-numbered vertical sync signal thus extracted is led out of the display control device 10 via the terminal switching circuit 16 as an external sync signal Ex.

Although the portion which issues the synchronizing signal Ex to the outside has been described above, the display control circuit 10 is also configured to receive the synchronizing signal Ex from the outside. The synchronizing signal Ex from the outside is an odd-numbered (or even-numbered) vertical synchronizing signal like the synchronizing signal Ex output to the outside. The synchronizing signal Ex from the outside is input to the pulse cutout circuit 14 via the terminal switching circuit 16. The pulse cutout circuit 14 cuts out a narrow pulse from the external synchronization signal Ex. Then, the cut-out narrow pulse is distributed as a clear signal (reset signal) CR to each of the counters C ₀ , C ₁ and C ₂ . Thus, when the external synchronizing signal Ex is input, is thereto synchronously each counter C _0, C _1, the count content D ₀ of C _2, D _1, D ₂ are initialized at once (reset to 0) Become so. This initialization is performed by, for example, the external synchronization signal E.
If x is from the display control device 10 having the same configuration,
It is performed for each frame. Therefore, if each counter C
_{If a} count error occurs in any of ₀ , C ₁ , and C ₂ , the error is automatically corrected at the start of the next frame period. As a result, the mutual synchronization between the plurality of display control devices can be surely kept consistent, and the image information described in the plurality of storage devices can always be displayed in a superimposed relationship in the correct positional relationship. . As a result, for example, composing a plurality of images to form a plurality of or various images can be performed easily and at high speed.

Here, in the present embodiment, whether the external synchronizing signal Ex is output to the outside or input from the outside is determined by the switching state of the terminal switching circuit 16. Further, this terminal switching circuit 16
The switching state of is controlled by the control signal R ₄ set by the register group. Therefore, whether the display control device 10 is used as a master or a slave can be freely selected by an external setting operation for the register group (not shown) which is performed when the display control device 10 is used. At the same time, only one input / output terminal for the signal Ex for synchronizing a plurality of display control devices with each other is required.

FIG. 2 is a timing chart showing an operation example of the above-mentioned display control device.

In the figure, Ta represents a memory access cycle, Th represents a horizontal scanning period, Tv represents a field period, and Ts represents a cycle of an external synchronization signal Ex issued for each frame.

FIG. 3 shows a usage example of the display control device 10 described above.

In the use example shown in the figure, two display control devices 10A and 10B are used. Each display control device 1
0A and 10B are connected to the address bus AB and the data bus DB of the computer system 100, respectively, so as to operate as peripheral devices of the computer system 100. The computer system 100 includes, for example, a CPU, ROM, RAM and I / O.
Etc.

Each display control device (CRT1, CRT2) 1
Reference numerals 0A and 10B manage storage devices (VRAM) 30A and 30B in which image information is stored. Each storage device 3
The image information read from each of 0A and 30B includes parallel-serial conversion circuits (P / S conversion circuits) 32A and 3A.
After being converted into serial image signals Sa and Sb by 2B, they are input to the video controller 40 together with the vertical synchronizing signal Vs and the horizontal synchronizing signal Hs output from the display control device 10A. The video controller 40 receives the image signal S of the CRT display device 50 based on the input signal.
The ab and the synchronization signal Ss are created. As a result, the CRT display device 50 displays the image information Sa and Sb read from the two storage devices 30A and 30B in a state of being superimposed on each other.

Here, the two display control devices 10A, 10
Of the B devices, one device 10A is set to issue a synchronization signal Ex to the outside every frame period. The other device 10B is set so as to receive the external synchronization signal Ex emitted from the one device 10A. That is, when the display control device is used, the internal register of the display control device 10A is set by the computer system 100 so that the display control device 10A becomes the master.
The internal register is set so that the display control device 10B becomes a slave. As a result, one display control device 10A operates as a master, and the other display control device 10B operates as a slave.
B reliably follows and synchronizes with the device 10A.

FIG. 4 shows another embodiment of the present invention.

The embodiment shown in the figure uses the above-described display control device 10, and the image information St displayed on a display system having an independent synchronizing signal system such as the television system 60 and the above-mentioned image information St. The image information Sc managed by the display control device 10 can be superimposed and displayed on one CRT display device 50 while maintaining a fixed positional relationship with each other.

Regarding the display control device 10, as in the case described above, the interlaced scanning type display device in which the image information stored in the storage device 30 constitutes a display screen by horizontal scanning lines and vertical frames, that is, in this case. Is a CRT
In order to display on the display device 50, a scanning counter is provided, which is stepped in a cycle based on the access timing of the storage device 30 and whose count content is cyclically circulated. The storage device 30 is accessed by the address data Ad created based on the count content of the scan counter. Further, horizontal and vertical synchronizing signals are generated based on the count contents of the scanning counter.

The television system 60 receives the image information St on the television system 60 side from the synchronization signal S created independently.
It is displayed on the CRT display device 50 using s.

Here, the display control device 10 is used together with a phase difference detection circuit 62, an AND gate G11, a basic clock generation circuit 64 formed by using a PLL (phase locked loop), and the like.

The basic clock generating circuit 64 creates the basic clock φ for the display control device 10 based on the horizontal synchronizing signal Hst issued from the television system 60. The display control device 10 creates the access control signal of the storage device 30, the address data Ad, the vertical synchronization signal Vs, etc. based on the basic clock φ.

The phase difference detecting circuit 62 detects the phase difference between the vertical synchronizing signal Vs emitted from the display control device 10 and the vertical synchronizing signal Vst emitted from the television system 60. FIG. 5 shows the phase difference detection circuit 62 and the AN.
7 shows a timing chart of the external synchronization signal Ex generated by the D gate 11. The timing indicated by the broken line is a comparison signal used inside the phase difference detection circuit 62. Here, as shown in FIG. 5, the phase difference detection circuit 62
Then, the vertical synchronization signal Vs issued from the display controller 10
And the vertical synchronizing signal Vs emitted from the television system 60.
The phase detection with t is performed while comparing the relationship between the vertical synchronization signals. (Detects whether the vertical sync signal is an odd number or an even number, and compares them). Accordingly, the AND output of the phase difference detection circuit 62 is ANDed by the AND gate G11 and the vertical synchronization signal Vst issued from the television system 60 is ANDed to obtain the vertical synchronization signal Vs.
A pulse output under synchronization is obtained at t. By applying this pulse output to the display control device 10 as the external synchronization signal Ex, the initialization timing of the contents of each counter in the display control device 10 is set to an odd-numbered (even-numbered) vertical synchronization signal on the television system 60 side. Can be periodically synchronized to.

Note that the display control device 10 in this case, by a command from the computer system 100 side,
It is preset to operate as a slave.

As described above, the image information St displayed by the display system having the independent synchronizing signal system such as the television system 60 and the image information Sc managed by the display control device 10 are mutually exchanged. It is possible to superimpose and display on one display screen while maintaining a fixed positional relationship.

(1) In the above embodiment, the storage device is accessed by the address data created based on the count content of the scan counter, and the horizontal sync signal and the vertical sync signal are respectively supplied based on the count content of the scan counter. In this configuration, the count content of the scanning counter is initialized to a constant value by an externally applied signal, and a plurality of images respectively managed by a plurality of CRTCs are generated. It is possible to obtain the effect that the information can be displayed in an overlapping manner on one display screen while maintaining a fixed positional relationship with each other.

(2) In the above embodiment, the storage device is accessed by the address data created based on the count content of the scan counter, and the horizontal synchronizing signal and the vertical sync signal are generated based on the count content of the scan counter. Each of the plurality of CRTCs manages a plurality of signals, each of which is synchronized with the odd-numbered or even-numbered vertical sync signal to be output to the outside. It is possible to obtain the effect that the image information of (1) can be jumped over and displayed on the scanning display device while maintaining a constant positional relationship with each other.

(3) The above embodiment is configured so that the storage device is accessed by the address data created based on the count contents of the scan counter, and with this, the interlaced scanning having an independent synchronizing signal system. A horizontal synchronizing signal and a vertical synchronizing signal are received from the display system of the system, and a clock for determining the access timing of the storage device is created based on the horizontal synchronizing signal, and either an odd number or an even number from the vertical synchronizing signal. By detecting one of the vertical sync signals and forcibly initializing the content of the scanning counter to a constant value based on the detected signal, an independent sync signal system like a television system is provided. The image information displayed on the display system having the image and the image information managed by the CRTC are mutually fixed to a certain degree. While maintaining the relationship, can be displayed superimposed on one display screen, the effect is obtained that.

By the above (1) and (2), it is possible to obtain a synergistic effect that a plurality of images can be combined to create a plurality of or various images easily and at high speed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the CRT display device may be a liquid crystal display device or a plasma display device. The interval of the external synchronization signal Ex may be every several frames or any time interval longer than that.

In the above embodiment, the case where the invention is applied to the display control device for the interlaced scanning type display device is explained, but the present invention can be applied to the display control device which performs the progressive scanning type display. is there.

In the above description, the invention mainly made by the present inventor is the field of application which is the background of the invention.
The case where the present invention is applied to the synchronization technology of the display control device of the display device has been described, but the present invention is not limited to this. For example, a display control device having an intelligent processing function of judging the content of image information and rewriting it. It can also be applied to synchronization technology in. It can be applied at least under the condition that synchronization or alignment is required.

[0048]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to superimpose and display a plurality of pieces of image information without disturbing the mutual positional relationship.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of a display control device constituting a display control system according to the present invention.

FIG. 2 is a timing chart showing the operation of the device shown in FIG.

FIG. 3 is a block diagram showing an embodiment of a display control system according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the display control system.

5 is a timing chart showing an operation state of a part of the device shown in FIG.

[Explanation of symbols]

10, 10A, 10B Display control device (CRTC) 12 Interlace control circuit 14 Pulse cutout circuit 16 Terminal switching circuit 20 Address generation circuit 30, 30A, 30B Storage device (refresh memory or VRAM) 32, 32A, 32B Parallel-serial conversion circuit (P / S conversion circuit) 40 video controller 50 CRT display device 60 interlaced scanning type display system having independent sync signal system (television system) 62 phase difference detection circuit 64 basic clock generation circuit 100 computer system AB address bus DB Data bus C ₀ Access timing detection counter C ₁ First scanning counter C ₂ Second scanning counter CP ₀ , CP ₁ , CP ₂ Data comparison circuit G ₁ , G ₁₁ AND gate D ₀ Access timing detection counter count Content D ₁ Count content of the first scan counter D ₂ Count content of the second scan counter R ₀ , R ₁ , R ₂ Comparison reference value R ₄ Switching control signal Ad Address data CE Access control signal Hs, Hst Horizontal sync signal Vs, Vst Vertical synchronization signal Ex External synchronization signal φ Basic clock Sa, Sb, Sab Image signal Ta Access cycle Th Horizontal synchronization period Tv Field period Ts Period of external synchronization signal CR Clear signal

Claims (9)

[Claims] 1. A memory for storing image data, a video signal generating means for generating an image signal and a synchronizing signal to be displayed on a display device, and a memory connected to the memory and the video signal generating means and selected in advance. A display control device configured to access the memory to read image data to be displayed on a plurality of horizontal scanning lines of the display device based on the generated timing. Is a register means for storing first data for indicating the first reference value, second data for indicating the second reference value, and third data for indicating one of the internal mode and the external mode. A horizontal counter means that is stepped in response to the periodic pulse signal, and a horizontal counter means when the count content of the horizontal counter means matches the first data. First for outputting a synchronization signal
A comparing means; a vertical counter means which is stepped in response to the horizontal synchronizing signal; and a second counter for outputting a vertical synchronizing signal when the count content of the vertical counter means matches the second data.
Comparing means and address generating means for generating an address signal for accessing the memory based on the count contents of the horizontal counter means and the vertical counter means, and when the third data indicates the internal mode ,
An initial value is set in the horizontal counter means on the basis of a signal indicating a match between the count content and the first data from the first comparing means, and the vertical counter means is provided with the count from the second comparing means. When the initial value is set on the basis of the signal indicating the match between the contents and the second data, and the third data indicates the external mode, the horizontal counter means and the vertical counter means receive the initial value in accordance with an external signal. A display control system, wherein the display control system is configured to be set. 2. The register means has a first register for storing the first data, a second register for storing the second data, and a third register for storing the third data. The display control system according to claim 1, wherein: 3. The display control system according to claim 1, wherein the initial value is 0. 4. Two or more memories for storing image data, and for reading out image data to be displayed on a plurality of horizontal scanning lines of a display device, each connected to the memories and based on a preselected timing. A display control system configured by two or more display control devices that access a memory, wherein each of the display control devices includes a terminal for supplying a signal, first data for indicating a first reference value, Register means for storing second data for indicating the second reference value and third data for indicating one of the internal mode and the external mode, and horizontal stepped in response to the periodic pulse signal. A first means for outputting a horizontal synchronizing signal when the count contents of the counter means and the horizontal counter means match the first data.
A comparing means; a vertical counter means which is stepped in response to the horizontal synchronizing signal; and a second counter for outputting a vertical synchronizing signal when the count content of the vertical counter means matches the second data.
A comparison unit, an address generating means for generating an address signal for accessing the memory based on the count contents of the horizontal counter means and the vertical counter means, for coupling said terminal to said horizontal counter means and the vertical counter means The display control device according to any one of claims 1 to 5, wherein the horizontal counter corresponds to the third data indicating the internal mode.
Means for counting the count from the first comparing means and the first
The initial value is set based on the signal indicating the agreement with the data.
And the vertical counter means is provided with the second comparison means.
Based on the signal indicating the match between the above count content and the second data
An initial value is set based on the above, and a sync signal based on the vertical sync signal is supplied to the terminal. Another display control device responds to the third data indicating the external mode. characterized by being configured so that the initial value respectively to said horizontal counter means and the vertical counter means is set from the terminal 1 of the display control device in accordance with the sync signal supplied to the terminal of the other of the display control device And display control system. 5. The register means has a first register for storing the first data, a second register for storing the second data, and a third register for storing the third data. The display control system according to claim 4, wherein: 6. The display control system according to claim 4, wherein the initial value is 0. 7. A display device and a display device to be displayed on the display device.
Image signal, horizontal sync signal and vertical sync signal
Video signal generating means for storing the video signal and the video signal generating means
And an image signal is formed separately from the above image signal.
A display control system configured by display control means , wherein the display control means includes first data for indicating a first reference value, second data for indicating a second reference value, and internal data. Register means for storing third data for indicating one of the mode and the external mode, horizontal counter means which is stepped in response to a periodic pulse signal, and the count content of the horizontal counter means is 1st for outputting horizontal sync signal when 1 data matches
A comparing means; a vertical counter means which is stepped in response to the horizontal synchronizing signal; and a second counter for outputting a vertical synchronizing signal when the count content of the vertical counter means matches the second data.
Comparing means, and when the third data indicates the internal mode,
The horizontal counter means is provided with the above-mentioned one from the first comparing means.
Based on the signal indicating the match between the count content and the first data
The initial value is set by the
2 One of the above-mentioned count content from the comparison means and the second data
An initial value is set on the basis of the signal indicating the match and the third data indicates the external mode , based on the horizontal synchronizing signal and the vertical synchronizing signal from the video signal generating means.
The horizontal counter means and the vertical counter means, respectively.
A display control system characterized by being configured so that the initial value is set . 8. The display control means generates a first synchronizing signal synchronized with a horizontal synchronizing signal from the video signal generating means and a second synchronizing signal synchronized with a vertical synchronizing signal from the video signal generating means. 8. The display control system according to claim 7, further comprising a synchronization signal generating means for performing the above. 9. The display control system according to claim 8, wherein the periodic pulse signal is the first synchronization signal.