JPH0820945B2 - Microprocessor - Google Patents

Description

Detailed Description of the Invention 【Overview】

Regarding a microprocessor of a micro program control system, a micro program ROM storing a micro program for executing each machine language instruction and a bus in response to a memory access command are provided for the purpose of improving the processing speed of the microprocessor. A memory access unit for accessing an external memory via the CPU and outputting a wait signal indicating that the bus is in use; and various instructions including the memory access command for sequentially reading microinstructions from the microprogram ROM to execute a machine language instruction. A microprogram controller that issues a control command and stops the operation in response to the wait signal;
In the microprocessor provided with, the microprogram control unit outputs a bus check signal when it is necessary to stop its own operation to avoid a bus collision,
Only when a bus check signal is supplied from the micro program control unit, a wait control circuit for transferring the wait signal from the memory access unit to the micro program control unit is additionally provided.

[Industrial applications]

The present invention relates to a microprocessor of a micro program control system.

[Prior art]

In this type of microprocessor, a microprogram for executing each machine language instruction is stored in the microprogram ROM, and the microprogram control unit sequentially reads the microinstruction from the microprogram ROM to execute the machine language instruction. Then, various control commands are issued to the memory access unit, the arithmetic unit, and the like. In a conventional microprocessor, when the microprogram control unit supplies a memory access command to the memory access unit, the memory access unit acts on the internal bus during its operation. Therefore, a wait signal is sent to the microprogram control unit to avoid bus collision. It was supplied, and the operation of the microprogram controller was stopped.

[Problems to be Solved by the Invention]

However, even if the memory access unit uses the internal bus, the microprogram control unit may
It may be possible to execute processing without causing a bus collision. For example, in a 2-byte operation, there are cases where the operation unit can execute the operation of the lower byte without using the internal bus while the upper byte is being accessed by the memory access unit. Conventionally, even in such a case, the operation of the micro program control unit is stopped, so that the processing efficiency is lowered, which is a cause of impeding the speeding up of the processing of the microprocessor. An object of the present invention is to improve the processing speed of a microprocessor in view of such problems.

[Means for Solving the Problems]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle configuration of the present invention will be described with reference to FIG. In the figure, 26 is a microprogram ROM, which stores microprograms for executing each machine language instruction. Reference numeral 18 denotes a memory access unit, which accesses an external memory via the bus 12 in response to a memory access command and outputs a wait signal indicating that the bus is in use. Reference numeral 16 denotes a micro program control unit, which sequentially reads micro instructions from the micro program ROM 26 to execute machine language instructions, issues various control instructions including the memory access instruction, and executes its own operation to avoid a bus collision. A bus check signal is output when it needs to be stopped, and the operation is stopped in response to the wait signal. Reference numeral 28 denotes a wait control circuit, which transfers the wait signal from the memory access unit 18 to the micro program control unit 16 only when the bus check signal is supplied from the micro program control unit 16.

[Action]

When the memory access unit 18 uses the bus 12, if the processing such as the operation can be executed without using the bus 12, the microprogram control unit 16 performs the bus check after executing this processing. Output a signal. When the memory access unit 18 receives the memory access command,
A wait signal is output to avoid a bus collision, but this wait signal is not supplied to the micro program control unit 16 until the bus check signal is output from the micro program control unit 16, and the micro program control unit 16 is in an operable state. Becomes Therefore, the parallel processing of the micro program control unit 16 and the memory access unit 18 is possible, and the processing speed of the microprocessor is improved.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the main configuration of the microprocessor 10 of the micro program control system. In the microprocessor 10, an instruction register 14, a micro program control unit 16, a memory access unit 18, an arithmetic unit 20, and a general-purpose register 22 are connected by an internal bus 12. When a machine language instruction is read from an external memory (not shown) and held in the instruction register 14 via the internal bus 12, the instruction decoder 24 decodes the machine language instruction,
The result is supplied to the microprogram controller 16. The microprogram control unit 16 outputs a series of microinstructions for executing this machine language instruction to the microprogram ROM 2
The data is sequentially read from 6 and a control command is supplied to the memory access unit 18, the arithmetic unit 20, or the general-purpose register 22 based on each microinstruction. For example, when performing an operation between the contents of the general-purpose register 22 and the contents of the external memory, the microprogram controller 16 supplies a memory access command to the memory access unit 18 in order to read the data from the external memory. In this case, since the memory access unit 18 uses the internal bus 12,
A wait signal is output so that bus collision does not occur. This weight signal was supplied directly to the microprogram control unit 16 in the past, but is supplied to the weight control circuit 28 in this embodiment. As shown in FIG. 1, the weight control circuit 28 is composed of an RS flip-flop 30, a NAND gate 32 and an inverter 34. The micro program controller 16 sends a bus check to the set input terminal S of the RS flip-flop 30. A signal is supplied, the Q output of the RS flip-flop 30 is supplied to one input terminal of the NAND gate 32, the wait signal from the memory access unit 18 is supplied to the other input terminal of the NAND gate 32, and the output of the NAND gate 32 is , Is supplied to the reset input terminal R of the RS flip-flop 30 and is also supplied to the micro program control unit 16 via the inverter 34. In FIG. 2, reference numeral 36 is a system control unit, which controls the entire microprocessor 10. In the above configuration, when the memory access unit 18 supplies the memory access command to the memory access unit 18 and the memory access unit 18 uses the internal bus 12, if the micro program control unit 16 cannot execute the next process, The micro program control unit 16 outputs a bus check signal (high level) to the memory access unit 18 at the same time as the memory access command. As a result, the Q output of the RS flip-flop 30 becomes high level, and the wait signal output from the memory access unit 18 is supplied to the micro program control unit 16 via the NAND gate 32 and the inverter 34.
The operation of the micro program control unit 16 stops. The RS flip-flop 30 is reset when the memory access process is completed and the wait signal becomes low level. In this case, the micro program control unit 16 and the memory access unit 18
The operation state transition of is similar to that in the conventional case shown in FIG. However, when the memory access unit 18 uses the internal bus 12, if it is possible to execute processing such as operation without using the internal bus 12, for example, in the memory access unit 18 in 2-byte operation. While the upper byte is being accessed, if the arithmetic unit 20 can execute the arithmetic operation of the lower byte without using the internal bus 12, the following parallel processing is performed. That is, the micro program control unit 16 outputs the bus check signal after executing this arithmetic processing. The memory access unit 18 outputs a wait signal immediately upon receiving a memory access command, but the Q output of the RS flip-flop 30 is at a low level until the bus check signal is output from the microprogram control unit 16, and the NAND gate 32 is provided. Since this is closed, the wait signal is not supplied to the micro program control unit 16 during this period, the micro program control unit 16 is in the operable state, and the arithmetic processing is performed. Then, when the bus check signal is output from the micro program control unit 16, the NAND gate 32 is opened and this wait signal is supplied to the micro program control unit 16, and the micro program control unit 16 is stopped. Therefore, as shown in FIG. 3, the microprogram controller 16 and the memory access unit
18 parallel processings are possible, and the processing speed of the microprocessor 10 is improved.

【The invention's effect】

As described above, in the microprocessor according to the present invention, even if the memory access unit uses the bus, the wait signal is not supplied to the micro program control unit until the bus check signal is output from the micro program control unit. Since the micro program control unit is in the operable state and therefore the parallel processing of the micro program control unit and the memory access unit is possible, there is an excellent effect that the processing speed of the microprocessor is improved as compared with the conventional case.

[Brief description of drawings]

1 to 3 relate to an embodiment of the present invention, FIG. 1 is a detailed configuration diagram of a main portion of FIG. 2, and FIG. 2 is a block diagram showing a main configuration of a microprocessor of a micro program control system, FIG. 3 is an operation state transition diagram of the microprogram control unit and the memory access unit. FIG. 4 is an operation state transition diagram of a microprogram control unit and a memory access unit of a conventional microprocessor. In the figure, 10 is a microprocessor 12, is an internal bus 16, is a microprogram control unit 18, is a memory access unit 20, is an arithmetic unit, 26 is a microprogram ROM, 28 is a wait control circuit, 30 is an RS flip-flop.

Claims (1)

[Claims] 1. A microprogram ROM (26) storing a microprogram for executing each machine language instruction.
A memory access unit (18) for accessing an external memory via the bus (12) in response to a memory access command and outputting a wait signal indicating that the bus is in use; and the microprogram for executing a machine language instruction. ROM
A microprogram control unit (16) for sequentially reading microinstructions from the memory, issuing various control commands including the memory access command, and stopping the operation in response to the wait signal; The control unit (16) outputs a bus check signal when it is necessary to stop its own operation to avoid a bus collision, and only when the bus check signal is supplied from the microprogram control unit, the memory access unit. 10. A microprocessor characterized in that a wait control circuit (28) for transferring the wait signal from the microcomputer to the micro program controller is attached.