JPH0821572B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device. In particular, Al
Even when a layer is etched on a base layer made of a material such as (aluminum) that can cause a spatter phenomenon by etching, a redeposition (redeposition) phenomenon of the base layer due to sputtering can be prevented. It relates to a manufacturing method.

[Outline of Invention]

When manufacturing a semiconductor device by forming a hole for connection,
When the inorganic material layer on the underlayer made of a material capable of causing a spattering phenomenon by etching, redeposition of the underlayer material due to sputtering may occur due to the etching. At least a bottom portion of the connection hole formed in, a buffer layer made of a material having high etching resistance against the dry etching is formed, and the dry etching is performed.
Further, the above-mentioned problem is solved by etching the buffer layer using the dry-etched layer as a mask.

[Conventional technology]

From the necessity of fine processing associated with the improvement of the integration degree of LSI,
The introduction of dry etching technology such as RIE (Reactive Ion Etching) into each process is remarkable. RIE has also come to be used for forming holes in the manufacture of semiconductor devices, for example, forming via holes in an interlayer insulating film when forming Al 2 layer wiring. The via hole anisotropically processed by RIE has a steep step shape, which may cause step breakage when coating the via hole with Al.
This leads to unfavorable results such as reduced yield and reduced reliability. In order to avoid this, a method of tapering the via hole before the second layer Al coating is widely adopted at present. As a method of tapering the shape of the via hole, one using solution etching (see, for example, JP-A-60-28245), one utilizing resist receding during RIE, and one anisotropic processing It is known that the via hole is covered with an interlayer insulating film again and anisotropically etched to form a sidewall spacer. However, because of the solution etching, there is a problem in the controllability when forming the side-etched region.
It is hard to say that it is a process for. Although and have been put into practical use at present, in both cases, re-deposition of Al (redeposition is abbreviated. The same applies hereinafter) occurs by over-etching the underlying Al film during taper formation.
However, there is a problem that the re-deposited substance adheres to the side wall of the via hole, which adversely affects the step coverage of Al when the second layer of Al is coated, resulting in a decrease in the reliability of the wiring. That is,
Since Al causes a spattering phenomenon by dry etching such as RIE, spattering occurs during etching for forming a taper in a via hole, which may cause a so-called redeposition phenomenon in which this is redeposited, which is a problem. Since the re-deposited material cannot be removed by post-treatment or the like, it is necessary to prevent such re-deposition phenomenon from occurring originally.

[Problems to be solved by the invention]

As described above, in the prior art, when an etching process is performed on an interlayer insulating film or the like on an underlayer made of a material capable of exhibiting a sputtering phenomenon by dry etching such as Al, the underlayer material causes a sputtering phenomenon, There was the problem of redeposition.

This is a problem that may occur when not only Al but also a material that can be sputtered is used as a base layer and an inorganic material layer (interlayer insulating film or the like) thereon is dry-etched.

The present invention solves such a problem, and even when the upper inorganic material layer is dry-etched using the underlayer of the material as described above, etching can be achieved with good controllability and the re-use of the material can be improved. An object of the present invention is to provide a method for manufacturing a semiconductor device in which deposition does not occur.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a connection hole in an upper layer made of an insulating material formed on an underlayer, and the upper layer or the upper layer after the hole is formed. In a method for manufacturing a semiconductor device, which comprises at least a step of dry-etching an inorganic material layer formed above, the underlayer is made of a material that can cause a sputtering phenomenon by dry etching, and an upper layer above the underlayer is formed. A buffer layer made of a material having a high etching resistance against the dry etching is formed on at least the bottom of the formed connection hole, the dry etching is performed, and the dry-etched layer is used as a mask. The technical object of etching the buffer layer achieves the above object.

The configuration of the present invention will be described below with reference to an embodiment of the present invention illustrated in FIG.

In the illustrated example, the present invention is applied to dry-etch the inorganic material layer which is the upper layer 2 formed on the underlayer 1, and here, in particular, a tapered connecting hole 4 (where the upper surface of the opening is widened) In the illustrated example, a lower layer Al wiring which is the underlayer 1 and a via hole for connecting the upper layer wiring are formed, and the underlayer 1 is made of a material (here, a sputter phenomenon) which may occur by dry etching. In the case of dry-etching the inorganic material layer 2 on the underlayer 1 which has been subjected to the step of forming the connection hole 4 in the upper layer 2 on the underlayer 1. , The underlayer 1
A buffer layer 5 made of a material having a high etching resistance against the dry etching applied to the inorganic material layer 2 is formed on at least the bottom of the hole 4, and the inorganic material layer is dry-etched (see FIGS. 1A and 1B). )), And further, the step of etching the buffer layer 5 using the dry-etched inorganic material layer 2 as a mask (FIG. 1D).

In the illustrated example, the photoresist 3 as shown in FIG. 1 (a) is used to form the via hole 4 as shown in FIG. 1 (b).
Further, when the via hole 4 is tapered by etching, the present invention is applied.

That is, the underlayer 1 is made of a material exhibiting a spattering phenomenon by etching, but at the time of etching for taper processing, a buffer layer 5 is formed on the underlayer 1 exposed at least at the bottom of the hole 4 and etched ( See FIG. 1C. In the illustrated example, the buffer layer 5 is formed in advance). Since the buffer layer 5 is present in this manner, neither the sputter phenomenon of the underlayer 5 nor the re-deposition phenomenon occurs.

If the present invention is adopted in the step of forming the via hole 4 in the interlayer insulating film as the upper inorganic material layer 2, for example, the redeposition of the underlying layer 1 (Al or the like) which becomes a problem at the time of forming a taper by etching the via hole 4 is performed. Can be prevented. The buffer layer 5 remaining at the bottom of the via hole 4 may be etched as shown in FIG. 1D using the etched upper layer 2 as a mask after forming the taper.

[Action]

As described above, in the present invention, the step of forming a connecting hole in the upper layer made of an insulating material formed on the underlayer, and forming the inorganic material layer on the upper layer in which the hole is formed. In the method for manufacturing a semiconductor device, which comprises at least the step of dry-etching the inorganic material layer, when the inorganic material layer on the underlayer is etched, a buffer layer is formed on the underlayer, and the etching is performed. Even if the underlayer is made of a material that can cause a sputter phenomenon due to etching, at least the buffer layer formed at the bottom of the hole suppresses the sputter phenomenon of the underlayer, thereby spattering the underlayer material and accompanying it. The redeposition phenomenon can be prevented. Moreover, since the buffer layer is etched using the dry-etched upper layer as a mask, holes can be easily formed in the buffer layer as it is,
The above action can be obtained simply and efficiently.

〔Example〕

Examples of the present invention will be described below. However, as a matter of course, the present invention is not limited to the following examples.

 FIG. 1 shows a first embodiment of the present invention.

In this embodiment, P-Si is used as the interlayer insulating film on Al which is the underlayer 1.
adopted _x N _y / SiO ₂ of a two-layer structure, after anisotropically selectively etched P-Si _x N _y, by the lower layer of SiO ₂ is etched away, to prevent re-deposition of Al during overetching It is a thing. That is, in the present embodiment, the underlayer 1 made of a material that can cause a sputtering phenomenon by etching is
The upper inorganic material layer 2 to be etched, which is an Al layer and is formed on the underlayer 1, is made of silicon nitride (especially P-Si).
_x N _{y, that} is, plasma Si _x N _y ) is an interlayer insulating film, and as a buffer layer 5 when etching the upper layer 2,
The SiO ₂ layer is used to form a two-layer structure of P-Si _x N _y / SiO ₂ to prevent redeposition of Al as the underlayer 1.

In this embodiment, the inorganic material layer 2 formed on the underlayer 1
(Here, a layer made of silicon nitride) is dry-etched to form a tapered hole 4 whose upper surface is widened (in this case, a via hole for connecting the lower Al wiring which is the underlayer 1 and the upper wiring). ), The underlayer 1 is made of a material (here, Al) which can cause a spattering phenomenon by dry etching.
When the layer 2 on the base layer 1 is dry-etched,
A buffer layer 5 (here, a SiO ₂ layer) made of a material having high etching resistance against the dry etching is formed on the underlying layer 1.
And dry etching (FIGS. 1 (a) and 1 (b)),
Further, the buffer layer 5 is etched by using the dry-etched upper inorganic material layer 2 as a mask (FIG. 1).
(D)).

More specifically, in this embodiment, as shown in FIG. 1 (a), first, a buffer layer 5 made of several hundred liters of SiO ₂ is formed on an underlayer 1 made of Al, and P-Si is used as an interlayer insulating film. Form _x N _y layers. As described above, the P-Si _x N _y interlayer insulating film is the upper inorganic material layer 2 to be etched which is itself etched and patterned. Further, as shown in the drawing, the via hole 4 is patterned with the photoresist 3 (indicated by PR in the drawing).

Then, P-Si _x N _y as the upper layer 2 is subjected to RIE while maintaining a selection ratio with respect to SiO _{2 of the} buffer layer 5. This makes the first
The structure of FIG. (B) is obtained.

Next, taper processing is performed so that the shape as shown in FIG. That is, in order to round the shoulder portion, O ₂ or CO ₂ is added to the etching gas, the photoresist 3 is retracted, and taper etching is performed. At that time, the underlying buffer layer 5
Since a selection ratio can be obtained with respect to (SiO ₂ ), this SiO ₂ acts as a layer exhibiting a buffering action, and no deposition occurs from the underlayer 1, Al. Anisotropy etching and taper processing are indispensable in order to round off only the shoulder part by taper etching with photoresist.However, in the conventional method, the underlying layer is overetched and re-deposition is avoided. I was not able to
When the present invention is applied, re-deposition can be prevented, and thus taper processing can be effectively used.

In this case, as the etching gas for obtaining the selection ratio of silicon oxide and silicon nitride,
An etching gas containing a gas having at least carbon and fluorine as constituent elements, which has a small fluorine / carbon ratio and is excessively mixed with CO ₂ , can be preferably used. The etching gas will be described later.

Regarding the structure of FIG. 1 (c) thus obtained, the upper inorganic material layer 2 in which SiO _{2 of the} buffer layer 5 is etched
Is used as a mask and is removed by an appropriate means such as RIE or solution etching to obtain the structure of FIG. 1 (d).

Next, a gas that can be suitably used for etching in the above-mentioned example, that is, containing a gas having at least carbon and fluorine as constituent elements, and a gas having a small F / C ratio, is formed by excessively mixing CO _2. The etching gas will be described.
As a gas with a small F / C ratio, F / C is 4: 1 like CF ₄ and CHF _3.
For example, the F / C ratio becomes 2: 1 such as CH ₂ F ₂ and CH ₃ F, whereas the F / C ratio becomes large due to the fluorine richness like 3: 1 and 3: 1.
A small F / C ratio such as or 1: 1 can be used. Further, CO ₂ may be mixed in such an amount that the generation of CF ₃ ⁺ (acting as an SiO ₂ etchant) due to recombination of F ^* can be suppressed by removing the fluorine radical F ^* as COF.

For example, a preferable etching gas is CH ₂ F ₂ and C.
A mixture of O ₂ in a flow rate ratio of 30 to 70% can be used. (However, the flow rate is not limited to this, and may be set appropriately depending on the device and conditions). Such etching gas is SiO
_It can be used effectively when selectively etching silicon nitride on ₂ (or other silicon oxide). For example, this can be preferably used for a layer in which Si ₃ N ₄ is provided on SiO _{2 as in the} above example. That is,
CO ₂ is mixed with a gas with a small F / C ratio to produce F ^*
If the generation of CF ₃ ⁺ due to the recombination of F ^* is suppressed by removing as SiO ₂ , the etching rate of SiO ₂ which is easily etched by CF ₃ ⁺ is reduced, while Si ₃ N ₄ is
Since the ions and radicals other than F ₃ ⁺ sufficiently promote etching, Si ₃ N ₄ has a higher selection ratio of / SiO ₂ , and the selective etching is effectively achieved.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the present invention is applied in order to prevent the spattering of the underlayer when the etching is performed to form the sidewall spacer for buffering the stepped shape of the via hole.

In this embodiment, the material is made of a material (here, made of Al) in which the sputtering phenomenon can occur by dry etching, and the inorganic material layer (here, P-silicon nitride layer 6) formed on the underlayer is formed. When a semiconductor device is manufactured by forming a tapered hole in which the upper surface of the opening is widened (specifically, it is obtained by forming the sidewall spacer 7) by dry etching this layer as an etching target layer When the inorganic material layer 6 on the underlayer 1 is dry-etched, a buffer layer 5b made of a material having a high etching resistance against the dry etching is formed on the underlayer, and the dry etching is performed. The buffer layer 5b is etched using the etched upper layer 7 (sidewall spacer) as a mask.

In this embodiment, first, an upper layer 21 (made of SiO ₂ ) 12 RIE on the underlayer 1 made of Al is used to open a window to obtain a via hole 4. In this embodiment, a buffer layer is formed by a silica film having a good covering property. To form. Specifically, SOG (Tokyo Ohka Co., Ltd.)
Made, product name. Plasma SiO _{2 (} a type of plasma SiO ₂ ) is used and coated for several hundred liters to obtain the structure shown in FIG. 2 (b). On both sides
The buffer layers on SiO ₂ are indicated by 5a and 5c, and the buffer layer on the underlayer 1 formed at the bottom of the via hole 4 is indicated by 5b. Next, plasma Si _x N _y is subjected to CVD to form the structure shown in FIG. This P-Si _x N _y is a layer to be etched 6 (spacer forming layer) for forming a sidewall spacer. That is,
From the state shown in FIG. 2 (c), the layer to be etched 6 (spacer forming layer) made of P-Si _x N _y is selected by RIE with the underlying buffer layer 5 (SOG), The entire surface is etched back to form sidewall spacers 7 on the sidewalls of the via hole 4 to taper the via hole shape.
As a result, the structure shown in FIG. 2 (d) is obtained. At this time, the buffer layer 5b (buffer SiO ₂ layer) formed by the underlying SOG
However, since the Al surface of the underlayer 1 is protected from over-etching when the sidewall 7 is formed, there is no concern that redeposited material of Al will adhere to the sidewall of the via hole 4.

Then, the SOG forming the buffer layers 5a to 5c is removed by RIE, solution etching or other appropriate means by using the sidewall spacers 7 formed by the dry etching as a mask to form a structure as shown in FIG. 2 (e). In the figure, the buffer layers 5a and 5c are removed by this, but the portion of the buffer layer 5b located below the inner sidewall spacer 7 remains.

According to the above-mentioned embodiment, the dry etching for taper processing of the via hole of the upper layer 2 (interlayer insulating film, etc.) laminated on the Al as the underlying layer 1 causes re-deposition by overetching the underlying Al. You can do it without This is achieved by the fact that the SiO ₂ film forming the base of the upper layer 2 serves as the buffer layer 5b and exhibits a buffer function for preventing redeposition of Al. In addition, in the present embodiment, this is effectively achieved by adopting the high selective etching of SiN / SiO ₂ (silicon nitride and silicon oxide) using the above-described etching gas or the like.

〔The invention's effect〕

As described above, according to the present invention, even when etching a layer formed on an underlayer made of a material that may cause a sputtering phenomenon by etching, re-deposition (re-deposition) of the material does not occur, The effect is great in the case of taper processing (contact hole, beer hole, etc.).

[Brief description of drawings]

1 and 2 show the respective steps of the first and second embodiments of the present invention. 1 ... Base layer (Al layer), 2 ... Upper inorganic material layer (interlayer insulating film to be etched), 3 ... Photoresist, 4 ...
(Beer) hole, 5, 5a to 5c ... Buffer layer, 6 ... Inorganic material layer to be etched (sidewall spacer forming layer),
7 ... Sidewall spacer.

Claims (1)

[Claims] 1. A step of forming a connecting hole in an upper layer made of an insulating material formed on an underlayer, and the upper layer or an inorganic material formed on the upper layer after the hole is formed. In a method for manufacturing a semiconductor device, which comprises at least a step of dry-etching a layer, the underlayer is made of a material capable of causing a spattering phenomenon by dry etching, and a connection layer formed on an upper layer above the underlayer. A buffer layer made of a material having a high etching resistance against the dry etching is formed at least at the bottom of the hole, the dry etching is performed, and the buffer layer is further etched using the dry-etched layer as a mask. , Method for manufacturing semiconductor device.