JPH0821677B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0821677B2 JPH0821677B2 JP63308279A JP30827988A JPH0821677B2 JP H0821677 B2 JPH0821677 B2 JP H0821677B2 JP 63308279 A JP63308279 A JP 63308279A JP 30827988 A JP30827988 A JP 30827988A JP H0821677 B2 JPH0821677 B2 JP H0821677B2
- Authority
- JP
- Japan
- Prior art keywords
- detection
- output
- latch means
- test mode
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、通常の使用モードの動作とは異なるテス
トモード動作を有する半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a test mode operation different from a normal operation mode operation.
この発明は、テストモード動作を行うことができる半
導体集積回路装置において、少なくとも、電源電圧より
高い電圧入力の検出手段と、検出出力のラッチ手段と、
不検出出力のラッチ手段とからなる構成とすることによ
り、ノイズ等により誤ってテストモード動作を起こすこ
とを防止するようにしたものである。The present invention provides, in a semiconductor integrated circuit device capable of performing a test mode operation, at least a detecting means for inputting a voltage higher than a power supply voltage, a latching means for detecting output,
The configuration including the non-detection output latch means prevents the test mode operation from being accidentally caused by noise or the like.
テストモード動作を行うことができる半導体集積回路
装置では、従来、通常モード動作を行わせるのと同じ入
力端子１を用いてテストモード動作を行えるようにする
ために、第２図に示すように電源電圧より高い電圧の入
力を検出する検出手段２と、前記検出手段２の出力が入
力される検出ラッチ手段３とからなる構成のものが知ら
れていた。In a semiconductor integrated circuit device capable of performing a test mode operation, in order to perform a test mode operation using the same input terminal 1 that is conventionally used for performing a normal mode operation, a power supply as shown in FIG. There has been known a structure including a detection means 2 for detecting an input of a voltage higher than a voltage and a detection latch means 3 for receiving an output of the detection means 2.
しかし従来の技術では、ノイズ等で簡単にテストモー
ドに入ってしまったり、一旦テストモードに入ってしま
うと解除用の信号を新たに入力しない限り、通常モード
に戻れなくなってしまい、そのまま使用すると誤動作を
引き起こすという欠点があった。この発明は、従来のこ
のような欠点を解決する為に成されたもので、ノイズ等
では簡単にはテストモードに入りにくく、さらに一旦テ
ストモードに入っても簡単に解除できるようなテストモ
ードの設定機能を持った半導体集積回路装置を得ること
を目的としている。However, with the conventional technology, if you easily enter the test mode due to noise etc. There was a drawback that caused. The present invention has been made to solve the above-mentioned drawbacks of the related art, and it is difficult to easily enter the test mode due to noise or the like, and it is possible to easily cancel the test mode once the test mode is entered. The purpose is to obtain a semiconductor integrated circuit device having a setting function.
上記課題を解決する為に、この発明は、少なくとも、
電源電圧より高い電圧入力を検出する検出手段と、前記
検出手段の検出出力が入力に接続される検出ラッチ手段
と、前記検出手段の不検出出力が入力に接続されるとと
もに前記検出ラッチ手段のリセット入力に出力が接続さ
れる不検出ラッチ手段とからなる構成とし、ノイズ等で
はテストモードへ入りにくくし、さらに一旦テストモー
ドへ入っても解除が容易になるようにした。In order to solve the above problems, the present invention, at least,
Detection means for detecting a voltage input higher than the power supply voltage, detection latch means for connecting the detection output of the detection means to the input, and non-detection output of the detection means for resetting the detection latch means while being connected to the input The configuration is made up of non-detection latch means in which the output is connected to the input, so that it is difficult to enter the test mode due to noise and the like, and even if the test mode is entered once, it is easily released.
上記のように構成された半導体集積回路装置におい
て、前記検出手段に電源電圧より高い電圧が入力される
と出力に検出信号が表われる。前記検出ラッチ手段は前
記検出信号によってセットされ、前記検出ラッチ手段の
出力はテストモード動作を可能にする信号を出力する。
しかし、一度でも前記検出手段より不検出信号が出力さ
れると前記不検出ラッチ手段がセットされ、前記不検出
ラッチ手段の出力は前記検出ラッチ手段をリセットし、
前記検出ラッチ手段の出力はテストモード動作を解除す
る。In the semiconductor integrated circuit device configured as described above, when a voltage higher than the power supply voltage is input to the detection means, a detection signal appears at the output. The detection latch means is set by the detection signal, and the output of the detection latch means outputs a signal enabling the test mode operation.
However, even if the non-detection signal is output from the detection means even once, the non-detection latch means is set, and the output of the non-detection latch means resets the detection latch means,
The output of the detection latch means releases the test mode operation.
以下にこの発明を図面に基づいて説明する。 The present invention will be described below with reference to the drawings.
第１図は、この発明の実施例を示すものである。入力
端子１に入力された電源電圧より高い電圧入力を検出す
る検出手段２の検出出力端子2aから出力される検出信号
は検出ラッチ手段３のセット入力端子3aに入力される。
また前記検出手段２の不検出出力端子2bから出力される
不検出信号は、不検出ラッチ手段４のセット入力端子4a
に入力される。前記不検出ラッチ手段４の出力は前記検
出ラッチ手段３のリセット入力端子3bに入力され、前記
不検出ラッチ手段４のリセット入力端子4bにはこのシス
テムのリセット信号が入力される。FIG. 1 shows an embodiment of the present invention. The detection signal output from the detection output terminal 2a of the detection means 2 for detecting a voltage input higher than the power supply voltage input to the input terminal 1 is input to the set input terminal 3a of the detection latch means 3.
The non-detection signal output from the non-detection output terminal 2b of the detection means 2 is the set input terminal 4a of the non-detection latch means 4.
Is input to The output of the non-detection latch means 4 is input to the reset input terminal 3b of the detection latch means 3, and the reset signal of this system is input to the reset input terminal 4b of the non-detection latch means 4.
なお、検出ラッチ手段３の出力端子3cからはテストモ
ード信号が出力される。A test mode signal is output from the output terminal 3c of the detection latch means 3.
上記のごとく構成されたシステムにおいて、まず、テ
ストモード動作を行わせるために、前記入力端子１に、
電源電圧より高い電圧を与えると、前記検出手段２は、
検出出力端子2aから検出信号を出力しこれを前記検出ラ
ッチ手段３がラッチして前記検出ラッチ手段３の出力端
子3cにテストモード信号を出力する。この後、もし前記
入力端子１に電源電圧より高い電圧が与えらえず、前記
検出手段２が高い電圧の検出を行わないと、前記検出手
段２は不検出出力端子2bから不検出信号を出力し、これ
を前記不検出ラッチ手段４がラッチする。前記不検出ラ
ッチ手段４の出力は、前記検出ラッチ手段３のリセット
入力端子3bに入力されるので前記検出ラッチ手段３はリ
セットされ、出力端子3cからの前記テストモード信号は
出力されなくなる。この後、再び前記入力端子１に電源
電圧より高い電圧が与えられても前記不検出ラッチ手段
４はリセット入力端子4bに前記システムのリセット信号
が入力されるまでリセットされないので、前記検出ラッ
チ手段３のリセット入力は解除されず、出力端子3cから
の前記テストモード信号は出力されない。従って、ノイ
ズ等でテストモードに入ったままになることは非常に起
こりにくくノイズ等ですぐに解除され、前記システムの
リセット入力が入るまで再びテストモードに入る心配は
ない。また、たとえテストモードに入ってしまった場合
でも、前記入力端子１に通常動作のモードの入力を与え
ると、不検出出力端子2bから前記不検出信号が出力さ
れ、テストモードは解除され誤動作は発生しない。In the system configured as described above, first, in order to perform the test mode operation, the input terminal 1 is
When a voltage higher than the power supply voltage is applied, the detection means 2
A detection signal is output from the detection output terminal 2a, which is latched by the detection latch means 3 to output a test mode signal to the output terminal 3c of the detection latch means 3. After this, if a voltage higher than the power supply voltage is not applied to the input terminal 1 and the detection means 2 does not detect a high voltage, the detection means 2 outputs a non-detection signal from the non-detection output terminal 2b. Then, the non-detection latch means 4 latches this. Since the output of the non-detection latch means 4 is input to the reset input terminal 3b of the detection latch means 3, the detection latch means 3 is reset and the test mode signal is not output from the output terminal 3c. After this, even if a voltage higher than the power supply voltage is applied to the input terminal 1 again, the non-detection latch means 4 is not reset until the reset signal of the system is input to the reset input terminal 4b. Is not released, and the test mode signal from the output terminal 3c is not output. Therefore, it is extremely unlikely that the test mode is kept in the test mode due to noise or the like, and the test mode is canceled immediately due to noise or the like, and there is no fear of entering the test mode again until the reset input of the system is input. Further, even if the test mode is entered, if the input in the normal operation mode is applied to the input terminal 1, the non-detection signal is output from the non-detection output terminal 2b, the test mode is released and the malfunction occurs. do not do.
以上説明したように、この発明はテストモード動作を
行うことができる半導体集積回路装置において、ノイズ
やCPUの暴走等によって簡単にテストモード動作を起こ
すことを防止するとともに、もし万が一テストモードに
入ってしまったとしても通常モードの動作を行うことで
簡単にテストモードを解除することができるような極め
て誤動作の少ないテストモードの設定機能を持った半導
体集積回路装置を得ることができる。As described above, the present invention, in a semiconductor integrated circuit device capable of performing the test mode operation, prevents the test mode operation from being easily caused by noise, CPU runaway, or the like. Even if it happens, it is possible to obtain a semiconductor integrated circuit device having a test mode setting function with extremely few malfunctions in which the test mode can be easily released by performing the normal mode operation.
また、上記検出ラッチ手段や上記不検出ラッチ手段に
おいて、同期型のラッチ回路や、フリップフロップ回路
を用いて、同期信号に同期させたりさらに、上記検出手
段においても、上記検出信号出力や上記不検出信号出力
を同期信号に同期させても効果は変わりないだけでな
く、システム全体の設計もし易くなることは言うまでも
ない。Further, in the detection latch means or the non-detection latch means, a synchronous latch circuit or a flip-flop circuit is used to synchronize with the synchronization signal, and the detection means also outputs the detection signal or the non-detection signal. It goes without saying that synchronizing the signal output with the synchronizing signal does not change the effect but also facilitates the design of the entire system.
第１図はこの発明に係るテストモードの設定機能を持っ
た半導体集積回路装置のブロック図、第２図は従来のテ
ストモード機能を持った半導体集積回路装置のブロック
図である。 １……入力端子 ２……検出手段 ３……検出ラッチ手段 ４……不検出ラッチ手段FIG. 1 is a block diagram of a semiconductor integrated circuit device having a test mode setting function according to the present invention, and FIG. 2 is a block diagram of a conventional semiconductor integrated circuit device having a test mode function. 1 ... Input terminal 2 ... Detection means 3 ... Detection latch means 4 ... Non-detection latch means
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/822
Claims (1)
い値電圧と比較し検出出力信号及び不検出出力信号を出
力する検出手段と、該検出手段の不検出出力端子が不検
出ラッチ手段のセット入力端子に接続され、前記不検出
出力信号を入力、ラッチし、第一の出力信号を出力する
不検出ラッチ手段と、該不検出ラッチ手段の出力端子が
検出ラッチ手段のリセット入力端子に、前記検出手段の
検出出力端子が検出ラッチ手段のセット入力端子にそれ
ぞれ接続され、前記検出出力信号及び前記第一の出力信
号を入力、ラッチする検出ラッチ手段を有する半導体集
積回路装置。1. A set of at least a detection means for comparing an input voltage with a preset threshold voltage to output a detection output signal and a non-detection output signal, and a non-detection output terminal of the detection means. A non-detection latch means connected to an input terminal for inputting and latching the non-detection output signal and outputting a first output signal; and an output terminal of the non-detection latch means for a reset input terminal of the detection latch means, A semiconductor integrated circuit device having a detection latch means for inputting and latching the detection output signal and the first output signal, the detection output terminals of the detection means being respectively connected to the set input terminals of the detection latch means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308279A JPH0821677B2 (en) | 1988-12-06 | 1988-12-06 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308279A JPH0821677B2 (en) | 1988-12-06 | 1988-12-06 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02154459A JPH02154459A (en) | 1990-06-13 |
| JPH0821677B2 true JPH0821677B2 (en) | 1996-03-04 |
Family
ID=17979120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63308279A Expired - Lifetime JPH0821677B2 (en) | 1988-12-06 | 1988-12-06 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821677B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0827333B2 (en) * | 1989-03-20 | 1996-03-21 | 富士通株式会社 | Semiconductor integrated circuit |
-
1988
- 1988-12-06 JP JP63308279A patent/JPH0821677B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02154459A (en) | 1990-06-13 |
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