JPH0821714B2 - Insulated gate field effect transistor - Google Patents

Description

The present invention relates to a high breakdown voltage structure of a multi-cell type insulated gate field effect transistor.

[Conventional technology]

Insulated gate field effect transistors for electric power are used in a wide range of fields such as high frequency switching power supplies. As shown in FIG. 5, a conventional field effect transistor of this type has a drain region 1 consisting of an n ^{+ type} region 1a as a starting base material and an n type region 1b formed by epitaxial growth on its upper surface, Bulk region 2 comprising a p-type region surrounded by an n-type region and having a portion exposed on the surface of the shape region 2
A source region 3 formed of an annular n ^{+ -type} region surrounded by the bulk region 2 and having a portion exposed on the surface of the bulk region 2, and a source region 3 formed on the surface side of the bulk region 2 via an insulating film 4. A gate electrode 5, a source electrode (first main electrode) 6 in contact with the bulk region 2 and the source region 3, and a drain electrode (second main electrode) 7 in contact with the drain region 1. The gate electrode 5 and the source electrode 6 are formed of an insulating film 10
It is electrically insulated through. In the field effect transistor configured as described above, a voltage between the source electrode 6 and the drain electrode 7 with the drain electrode 7 side being positive is provided.
When V _DS is applied and a positive on-voltage is applied to the gate electrode 5 with respect to the source electrode 6, the bulk region 6 under the gate electrode 5 is inverted into an n-type to form a channel, and the drain region 1 A drain current I _D mainly flows in the vertical direction to the source region 3. Here, when the voltage V _DS increases, the depletion layer 8 expands as schematically shown in FIG. Depletion layer 8 supports this voltage until breakdown occurs. The depletion layer 8 is formed in the drain region 1 and the cell region 9
The depletion layer extending from the pn junction with the (bulk region 2) and the depletion layer extending under the gate electrode due to the electric field effect of the gate electrode 5 are integrated.

[Problems to be Solved by the Invention]

As shown in FIG. 6, in the field effect transistor of FIG. 5, a large number of island-shaped regions (hereinafter, referred to as cell regions) 9 including a source region 3 and a bulk region 2 surrounding the source region 3 are formed in the drain region 1. It is used as a multi-cell type field effect transistor. As is well known, even if the four corners of the cell region 9 are rounded as shown in the figure, the electric field concentration is more likely to occur as compared with the straight side portions. Therefore, it is disadvantageous in achieving high breakdown voltage.

Therefore, it is an object of the present invention to provide a multi-cell type insulated gate field effect transistor having a low on-resistance and a high breakdown voltage.

[Means for Solving the Problems] The present invention for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. The bulk region 2 and a source region formed in the bulk region 2 will be described below. In a multi-cell type insulated gate field effect transistor in which a plurality of cell regions 9 composed of 3 are arranged in the drain region 1 in an island shape, the plurality of cell regions are the first cell region and the first cell region. A plurality of second cell regions that are arranged around the first cell region at equal intervals with respect to the region, and the planar shapes of the first and second cell regions are substantially positive. Each of the second cell regions is a quadrangle or a substantially regular hexagon, and each of the second cell regions is arranged on an extension line of a plurality of virtual straight lines that connect a plurality of corner portions of the first cell region that face each other. The center and corner of the cell area The distance between the corner of the first cell region and the corner of the second cell region adjacent to the corner of the first cell region, which is located on the extension line of the virtual straight line, is the same as the side of the first cell region. Is set smaller than the distance between the sides of the second cell region adjacent to each other, and the drain region 1 has a high impurity concentration in the first region (for example,
n ^{+ -type} region) 1a, a second region (for example, n-type region) 1b having an impurity concentration lower than that of the first region 1a, and the second region 1b
Third region with a higher impurity concentration than that (eg n ^{+ type} region)
1c, the drain electrode 7 is connected to the first region 1a, the second region 1b is adjacent to the first region 1a, and the bulk region 2 and the first region 1a. And is formed by epitaxial growth.
The region 1c is related to the insulated gate field effect transistor, which is arranged between the first cell region and the second cell region facing each other.

[Operation and Effect of the Invention] In the insulated gate field effect transistor of the present invention, the first
Since the high impurity concentration region 1c is formed above the drain region between the cell region and the second cell region facing each other, the on-resistance is reduced. When the third region having a high impurity concentration is formed above the drain region as described above, the breakdown voltage of the corner portion of the cell region tends to be low. However, in the present invention, the pair of corner portions of the first cell region facing each other are formed. The center of the second cell region and the pair of corners are arranged on the extension of the connecting virtual straight line, and the distance between the corners of the first and second cell regions is smaller than the distance between the sides. Since it is set, the drain region between the corners of the first and second cell regions is filled with the depletion layer prior to the drain region between the sides. For this reason, the breakdown voltage at the corners of the first and second cell regions where electric field concentration is likely to occur increases and the breakdown voltage is suppressed from decreasing. In addition, since the distance between the sides of the first and second cell regions is larger than the distance between the corners, there is a relatively large drain region between the sides, which is the drain current. Effectively works as a passage.
As a result, it is possible to provide an insulated gate field effect transistor having a low on-resistance and a high breakdown voltage.

[Embodiment] An insulated gate field effect transistor according to an embodiment of the present invention will be described with reference to FIGS. The first
In FIGS. 3 to 3, parts that are substantially the same as those in FIGS. 5 and 6 are given the same reference numerals, and description thereof will be omitted.

The insulated gate field effect transistor of this embodiment is a multi-cell type insulated gate field effect in which a cell region 9 composed of a source region 3 and a bulk region 2 surrounding the source region 3 is scattered in an island shape in a drain region 1 as in the conventional example. It is a transistor. The source region 3 is formed in a ring shape in the bulk region 2, and the bulk region 2 penetrates into the hole inside the source region 3. As shown in FIG. 1, the cell region 9 has a planar shape of a substantially square shape, and has four corner portions and four substantially linear side portions formed between the corner portions. There is. The corners are rounded in an arc shape so as to alleviate the electric field concentration as in the conventional example.

The difference of this embodiment from the conventional example is the planar arrangement of the cell region 9 described above. That is, a certain cell region (hereinafter, referred to as the first
4 cell regions (hereinafter referred to as second cell regions) 9 which are different from each other at the four corners of the cell region 9).
Are placed close together. Further, the first cell region 9 and the second cell region 9 face each other at their corners,
The distance between the first cell region 9 and the second cell region 9 is small at the corners and large at the sides. The four second cell regions 9 are arranged at substantially equal intervals with respect to the first cell region 9. Each of the above-mentioned four second cell regions 9 is itself also the first cell region, and four cell regions 9 including the above-mentioned first cell region 9 are provided as the second cell regions at the respective four corners. The corners of the cell region 9 are arranged close to each other.

The drain region 1 includes an n ^{+ -type} first region 1a having a relatively high impurity concentration, to which the drain electrode 7 is connected, and the first region 1a.
N-type second region 1b having a lower impurity concentration than the first region 1a
And an n ^{+ type} third region 1c having an impurity concentration higher than that of the second region 1b. The second region 1b is a region formed by epitaxial growth on the first region 1a similarly to FIG. 5, and is arranged below the p-type bulk region 2 and the third region 1c. The third region 1c is arranged between the cell regions 9 facing each other, and is formed at the uppermost part of the drain region 1. this
Since the n ^{+ -type} third region 1c is arranged in the drain current path, it has the effect of lowering the on-resistance. If the third region 1c having a high impurity concentration is provided, the angular breakdown voltage of the cell region 9 tends to be low, but in this embodiment, the arrangement of the cell region 9 is changed to the arrangement shown in FIG. The decrease in breakdown voltage due to the third region 1c is suppressed. This makes it possible to provide a field effect transistor having high on-resistance.

In the field effect transistor of this embodiment, the source region 6
When a drain-source voltage V _DS having a positive polarity on the drain electrode 7 side is applied between the drain electrode 7 and the drain electrode 7, the depletion layer 8 shown in FIG. 2 expands as in the field effect transistor of the conventional example. The spread of the depletion layer 8 increases as the drain-source voltage V _DS increases. In this embodiment, the drain-source voltage V _DS is increased and the reverse breakdown voltage of the pn junction formed by the cell region 9 and the drain region 1 is increased.
When a predetermined voltage V _DS1 smaller than V _B (value when the distance between the cell regions 9 is sufficiently large) is reached, as shown schematically in FIG. 3, the first cell region 9 and the second cell region 9 The first cell region 9 and the second cell region 9 are formed so that a depletion layer 8 that can be regarded as deeply entangled with the depletion layer extending laterally from the pn junction is formed at a corner portion where the distance between 9 is small. The interval between and is determined to be relatively small. First cell area 9
In the side portion where the distance between the second cell region 9 and the second cell region 9 is large, the depletion layer extending laterally from the pn junction is not entangled or entangled when the voltage V _{DS1 is} applied, as shown in FIG. Even if it does, a relatively shallow depletion layer 8 is formed.
As described above, in the field effect transistor of this embodiment,
When the drain-source voltage V _DS is increased, before the breakdown occurs, the drain region 1 at the portion where the corners of the cell region 9 face each other is smoothed continuously by the depletion layer 8 preceding other drain regions 1. It is filled. As a result, the breakdown voltage at the corner where electric field concentration is likely to occur is improved, and an insulated gate field effect transistor with a high breakdown voltage can be realized.
On the other hand, the spread of the depletion layer 8 at the corner when the reverse bias voltage V _DS1 is applied to the conventional insulated gate field effect transistor shown in FIG. 6 is, as schematically shown in FIG. Since the opposing distance between the corners of the cell region 9 is large, the depletion layer 8 is not smoothly continuous so that the electric field concentration can be effectively alleviated. Further, even in the conventional example, if the distance between the two opposing cell regions 9 is made small, it is possible to easily form the depletion layer for relaxing the electric field concentration in the regions where the corners face each other as in the present embodiment, and the breakdown voltage is increased. The effect of improvement is obtained as it is. However, in the structure of the conventional example, the on-resistance increases because the mutual spacing of the sides becomes too narrow. In this embodiment, since the mutual intervals of the corners are narrowed,
Although the on-resistance increases in this portion, the on-resistance decreases conversely because the mutual intervals of the sides increase. as a result,
The total on-resistance has a small value equivalent to that of the conventional insulated gate field effect transistor in the state where the distance between the cell regions is not narrowed.

It is possible to improve the breakdown voltage even with a structure other than that of this embodiment. For example, in the field effect transistor of this embodiment, it is conceivable to dispose the internal FLR formed of the p-type region instead of the first cell region 9. However, this structure reduces the active area of the field effect transistor on the chip. Further, in the field-effect transistor of the conventional example, it may be possible to improve the breakdown voltage by making the planar shape of the cell region 9 circular. However, in this structure, the channel width (peripheral length of the cell region 9) becomes small, and the current capacity cannot be made large. As described above, this example can be said to be the most suitable structure as a high breakdown voltage structure for an insulated gate field effect transistor.

 The effects of this embodiment are summarized as follows.

(1) The breakdown voltage at the corner, which is a weak point, is improved, and a high breakdown voltage insulated gate field effect transistor can be realized.

(2) An insulated gate field effect transistor having a relatively small on-resistance can be realized.

(3) An insulated gate field effect transistor with good area efficiency can be realized.

(Modification)

The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible, for example.

(1) The planar shape of the cell region 9 may be substantially hexagonal as shown in FIG.

(2) It is also effective for a well-known deep base insulated gate field effect transistor in which the bulk region 2 is partially deeply formed.

(3) The present invention is effective when the planar shape of the cell region is substantially quadrangular or hexagonal. For example, it is effective to make the corners of a quadrangle into an arc shape as in the embodiment or to form a tapered cell region. When the taper is formed, two adjacent cell regions are arranged so that the respective tapered portions face each other.

[Brief description of drawings]

1 is a plan view showing a part of the surface of a semiconductor substrate of an insulated gate field effect transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of a portion corresponding to line II-II in FIG. FIG. 3 is a sectional view of a portion corresponding to the line III-III in FIG. 1, FIG. 4 is a plan view showing a part of the surface of a semiconductor substrate of an insulated gate field effect transistor of a modification, and FIG. FIG. 6 is a cross-sectional view of a portion corresponding to line VV in FIG. 6 showing an insulated gate field effect transistor, and FIG. 6 is a plan view showing a part of the surface of a semiconductor substrate of a conventional insulated gate field effect transistor. 1 ... Semiconductor substrate, 2 ... Bulk region, 3 ... Source region, 9 ... Cell region.

Claims (1)

[Claims] 1. A bulk region (2) and this bulk region (2)
In a multi-cell type insulated gate field effect transistor, wherein a plurality of cell regions (9) formed of a source region (3) formed in the drain region (1) are arranged in an island shape in the drain region (1). The cell region has a first cell region and a plurality of second cell regions arranged around the first cell region at equal intervals with respect to the first cell region, The planar shape of the first and second cell regions is a substantially regular quadrangle or a substantially regular hexagon, and the first cell region has a plurality of imaginary straight lines extending from a plurality of imaginary straight lines that connect a pair of opposing corners of the first cell region. Each of two cell regions is arranged, a center and a corner portion of the second cell region are located on an extension line of the virtual straight line, and a corner portion of the first cell region and the second cell region adjacent to the corner portion. The distance between the corner of the cell region is the first Is set to be smaller than the distance between the side of the region and the side of the second cell region adjacent thereto, and the drain region (1) and the first region (1a) having a high impurity concentration A second region (1b) having an impurity concentration lower than that of the first region (1a) and a third region (1c) having an impurity concentration higher than that of the second region (1b), The drain electrode (7) is connected to the first region (1a), the second region (1b) is adjacent to the first region (1a), and the bulk region (2) and the first region (1a) are connected to each other. The third region (1c) is interposed between the region (1a) and formed by epitaxial growth, and the third region (1c) is disposed between the first cell region and the second cell region facing each other. Insulated gate field effect transistor.