JPH0821835B2 - Voltage controlled oscillator - Google Patents

Description

The present invention relates to a voltage controlled oscillator circuit, which makes it possible to control an oscillation frequency by controlling a charging current of a capacitor corresponding to an input voltage, and for example, a voltage controlled oscillator suitable for a skew detection IC or the like. Regarding the circuit.

FIG. 1 shows the system of the voltage controlled oscillator circuit incorporated in the skew detection IC. In the figure, the input voltage applied to the input terminal 2 is an error voltage for voltage control. This input voltage is input to the voltage controlled oscillator 4,
The voltage controlled oscillator 4 generates a sawtooth wave having a frequency corresponding to the input voltage. The sawtooth wave is formed by charging and discharging the capacitor 8 inserted between the output terminal 6 formed in the voltage controlled oscillator 4 and the reference potential point, and
After going through 10, the capacitor 14 connected to its external terminal 12
Is sampled and held. That is, the sample switch 10
And the sample hold circuit is composed of the sample capacitor 14 and the sample switch 10
It is switched by Ps, which charges and discharges the capacitor 14. The charging voltage of the capacitor 14 passes through the filter circuit 16, resulting in the formation of an error voltage, which is applied to the input terminal 2 of the voltage controlled oscillator 4. In this case, the filter circuit 16 uses a capacitor 18 and a resistor 20 connected in parallel, and a resistor 22 and a capacitor 24 connected in series between the output side of this parallel circuit and the reference potential point. .

FIG. 2 shows operation waveforms of this voltage controlled oscillator circuit. In the waveforms A and C, a indicates the sawtooth wave output from the voltage controlled oscillator 4, b indicates the error voltage, and waveforms B and D indicate the sampling pulse Ps given to the sample switch 10. Waveforms A and B have the same phase, while waveforms C and
In D, the phase shift occurs due to the relationship with the input sampling pulse, and the error voltage b changes stepwise. That is, the situation shows that the output frequency (cycle) is controlled based on the error voltage.

In order to improve the control accuracy of such a voltage controlled oscillator circuit, the lock range and center frequency can be set with high accuracy,
Moreover, it is essential that the settings be easy.

Therefore, it is an object of the present invention to provide a voltage controlled oscillator circuit that can set a lock range extremely easily and highly accurately with a simple circuit configuration and can easily set a center frequency and is suitable for use in an IC.

That is, the voltage controlled oscillator according to the present invention includes the first resistor (3
A first and a second transistor (28, 30) whose emitters are connected in common through (2, 34), an input voltage at the base of the first transistor and a sawtooth at the base of the second transistor. Voltage-current conversion circuit (27) that converts the input voltage into a current based on the magnitude relationship between the upper reference voltage and the lower reference voltage, which is an intermediate value between the upper reference voltage and the lower reference voltage. A third transistor (54) for receiving an input current at the collector is installed, the base is connected to the base-collector of the third transistor, and the second resistor (62) is connected to the emitter side of the third transistor (54). A fourth transistor (54) for drawing in a reference current corresponding to the current from the emitter side of the first and second transistors of the voltage-current conversion circuit is provided, and a base collector of the third transistor is provided. Connect the base to another, and,
A fifth transistor (5) having a third resistor (64) connected to the emitter side and drawing a reference current corresponding to the input current
8) is installed, and the fifth and fifth reference currents drawn into the fourth transistor by the first and second resistors are installed.
A constant current source (52) for setting a current ratio with the reference current drawn into the transistor of No. 6 and a sixth transistor (68) having a common base / collector connection are installed, and the voltage is provided on the base / collector side. The reference current is drawn by the fifth transistor together with the output current of the current conversion circuit, and a seventh transistor (70) having a common base with the sixth transistor is installed to install the voltage current conversion circuit. A current combining circuit (current mirror circuit 66) for extracting a combined current of the output current and the reference current drawn into the fifth transistor, and the combined current obtained by this current combining circuit are supplied, and the combined current is used. A capacitor (84) to be charged is installed and is connected in parallel to this capacitor to form a discharge circuit, and the seventh transistor of the current combining circuit is formed. The eighth transistor (80) connected in series to the transistor is installed, and the fourth, fifth, and sixth transistors are installed.
And a reference voltage setting circuit (94) for setting the upper limit reference voltage, the lower limit reference voltage, and the intermediate reference voltage with a series circuit of a seventh resistor (86, 88, 90, 92), and charging the capacitor. A first comparator (96) for comparing a voltage with the upper limit reference voltage is installed, and a second comparator (98) for comparing the charging voltage of the capacitor with the lower limit reference voltage is installed. A flip-flop circuit (10) that generates an output by using the output as a set input and the output of the second comparator as a reset input
0) is installed, the output of this flip-flop circuit is applied to the base of the eighth transistor, and when the charging voltage of the capacitor becomes equal to or higher than the upper limit reference voltage, the eighth transistor is turned on to discharge the capacitor. Let
When the charging voltage becomes lower than the lower limit reference voltage, the eighth
And a sawtooth wave oscillating circuit (78) that oscillates the sawtooth wave by charging the capacitor with the combined current of the current combining circuit by turning off the transistor.

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 3 shows an embodiment of the voltage controlled oscillator circuit of the present invention. In the figure, an input terminal 2 corresponds to the input terminal 2 of the voltage controlled oscillator circuit shown in FIG. 1, and an input voltage Vin such as the error voltage is applied. Voltage application terminal 26
Is applied with V _CC as a drive voltage. A voltage-current conversion circuit 27 that converts an input voltage Vin applied to the input terminal 2 into a current is installed in the voltage-controlled oscillation circuit. The voltage-current conversion circuit 27 includes first and second transistors 28, 30.
A differential amplifier 36 configured by commonly connecting the emitters of the transistors through the first resistors 32 and 34 is installed, and each of the transistors 2
Transistors 38 and 40 and resistors 42 and 44 are individually connected between the collectors of 8 and 30 and the voltage application terminal 26. The bases of the transistors 38 and 40 are commonly connected, and the emitter and base of the transistor 46 are connected between the base and the collector of the transistor 38.
The transistors 38, 40 and 46 form a current mirror circuit. The base of the transistor 30 is a bias voltage of 1/2 of the voltage of the voltage V _CC from the address circuit to be described later (V _CC / 2) are applied, as compared to the input voltage applied to the base of the transistor 28 Made of

An input current Iin is given to the current input terminal 48, and a constant current source 52 that sets the operating current of each circuit based on the input current Iin is installed. The constant current source 52 is a third transistor 54, a fourth transistor 56, a fifth transistor
58, a resistor 60, a second resistor 62 and a third resistor 64, the bases of the transistors 54, 56 and 58 are commonly connected, and the resistor 60 is placed between the emitter and the reference potential point. , 62, 64 are individually connected, and the base and collector of the transistor 54 are commonly connected. That is, the transistors 54, 56 and 58 form a current mirror circuit. A transistor 56 and a resistor 62 that form a constant current source 52 are connected between a common connection point of the resistors 32 and 34 of the voltage-current conversion circuit 27 and a reference potential point. Transistor 56
Further, assuming that the current set by the resistor 64 is a reference current and this reference current is I ₀ , the total motion difference current for the voltage-current conversion circuit 27 is set to I ₀ / n by the transistor 56 and the resistor 62. In this example, the current ratio 1 / n is equal to the resistances 62, 64.
It is set by the resistance ratio of.

The reference current I ₀ set by the transistor 58 and the resistor 64, together with the output current of the voltage-current conversion circuit 27, is a current mirror circuit installed as a current combining circuit.
Given to 66. The current mirror circuit 66 is installed to add or subtract the output current of the voltage-current conversion circuit 27 to the reference voltage I ₀ and synthesize the output current.
The transistor 68, the seventh transistor 70, the transistor 72, and the resistors 74 and 76.

The frequency control current formed via the current mirror circuit 66 provided as the current combining circuit is input to the sawtooth wave oscillation circuit 78. That is, the eighth transistor 80 as a switching element for forming a sawtooth wave is connected between the collector of the transistor 70 and the reference potential point, and the transistor 80 has an output terminal for generating a sawtooth wave. 82 is formed, and a capacitor 84 is connected between the output terminal 82 and the reference potential point. Also, a fourth circuit forming a series circuit between the voltage application terminal 26 and the reference potential point,
A reference voltage setting circuit 94 including fifth, sixth and seventh resistors 86, 88, 90, 92 is installed, and an upper limit is set at a connection point of the resistors 86, 88 depending on a resistance ratio of the resistors 86, 88, 90, 92. Voltage Vh is 3V _CC /
4, intermediate reference voltage Vn is V _CC / 2, resistance at the connection point of resistors 88 and 90
The lower reference voltage Vl is set to V _CC / 4 at the connection point of 90 and 92. The inverting input terminal (-) of the first comparator 96 for voltage comparison is connected to the connection point of the resistors 86 and 88, and
The non-inverting input terminal (+) of the second comparator 98 that performs voltage comparison is connected to the connection point of the resistors 90 and 92, and the non-inverting input terminal (+) of the comparator 96 and the inverting input terminal (-) of the comparator 98 are connected. Are commonly connected to the collectors of the transistors 80. The outputs of the comparators 96 and 98 are set input and reset input of the RS flip-flop circuit 100, and the output terminal 1 of the RS flip-flop circuit 100.
A flip-flop oscillation output is generated at 02. The base of the transistor 80 is connected to one output terminal of the RS flip-flop circuit 100. In this embodiment, the reference voltage setting circuit 94 also serves as the bias circuit of the voltage-current conversion circuit 27, the base of the transistor 30 is connected to the connection point of the resistors 88 and 90, and the base of the transistor 30 is compared. A voltage of V _CC / 2 is applied as the voltage.

The operation will be described based on the above configuration. Input terminal 48
When an operating current Iin is applied to the
A constant current I ₀ flows through 8, and I ₀ / n flows through the transistor 56. Here, when a voltage having the same value as the intermediate reference voltage Vn (= V _CC / 2) set by the reference voltage setting circuit 94 is applied to the input terminal 2, the output current of the voltage-current conversion circuit 27 becomes zero and the current mirror The transistor 68 in circuit 66 is a transistor
Only the reference current I ₀ flows from 58. This reference current I ₀ becomes the charging current Ic from the transistor 70 to the capacitor 84 due to the current mirror effect of the current mirror circuit 66,
The capacitor 84 is charged with the reference current I ₀ . The charging voltage of the capacitor 84 is applied to the non-inverting input terminal (+) of the comparator 96 and the inverting input terminal (−) of the comparator 98, and is set to the upper limit reference voltage Vh or the lower limit set by the reference voltage setting circuit 94. It is compared with the reference voltage Vl. That is, when the terminal voltage of the capacitor 84 exceeds the upper limit reference voltage Vh, the output of the comparator 96 is input to the set terminal of the RS flip-flop circuit 100 as a set input, and the output Q of the RS flip-flop circuit 100 becomes high level, The transistor 80 becomes conductive. As a result, the capacitor 84
Is placed in a discharged state via transistor 80. This discharging operation is performed instantaneously, and when the charging voltage of the capacitor 84 falls below the lower limit reference voltage Vl, the comparator 98 instantaneously generates an output, and this output becomes the reset input of the RS flip-flop circuit 100, and the RS flip-flop circuit Output Q of 100
Will be low level. As a result, the transistor 80 becomes non-conductive, the capacitor 84 enters the charged state, and the constant current is supplied via the transistor 70.

Such charging / discharging is instantaneously performed, and as a result of the capacitor 84 repeating charging / discharging, a sawtooth wave as shown in FIG. 4 is generated at the output terminal 82. This sawtooth output is output terminal 82
As described above, it is taken out from the input terminal and is used as the input of the sample switch 10 in FIG.

The generation frequency (cycle) T of this sawtooth wave is
Relating to the capacitance C of 84, the voltages Vh and Vl and the current I _C (= I ₀ ),
The cycle T in this case is the central cycle, and when this is T ₀ , it is given by T ₀ = C (Vh−Vl) / I ₀ (1). That is, it can be seen that this value becomes the central period of the sawtooth wave, and the change in the period is given by the change in the current I _C.

In addition, the voltage applied to the input terminal 2 is the transistor 30.
When the voltage is changed to be higher or lower than the voltage V _CC / 2 applied to the base of, the output current ± ΔI flows through the transistor 30 of the voltage-current conversion circuit based on the voltage comparison. That is, in this case, the current ± ΔI flows in the direction of the arrow a or the arrow b corresponding to the direction of the input change, and the current Ic flowing through the transistor 70 is the reference current Io having a constant value plus the variable current ± ΔI. The value is (Io ± ΔI). The capacitor 14 is filled based on this current, and the charging / discharging operation as described above is performed to form a sawtooth wave.

Further, in this voltage controlled oscillator circuit, since the active load composed of the current mirror circuit is used as the load of the differential amplifier 36, the current ΔI is equal to the current ± Io flowing through the transistor 56.
It is in the range of / n and exhibits a linear change within this range.
That is, the current ΔI is in the range of −Io / n ≦ ΔI ≦ Io / n (2).

Further, since the current Io and the current Ic flowing from the transistor 70 to the capacitor 84 are Ic≈Io + ΔIo, (n−1) Io / n ≦ Ic = Io + ΔI ≦ (n + 1) Io / n ...
(3) Therefore, the variable range of the cycle T is nTc / (n + 1) ≤Tc≤nTc / (n-1) (4) with respect to the central cycle Tc.

When the minimum period Tmin and the maximum period Tmax are calculated from the equations (1), (2) and (3), Tmin≈C (Vh−Vl) / Io {(n + 1) / n} (5) Tmax≈C (Vh-Vl) / Io {(n-1) / n} (6)

In such a cycle setting, the lock range is the current
The ratio of Io and ΔIc can be easily set by the resistance ratio of the resistors 62 and 64. In particular, the central period Tc causes the adjustment terminal 104 formed at the base of the transistor 38 of the differential amplifier 36 and the input terminal 2 to be in a short-circuited state, and the intermediate reference voltage Vn (=
It can be easily set by adjusting the input current Iin by applying V _CC / 2) to make the current ΔIo zero.

According to such a voltage controlled oscillator circuit, the lock range and the center frequency (cycle) can be selected as arbitrary values, and the values can be set with high accuracy. Especially, the adjustment of the center frequency is easy, and the circuit configuration is extremely simple.
It is suitable for IC conversion. Further, since the transistors 28 and 30 of the voltage-current conversion circuit 27 only allow a current amount that determines the lock range to flow, the base current is small and the input impedance can be made high.

Such a voltage controlled oscillator circuit is a 0.5H skew detection IC.
In PLL phase control, necessary characteristics such as a wide lock range and good low frequency characteristics can be satisfied.

As described above, according to the present invention, the center frequency, the maximum frequency deviation, and the frequency control sensitivity can be independently set with high accuracy, the lock range can be easily set, and the circuit configuration can be simplified. It can be configured as a circuit suitable for integration into an IC. For example, it can be used for a PLL circuit to set the center frequency and lock range arbitrarily and with high accuracy, and it is extremely easy to adjust the center frequency of the sawtooth wave. It can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control system of a voltage controlled oscillator circuit, FIG. 2 is an explanatory diagram showing its operation waveform, FIG. 3 is an explanatory diagram showing an embodiment of the voltage controlled oscillator circuit of the present invention, and FIG. FIG. 4 is an explanatory diagram showing its operation waveform. 27 ... voltage-current conversion circuit, 28 ... first transistor,
30 ... second transistor, 32, 34 ... first resistor, 48
...... Input terminal, 52 …… Constant current source, 54 …… Third transistor, 56 …… Fourth transistor, 58 …… Fifth transistor, 62 …… Second resistance, 64 …… Third transistor Resistance, 66 ……
Current mirror circuit (current synthesizing circuit), 68 ... sixth transistor, 70 ... seventh transistor, 78 ... sawtooth wave oscillation circuit, 80 ... eighth transistor, 84 ... capacitor, 86 ... Fourth resistor, 88 ... Fifth resistor, 90 ... Sixth resistor, 92 ... Seventh resistor, 94 ... Reference voltage setting circuit, 96 ... First comparator, 98 ... Second Comparator, 100 …… Flip-flop circuit, 104 …… Adjustment terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H03L 7/099 H04N 5/93 H03L 7/08 FZ

Claims (2)

[Claims] 1. A first and a second transistor whose emitters are commonly connected via a first resistor, wherein an input voltage is applied to the base of the first transistor and a sawtooth is applied to the base of the second transistor. Voltage-current conversion circuit that converts the input voltage into a current based on the magnitude relationship between the upper reference voltage and the lower reference voltage, which is an intermediate value between the upper reference voltage and the lower reference voltage, and a common base / collector input. A third transistor for receiving a current is installed, a base is connected to a base / collector of the third transistor, and a second resistor is connected to an emitter side so that a reference current corresponding to the input current is applied to the voltage. A fourth transistor that is drawn from the emitter side of the first and second transistors of the current conversion circuit is installed, and the base is connected to the base and collector of the third transistor. A fifth transistor connected to the third resistor is connected to the emitter side to pull in a reference current corresponding to the input current, and the fifth transistor is pulled in to the fourth transistor by the first and second resistors. A constant current source in which a current ratio between the reference current and the reference current drawn into the fifth transistor is set, and a sixth transistor in which a base and a collector are commonly connected are installed, and the sixth transistor is connected to the base and collector side. Along with the output current of the voltage-current conversion circuit, the reference current is drawn to the fifth transistor, and a seventh transistor having a common base with the sixth transistor is installed to output the voltage-current conversion circuit. A current combining circuit for taking out a combined current of the current and the reference current drawn into the fifth transistor; Synthetic current is supplied,
A capacitor charged by the combined current is installed, and an eighth transistor connected in parallel to the capacitor to form a discharge circuit and connected in series to the seventh transistor of the current combining circuit is installed, A reference voltage setting circuit for setting the upper limit reference voltage, the lower limit reference voltage and the intermediate reference voltage is installed by a series circuit of fourth, fifth, sixth and seventh resistors, and the charging voltage of the capacitor and the upper limit are set. A first comparator for comparing a reference voltage is installed, a second comparator for comparing a charging voltage of the capacitor and the lower limit reference voltage is installed, and an output of the first comparator is set as an input, the second comparator A flip-flop circuit that generates an output by using the output of the flip-flop as a reset input is installed. In addition to the base of the eighth transistor,
When the charging voltage of the capacitor becomes equal to or higher than the upper reference voltage, the eighth transistor is turned on to discharge the capacitor, and when the charging voltage becomes equal to or lower than the lower reference voltage, the eighth transistor is turned off. A sawtooth wave oscillator circuit that oscillates the sawtooth wave by charging the capacitor with the combined current of the current combiner circuit, and a voltage controlled oscillator circuit. 2. An adjusting terminal is provided on the base of the fifth transistor, and the adjusting terminal and the input terminal provided on the base of the fourth transistor are short-circuited to reduce the center frequency of the sawtooth wave. The voltage controlled oscillator circuit according to claim 1, wherein the voltage controlled oscillator circuit is set.