JPH0821836B2 - Voltage detection circuit - Google Patents

Description

The present invention relates to a voltage detection circuit for detecting fluctuations in voltage input to a microcomputer, for example.

[Conventional technology]

FIG. 3 shows a conventional voltage detecting circuit of this type disclosed in, for example, Japanese Patent Laid-Open No. 61-276413.

In FIG. 3, a first multi-collector pnp transistor (1) has an emitter at a high potential point (3) connected to a power supply (2) of voltage + Vcc, and a second collector (1b) and a base connected to a first npn transistor. Each is connected to the collector of (4). The second multi-collector pnp transistor (5) has its emitter connected to the high potential point (3), and its second collector (5b) and base connected to the collector of the second npn transistor (6), respectively. 1st multi-collector pnp
In this connection, the transistor (1) and the second multi-collector pnp transistor (5) respectively form a first current mirror circuit (30) and a second current mirror circuit (40), and their current mirror ratios are both It is 1: 1. The emitter area ratio of the first npn transistor (4) and the second npn transistor (6) is 1: n (n> 1), and both bases are connected to the signal input terminal (7). 2nd npn
The emitter of the transistor (6) is directly connected to the first connection point (9) via the first load (8), and the emitter of the first npn transistor (4) is directly connected to the first connection point (9). . A second load (11) is coupled between the first connection point (9) and the ground line (10) which is a low potential point.
The first collector (1a) of the first multi-collector pnp transistor (1) is connected to the second connection point (12). Second
The first collector (5a) of the multi-collector pnp transistor (5) is connected to the collector of the fourth npn transistor (13). The base and collector of the fourth npn transistor (13) are connected. 3rd npn transistor (1
The collector of 4) is the second connection point (12) and the base is the 4th npn
The bases of the transistors (13) are respectively connected, and the emitters of the fourth npn transistor (13) and the third npn transistor (14) are both connected to the ground line (10). The fourth npn transistor (13) and the third npn transistor (14) also form a third current mirror circuit (50), and the current mirror ratio thereof is 1: 1. Further, a constant current source (15) and a first line are connected between the high potential point (3) and the ground wire (10).
The 5npn transistor (16) is connected in series, the constant current source (15) and the collector of the fifth npn transistor (16) are connected at the third connection point (17), and the fifth npn transistor (16) is connected.
Has its emitter connected to the ground wire (10). The third connection point (17) is connected to the signal output terminal (19) via the inverter circuit (18).

 Next, the operation will be described.

When the collector currents I _C1 and I _{C2 of the} first npn transistor (4) and the second npn transistor (6) become equal due to the input signal voltage V _IN input to the signal input terminal (7), the input signal voltage is reduced. The threshold voltage is used. The threshold voltage V _S is Boltzmann's constant k, electronic charge q, absolute temperature T, base-emitter voltage V _BE2 of the second npn transistor (6), and resistance value of the first load (8). When R ₁ and the resistance value of the second load (11) are R ₂ ,
Given by the formula.

In the circuit configuration of FIG. 3, the current mirror ratio of the first current mirror circuit (30), the second current mirror circuit (40) and the third current mirror circuit (50) is 1: respectively.
Current I ₁ of the current I _C1 and the output stage of the input stage of since one first current mirror circuit (30), a second current mirror circuit (4
Input stage of the current I _C2 and the output stage of the current I ₂ 0), and a value equal to the third current mirror circuit (50 current I _C3 of the current I ₂ and the output stage of the input stage of the). That is, it is expressed by the second and third equations.

_{I C1 = I 1 ...... (2} ) I C2 = I 2 = I C3 ...... (3) the base current I _B of the 5npn transistor (16) I ₁ and the third current of the first current mirror circuit (30) It is the difference from I _C3 of the mirror circuit (50) and is shown by the fourth equation.

I _B = I ₁ −I _C3 (4) When the input voltage V _{IN of the} signal input terminal (7) is lower than V _S , input to the bases of the first npn transistor (4) and the second npn transistor (6). When a voltage is applied, first the charge easily flows to the emitter with the larger emitter area.
I _C1 <I _C2 , and I _B <0 from the second, third, and fourth equations. Therefore, the fifth npn transistor (16) is turned off,
The output voltage of the constant current source (15) becomes a power supply potential of approximately + _Vcc , a high potential level (hereinafter referred to as "H" level) is input to the inverter circuit (18), and a low potential level (from the signal output terminal (19) ( Hereinafter, "L" level) is output.

When V _IN is equal to V _S , I _C1 = I _C2 and I _B = 0 from the second, third, and fourth equations. Therefore, the fifth npn transistor (16) is turned off, and the “L” level is output from the signal output terminal (19) as in the case of V _IN <V _S.

When V _IN becomes higher than V _S , I _C1 > I _C2 . This is because the voltage from the base of the first npn transistor (4) to the first connection point (9) is equal to the voltage from the base of the second npn transistor (6) to the first connection point (9).
The base-emitter voltage V _BE1 of the pn transistor (4) is the base-emitter voltage V _BE of the second npn transistor (6).
_It becomes equal to the sum of the voltage across _BE2 and the first load (8). That is, since V _BE1 becomes larger than V _BE2 , the collector current I _C1 of the first npn transistor (4) becomes larger than I _{C2 of} the second npn transistor (6). As a result, I _B > 0 from the second, third, and fourth equations. Therefore,
The 5npn transistor (16) turns ON, the output potential of the constant current source (15) becomes the ground potential, the "L" level is input to the inverter circuit (18), and the "H" level is output from the signal output terminal (19). To be done.

[Problems to be Solved by the Invention]

Since the conventional voltage detection circuit is configured as described above, when reducing the power consumption of the detection circuit, when the current flowing through each branch of the circuit becomes a very small current, the bipolar transistor used in the circuit Since the current amplification factor h _FE decreases, the influence of the base current during current amplification increases, and as a result, it becomes difficult to balance the output current of the current mirror circuit and offset occurs, which causes voltage detection. The accuracy of is reduced. In order to prevent this, it is necessary to change from a bipolar transistor structure to a MOS field effect transistor (hereinafter referred to as MOST) structure. However, when the transistor that controls the input level to the inverter circuit is a bipolar transistor, the operation is started even with a small base current, so the response was extremely good, but when using MOST as the above transistor, turning MOST from ON to OFF At the time of switching, it is necessary to move the charge accumulated in the gate-source capacitance, but under a very small current, the environment for moving the charge is extremely bad. Therefore, the amount of accumulated charge to be moved is large with respect to the required voltage. When the number of calls is large, there is a problem that responsiveness deteriorates.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a voltage detection circuit with low current consumption, which has a good responsiveness to a change in an output signal when the input signal changes. I am trying.

[Means for solving the problem]

A constant current source in which a first potential point is connected to one terminal and a signal output terminal to which a signal is output is connected to the other terminal, and when the voltage value of the input signal is larger or smaller than a predetermined value. Current generating means for generating and outputting a current in the opposite direction, connected between the second potential point and the other terminal of the constant current source,
A field effect transistor having a control terminal to which a signal line for outputting the current in the current generating means is connected, and a field effect transistor connected to a control terminal of the field effect transistor and a second potential point. It is provided with a bipolar transistor to which the drain current of the transistor is input.

Further, another voltage detection circuit according to the present invention includes a constant current source having one terminal connected to a first potential point and another terminal connected to a signal output terminal for outputting a signal, an input stage and an output stage. The same input signal is applied to the control terminals of the first current mirror circuit and the second current mirror circuit, and each one terminal receives different currents of the input stages of the first and second current mirror circuits. A first transistor and a second transistor, a first load connected between the other terminals of the first and second transistors, a connection point of the second transistor and the first load is connected to one terminal, and a second terminal is connected to the other terminal. A second load connected to a potential point, a third current mirror circuit having an input stage and an output stage, the input stage receiving a current of the output stage of the first current mirror circuit, a second potential point and a constant current source Between other terminals Connected, field effect transistors difference is injection of a current of the output stage of the current and the third current mirror circuit of the output stage of the second current mirror circuit to the control terminal, and control of the field effect transistor terminal and a second
A bipolar transistor connected to the potential point and having the drain current of the field effect transistor input to the control terminal is provided.

[Work]

In the voltage detection circuit according to the present invention, the voltage detection circuit is connected between the control terminal and the second potential point in the field effect transistor that controls the potential level of the signal output from the signal output terminal when turned on or off, and is connected to the control terminal. Since the bipolar transistor into which the drain current of the field effect transistor is input is provided, the excess charge accumulated between the gate and the source of the field effect transistor can be moved to the second potential point via the bipolar transistor, The gate voltage of the field effect transistor does not become higher than the saturation voltage between the emitter and collector of the bipolar transistor. Therefore, when the input signal voltage V _IN transitions from a state higher than the threshold value V _S to a state lower than the threshold value V _{S, the} time required for the gate voltage of the field effect transistor to decrease to the operating voltage V _TH of the field effect transistor is significantly increased. Shortened.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention. In this embodiment, the first current mirror circuit (3
0) and the second current mirror circuit (40) are, for example, p-channel MOST (hereinafter referred to as p-MOST), and the third current mirror circuit (50) is, for example, an n-channel MOST (hereinafter, n-channel MOST is referred to as n-MOST). Called)).

In FIG. 1, the first p-MOST (61) and the second p-MOST are shown.
The input stage (31) of the first current mirror circuit (30) composed of (62) includes a first potential point connected to the power source (2), here a high potential point (3) and the first transistor. It is arranged between the collector of a certain first npn transistor (4). The output stage (32) of the first current mirror circuit (30) is arranged between the high potential point (3) and the second connection point (12). The second connection point (12) is connected to the drain of the first n-MOST (65).

Further, the input stage (41) of the second current mirror circuit (40) including the third p-MOST (63) and the fourth p-MOST (64).
Is also arranged between the high potential point (3) and the collector of the second npn transistor (6) which is the second transistor. The output stage (42) of the second current mirror circuit (40) is arranged between the high potential point (3) and the drain of the second n-MOST (66).

The emitter area ratio of the first npn transistor (4) and the second npn transistor (6) is 1: n (n <1 in this example), and both bases are connected to the signal input terminal (7).

The emitter of the second npn transistor (6) is connected to a first connection point (9) via a first load (8) and to the first npn transistor (6).
The emitter of the transistor (4) is directly connected to the first connection point (9). A second load (11) is connected between the first connection point (9) and the ground line (10) which is the second potential point. 1n-MOST (65) and 2n-
The gates of MOST (66) are connected to each other,
It is also connected to the drain of the -MOST (66) to form a third current mirror circuit (50), and its current mirror ratio is 1: 1. The third current mirror circuit (50) is connected to the ground line (10).

Further, the high potential point (3) is connected to the third point via the constant current source (15).
It is connected to the connection point (17), and one end of the third connection point (17) is connected to the signal output terminal (19) via the inverter circuit (18). The other end of the third connection point (17) is connected to a bipolar transistor, which is the base of a pnp transistor (67) in this embodiment, and is further connected to the drain of a field effect transistor, which is a third n-MOST (68) in this embodiment. Has been done. The source of the third n-MOST (68) is connected to the ground line (10), the gate is connected to the second connection point (12), and the collector is connected to the ground line (10).
It is also connected to the emitter of the pnp transistor (67). The parasitic capacitance (69) between the gate of the third n-MOST (68) and the ground line (10) indicates the parasitic capacitance between the gate and the source.

 Next, the operation will be described.

The threshold voltage V _S is given by the first equation as described in the conventional example.

In the circuit configuration of FIG. 1, the first current mirror circuit (30), the second current mirror circuit (40) and the third current mirror circuit (50) have a current mirror ratio of 1: 1. circuit input stage (31) current I _C1 and the output stage of the current I ₁ (32), an output stage (42) and the current I _C2 of the input stage (41) of the second current mirror circuit (40) (30) The current I ₂ , and the current I ₂ at the input stage and the current I _{D3 at the} output stage of the third current mirror circuit (50) have the same value. That is, it is represented by the above-mentioned second equation and then the fifth equation.

I _C2 = I ₂ = I _D3 (3) When the input voltage V _{IN of the} signal input terminal (7) is lower than V _S , I _C1 <I _C2 and the second Since there is a relationship between the equation and the fifth equation, it becomes necessary to _satisfy I ₁ <I _D3, and the charge is extracted from the gate electrode of the third n-MOST (68). Therefore, the gate voltage V _{G of the} third n-MOST (68) is
The third n-MOST (68) is turned off, the drain voltage becomes "H" level, the "H" level is input to the inverter circuit (18), and the "L" level is output from the signal output terminal (19). Is output.

When V _IN is equal to V _S , I _C1 = I _C2 , and from the second and fifth equations, I ₁ = I _D3 . At this time, since a sufficient voltage is not applied to the gate electrode of the 3n-MOST (68), the 3n-MOT (68) cannot be applied.
ST (68) is turned off, and the “L” level is output from the signal output terminal (19) as in the case of V _IN <V _S.

When V _IN is higher than V _S, I
_C1 > I _C2, and I ₁ > I _D3 from the second and fifth equations. Therefore, the excess current flows in as an accumulated current of the capacitance formed by the gate electrode and the source electrode of the third n-MOST (68). The gate-source parasitic capacitance of the third n-MOST (68) (6
When the value of 9) is C _GS , the gate voltage V _G is given by the sixth equation.

When V _G reaches the operating voltage V _TH of the third n-MOST (68), the third
The n-MOST (68) turns ON, the output potential of the constant current source (15) becomes the ground potential, the "L" level is input to the inverter circuit (18), and the "H" level is output from the signal output terminal (19). Is output.

Thus, the first to third current mirror circuits (3
0), (40), (50), 1st and 2nd npn transistors (4), (6), 1st and 2nd loads (8), (11) make a signal input terminal (7) input _Done V _IN
It is possible to obtain a current generation circuit that generates currents in the opposite directions from the second potential point (12) when V is larger than V _{S and} when V _S is smaller than V _S. The current from this second potential point (12) is the third n
-Injected into the gate electrode of MOST (68),
-ON / OFF of the MOST (68) is controlled, and the logic level of the signal output terminal (19) changes.

Here, the drain current _ID of the third n-MOST (68) increases as its gate voltage V _G increases. At this time, I _D is pnp
Sufficient since it corresponds to the base current of the transistor (67)
When I _D flows, the pnp transistor (67) turns on.
However, since excess charge of the gate electrode of the third n-MOST (68) flows from the emitter electrode of the pnp transistor (67) to the collector electrode, V _G is the emitter-collector saturation voltage V _{EC of the} pnp transistor (67). _Does not rise above _(sat) . That is, without the pnp transistor (67), V _G approaches the power supply voltage V _cc , but with the pnp transistor (67),
V _G is limited to V _{EC (sat)} .

Fig. 2 (a) shows V with and without pnp transistor (67).
FIG. 8 is a comparative diagram of _G over time. In FIG. 2 (a),
The horizontal axis is time and the vertical axis is V _G. Further, FIG. 2 (b) is a comparison diagram of the time lapse of the output signal voltage V ₀ depending on the presence or absence of the pnp transistor (67). In FIG. 2B, the horizontal axis is time and the vertical axis is V ₀ . 2 (a) and 2 (b) are drawn with the origins of the time axes aligned. In FIG. 2A, the gate voltage V _G of the third n-MOST (68) without the pnp transistor (67).
There a dotted line (i.e. V _G2 curve), also is V _G in the case where there is a pnp transistor (67) shown in solid lines (i.e. V _G1 curve). In FIG. 2, t ₁ is the time when the input voltage of the signal input terminal (7) becomes larger than the threshold voltage V _S , and t ₂ is the input voltage of the signal input terminal (7) more than the threshold voltage V _S. When it becomes small, t _X is the gate voltage V _G of the third n-MOST (68)
Is the time when V _{EC (sat)} is reached.

If t ₁ = 0 now, the change in V _G from t ₁ to t ₂ is
When the gate-source parasitic capacitance (69) of 3n-MOST (68) is C _GS , t = 0, V _G = 0, and t → ∞, and V _G = V _cc. Shown.

(Where α is a positive constant) The time Δt ₁ from V _G = 0 to V _G = V _TH is expressed by the equation 8 regardless of the presence or absence of the pnp transistor (67).

Next, the gate voltage of the third n-MOST (68) has an initial value of t = 0.
The manner in which the value decreases from V _G0 is shown in Equation 9.

(However, β is a positive constant) The ninth equation is an equation in which t = 0 at time t ₂ in FIG. 2 (a).

In formula 9, V _G = V _G0 begins to decrease and V _G = V _TH
The time Δt ₂ required to reach is expressed by equation 10.

If there is a pnp transistor (67) from the 10th equation, the initial value is V _G = V _{EC (sat)} , and the time Δt ₂₁ from the initial value V _{Ec (sat)} to V _TH is the 11th equation. Shown.

If there is no pnp transistor (67), the initial value is V _G = V _cc
, The time it takes for the initial value V _cc to decrease to V _TH , Δt ₂₂
Is given by Equation 12.

Since the magnitude relationship between Δt ₂₁ and Δt ₂₂ given by the equations _{(11) and (12)} has a relation of V _TH <V _{EC (sat)} <V _cc , it is expressed by the equation (13 ₎ .

Δt ₂₁ <Δt ₂₂ (13) Therefore, by connecting the pnp transistor (67) as in the invention, the response positiveness is improved by Δt ₂₂ −Δt ₂₁ .

Further, in the above embodiment, the voltage detection circuit of the microcomputer is shown, but it operates with other low current consumption.
A circuit including a MOST output circuit may be used, and the same effects as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the present invention, it is connected between the control terminal and the second potential point in the field effect transistor that controls the potential of the signal output from the signal output terminal when turned on or off, and the control terminal is connected to the control terminal. Since the bipolar transistor into which the drain current of the field effect transistor is input is provided, the surplus charge accumulated between the gate and the source of the field effect transistor can be moved to the second potential point via the bipolar transistor, and Even if the current consumption of the detection circuit becomes very small, the voltage detection circuit can be operated with good responsiveness.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention, FIG. 2 (a) is a diagram comparing the time passage of gate voltage depending on the presence or absence of a pnp transistor, and FIG. 2 (b) is a diagram of a pnp transistor. FIG. 3 is a circuit diagram of a voltage detection circuit according to the prior art, in which the time course of the output signal voltage depending on the presence or absence is compared, and FIG. In the figure, (3) is a first potential point, (4) is a first transistor, (6) is a second transistor, (8) is a first load, (10) is a second potential point, and (11) is a second potential point. 2 load, (15) constant current source, (19) signal output terminal, (30) or (40)
Is the first current mirror circuit, and (40) or (30) is the second
A current mirror circuit, (50) a third current mirror circuit, (67) a bipolar transistor, and (68) a field effect transistor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A constant current source having one terminal connected to a first potential point and the other terminal connected to a signal output terminal for outputting a signal, and a case where a voltage value of an input signal is larger than a predetermined value. Current generating means for generating and outputting currents in directions opposite to each other when small, connected between the second potential point and the other terminal of the constant current source,
A field effect transistor having a control terminal connected to a signal line for outputting the current in the current generating means, and a field effect transistor connected between the control terminal and the second potential point, and the control terminal having the above A voltage detection circuit comprising a bipolar transistor to which the drain current of a field effect transistor is input. 2. A constant current source having a first potential point connected to one terminal and a signal output terminal for outputting a signal to the other terminal, a first current mirror circuit having an input stage and an output stage, and Two current mirror circuits, a first transistor and a second transistor to which the same input signal is applied to their respective control terminals and each of which receives one of the different currents of the input stages of the first and second current mirror circuits. A first load connected between the other terminals of the first and second transistors, a connection point between the second transistor and the first load connected to one terminal, and a second potential point connected to the other terminal A second load, a third current mirror circuit having an input stage and an output stage, the input stage receiving the current of the output stage of the first current mirror circuit, the second potential point and the constant current source Between terminals A field effect transistor connected to the control terminal, into which a difference between the output stage current of the second current mirror circuit and the output stage current of the third current mirror circuit is injected, and a control terminal of the field effect transistor A voltage detection circuit comprising: a bipolar transistor connected to the second potential point and having a control terminal to which the drain current of the field effect transistor is input.