JPH0821864B2 - High efficiency encoder - Google Patents

Description

The present invention relates to a high-efficiency coding apparatus for compressing image data such as digital television signals.

[Outline of Invention]

According to the present invention, in a high-efficiency coding apparatus applied when transmitting image data such as a digital television signal, one screen is divided into a large number of two-dimensional or three-dimensional primary blocks, each primary The dynamic range of the block is detected, and the primary block is converted into a secondary block having a block size according to this dynamic range. Two
An average value is calculated for each subsequent block, the average value is quantized, and dynamic range information and average value data are transmitted. According to the present invention, the compression rate can be increased without degrading the quality of the restored image on the receiving side.

[Conventional technology]

When encoding a television signal, as a method of reducing the average number of bits per pixel, block encoding is known in which a screen of one field is subdivided into minute blocks and the average value of each block is transmitted. There is. In this block coding, if the block size is increased and the number of pixels included in one block is increased, the average number of bits per pixel is decreased and the compression rate can be increased. However, when the block size is increased, there is a drawback that block distortion is conspicuous in the restored image obtained on the receiving side in a place where the luminance level changes drastically.

[Problems to be solved by the invention]

In the conventional block coding, a block size is selected so that the block distortion is not noticeable even in a place where the luminance level changes drastically. Therefore, in a place where the change in the brightness level is small, the block size becomes larger than necessary, and the compression rate cannot be increased sufficiently.

Therefore, an object of the present invention is to provide a high-efficiency coding device capable of increasing the compression rate without causing block distortion by varying the block size adapted to the dynamic range of each block. .

[Means for solving problems]

According to the present invention, a dynamic range detection circuit 3 for obtaining a dynamic range DR for each first block composed of regions belonging to the same field or a plurality of consecutive fields of a digital image signal, and a second block having a block size corresponding to the dynamic range DR Secondary block circuit 4 for converting the first block into a block, an average value detection circuit 5 for calculating the average value of the pixel data included in the second block, and a quantization circuit 7 for quantizing the average value. And a framing circuit 8 for transmitting information indicating the dynamic range DR of each block and a quantized output.

[Action]

A block having a very small dynamic range DR is an image in which there is almost no change in the brightness level, so the average value of the first block is quantized and this quantized output is transmitted. In this case, the block sizes of the first block and the second block are equal, and the compression rate is the highest. Since the increase in the dynamic range DR means that the change in the brightness level increases, the block size of the second block is reduced and the average value of the second block is quantized. Then, since a block having a very large dynamic range DR is an image in a place where the luminance level changes drastically, all pixels of the first block are quantized. Quantizing all the pixels means that the second block is composed of one pixel. in this way,
By changing the block size adaptively to the dynamic range DR, the compression rate can be increased without causing block distortion.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This invention is made in the following order of items.

a. Configuration of transmitting side b. Configuration of receiving side c. Block and blocking circuit d. Dynamic range detection circuit e. Quantization circuit f. Modified example a. Configuration of transmitting side FIG. 1 shows the transmitting side of the present invention. The configuration of (recording side) is shown as a whole. A digital television signal in which, for example, one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to the primary blocking circuit 2.

The primary blocking circuit 2 converts an input digital television signal into a continuous signal for each two-dimensional primary block. In this embodiment, one block has a size of (8 lines × 8 pixels = 64 pixels). The output signal of the primary blocking circuit 2 is the dynamic range detection circuit 3
And to the secondary blocking circuit 4. The output signal of the secondary blocking circuit 4 is supplied to the average value detection circuit 5. The secondary blocking circuit 4 converts the primary block formed by the primary blocking circuit 2 into a secondary block having an equal block size or a smaller block size. This secondary block is a unit of coding. The block size of the secondary block is adaptively determined by the dynamic range DR from the dynamic range detection circuit 3.

The dynamic range detection circuit 3 detects the dynamic range DR and the minimum value MIN for each primary block. The data PD from the average value detection circuit 5 is supplied to the subtraction circuit 6,
The data PDI from which the minimum value MIN has been removed in the subtraction circuit 6.
Is formed.

As an example, in the secondary blocking circuit 4, the block size of the secondary block is determined according to the dynamic range DR as follows. The division ratio is defined for the primary block, and the compression ratio is (the number of data in the secondary block ÷
It is defined by the number of pixels in the primary block (64).

That is, when the dynamic range DR is very small, the block size of the secondary block is made equal to that of the primary block, and conversely, when the dynamic range DR is large, the block size of the secondary block is configured in pixel units. The threshold level of the dynamic range DR described above coincides with the threshold level in the dynamic range adaptive encoding described later, but it is not always necessary to make both coincide with each other.

The average value detection circuit 5 calculates an average value for each secondary block. 1 when the dynamic range DR is very small
The average value (8 bits) of the 64 pixel data of the next block is calculated. On the contrary, when the dynamic range DR is large, 64 pieces of pixel data are directly output from the average value detection circuit 5. The output of the average value detection circuit 5 is the subtraction circuit 6
Is supplied to. Data after removal of the minimum value from the subtraction circuit 6
The PDI is supplied to the quantization circuit 7. In the quantization circuit 7,
The data PDI is quantized with the number of bits adapted to the dynamic range DR of each block.

The coded code DT from the quantization circuit 7 is supplied to the framing circuit 8. In the framing circuit 8, the dynamic range DR (8
Bit) and the minimum value MIN (8 bits). The framing circuit 8 performs error correction coding processing on the coded code DT and the above-mentioned additional code, and also adds a synchronization signal. Transmission data is obtained at the output terminal 9 of the framing circuit 8, and this transmission data is sent to a transmission line such as a digital line.

As described above, the encoded code DT has a variable number of bits for each block, but the bit length of the pixel data of the block is uniquely determined from the dynamic range DR in the additional code. Therefore, there is an advantage that it is not necessary to insert a redundant code indicating a data delimiter in the transmission data, although the variable length code is adopted.

b. Configuration on the receiving side FIG. 2 shows the configuration on the receiving (or reproducing) side. The received data from the input terminal 11 is supplied to the frame decomposition circuit 12. The frame decomposing circuit 12 separates the encoded code DT from the additional codes DR and MIN and performs error correction processing. The encoded code DT is supplied to the decoding circuit 13, and the dynamic range DR is the decoding circuit 13 and the replacement circuit 15.
And the secondary block decomposition circuit 16.

The decoding circuit 13 performs a process reverse to that of the quantization circuit 7 on the transmission side. That is, the data after the 8-bit minimum level is removed is combined as a representative level, and this data and the 8-bit minimum value MIN are added by the adder circuit 14 to decode the original data. The output data of the adder circuit 14 is replaced by the replacement circuit 15
Is supplied to. The replacement circuit 15 forms the pixel data of the secondary block having the decoded level.

The decoded data for each secondary block is supplied from the replacement circuit 15 to the secondary block decomposition circuit 16. Secondary block decomposition circuit
Contrary to the secondary block forming circuit 4 on the transmission side, 16 converts the decoded data in the order of the secondary blocks into the order of each primary block. The output data of the secondary block decomposing circuit 16 is supplied to the primary block decomposing circuit 17. The primary block decomposing circuit 17 is a circuit for converting the data in the order of the primary block into the same order as the scanning of the television signal, contrary to the primary block forming circuit 2 on the transmitting side. The decoded television signal is obtained at the output terminal 18 of the primary block decomposition circuit 17.

c. Block and Blocking Circuit A block, which is a unit of coding, will be described with reference to FIG. In this example, by dividing the screen of one field, a large number of two-dimensional primary blocks of (8 lines × 8 pixels) shown in FIG. 3 are formed. Third
In the figure, the solid line indicates the odd field line,
Dashed lines indicate even field lines. Unlike this example, the present invention can be applied to, for example, a three-dimensional block including four two-dimensional regions belonging to each frame of four frames.

The primary blocking circuit 2 will be described with reference to FIGS. 4, 5, and 6. For the sake of simplicity of explanation, the screen of 1 field goes through the structure of (4 lines × 8 pixels) as shown in FIG. 5, and this screen is divided into two vertically and horizontally as shown by the broken line. A case will be described in which four blocks are divided into four to form eight blocks of (2 lines × 2 pixels).

In FIG. 4, as shown in FIG. 6A, input data A consisting of 4 lines (Th _{0 to} Th ₃ ) is applied to the input terminal indicated by 21.
And a sampling clock B (FIG. 6B) synchronized with the input data A is supplied to the input terminal indicated by 22. The numbers (1 to 8) indicate the sample data of the line Th ₀ , the numbers (11 to 18) indicate the sample data of the line Th ₁ , and the numbers (21 to 28) indicate the sample data of the line Th ₂ . , And the numbers (31-38) are the line Th ₃
The sample data of each is shown. The input data A is supplied to the delay circuit 23 having a delay amount of Th and the delay circuit 24 having a delay amount of 2Ts (Ts: sampling period). Further, the sampling clock B is supplied to the 1/2 frequency dividing circuit 27.

The output signal C of the delay circuit 24 (FIG. 6C) is a switch circuit.
The delay circuit 23 is supplied to one of the input terminals of 25 and 26, respectively.
Output signal D (FIG. 6D) is supplied to the other input terminals of the switch circuits 25 and 26, respectively. The switch circuit 25 is 1 /
Controlled by the output signal E of the divide-by-2 circuit 27 (Fig. 6E), the switch circuit 26 outputs the pulse signal E as an inverter.
It is controlled by the pulse signal inverted by 28. The switch circuits 25 and 26 alternately select the input signal (C or D) every 2Ts. The output signal F from the switch circuit 25 is shown in FIG. 6F, and the output signal G from the switch circuit 26 is shown in FIG. 6G.

The output signal F of the switch circuit 25 is the first signal of the switch circuit 29.
Input terminal and a delay circuit 30 having a delay amount of 4 Ts. The output signal G of the switch circuit 26 is supplied to the delay circuit 31 having a delay amount of 2Ts. The output signal H of the delay circuit 30 (FIG. 6H) is supplied to the third input terminal of the switch circuit 29. The output signal I (FIG. 6I) of the delay circuit 31 is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 4Ts. The output signal J (FIG. 6J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the 1/2 divider circuit 27 is supplied to the 1/2 divider circuit 33, and the output signal K (K in FIG. 6) is formed. The switch circuit 29 is controlled by the signal K, and the first and second switching is performed every 4Ts.
The second, third and fourth input terminals are sequentially selected. Therefore,
Signal L output from switch circuit 29 to output terminal 34
Is as shown in FIG. 6L. That is, the order of each field of data is the order of each block (for example, 1 → 2 → 11).
→ Converted to 12). Of course, the actual number of pixels in one field is much larger than the example shown in FIG. 5,
By the same scan conversion as described above, conversion is performed in the order of each block shown in FIG.

The secondary blocking circuit 4 is provided with a plurality of blocking circuits having the same configuration as the above-described primary blocking circuit 2 that blocks into different block sizes, and outputs the blocking circuit according to the dynamic range DR. It has a configuration to switch.

When the dynamic range DR is very small, the block size of the secondary block is made equal to that of the primary block, and when the dynamic range DR is small, FIG.
As shown in FIG. 7, when the primary block is divided into four secondary blocks of (4 lines × 4 pixels) and the dynamic range DR is medium, as shown in FIG. When the dynamic range DR is large, each pixel of the primary block is a secondary block. Therefore, the secondary blocking circuit 4 performs blocking as shown in FIGS. 7A and 7B, respectively. In the average value detection circuit 5,
The average value for each secondary block is calculated. However, when the dynamic range DR is large, each pixel data itself, not the average value, is output to the subtraction circuit 6.

d. Dynamic Range Detection Circuit FIG. 8 shows an example of the configuration of the dynamic range detection circuit 3. Image data is sequentially supplied to the input terminal indicated by 41 from the blocking circuit 2 for each primary block as described above. The data from the input terminal 41 is supplied to the selection circuit 42 and the selection circuit 43. One selection circuit 42
Selects between the input data and the output data of the latch 44, whichever has the larger level, and outputs the selected one. Other selection circuit
43 selects and outputs the one having a smaller level between the input data and the output data of the latch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also captured by the latch 44. The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and is also captured by the latch 45. A latch pulse is supplied from the control unit 49 to the latches 44 and 45. Timing signals such as a sampling clock and a synchronization signal that are synchronized with the input data are supplied to the control unit 49 from the terminal 50. Latch pulses are supplied to the control unit 49 to the latches 44 and 45 and the latches 47 and 48 at a predetermined timing.

At the first timing of each primary block, latch 44 and
The contents of 45 are initialized. All of the data of "0" is initialized to the latch 44, and all of the data of "1" is initialized to the latch 45. The maximum level is stored in the latch 44 among the pixel data of the same primary block sequentially supplied. In addition, the minimum level is stored in the latch 45 among the pixel data of the same primary block sequentially supplied.

When the detection of the maximum level and the minimum level is completed for one block, the maximum level of the primary block occurs at the output of the selection circuit 42. On the other hand, the output of the selection circuit 43
The minimum level of the next block occurs. Latches 44 and 45 are re-initialized upon completion of detection for one primary block.

The output of the subtraction circuit 46 is the maximum level from the selection circuit 42.
The dynamic range DR of each primary block obtained by subtracting MAX and the minimum level MIN from the selection circuit 43 is obtained. The dynamic range DR and the minimum level MIN are latched in the latches 47 and 48 by the latch pulse from the control unit 49. The dynamic range DR of each primary block is obtained at the output terminal 51 of the latch 47, and the output terminal of the latch 48
At 52, the minimum value MIN of each primary block is obtained.

e. Quantization circuit The quantization circuit 7 performs variable-length coding adapted to the dynamic range DR. FIG. 9 shows an example of the quantization circuit 7. In FIG. 9, the ROM indicated by 55 stores a data conversion table for converting the data PDI after the minimum value removal (8-bit pixel data or 8-bit average value data) into a compressed bit number. ing. For ROM55, dynamic range DR from input terminal 56 and input terminal
The data PDI from 57 is supplied as an address signal.

In the ROM 55, the data conversion table is selected according to the size of the dynamic range DR, and the 5-bit encoded data DT is taken out to the output terminal 58. Dynamic range DR
Accordingly, the number of bits of the encoded data DT changes within the range of 0 bit to 5 bits. Therefore, the effective bit length changes in the code output from the ROM 55. In the framing circuit 8, a valid bit is selected.

FIG. 10 is used for explaining the variable bit length coding adapted to the dynamic range, which is performed by the quantizing circuit 7. This encoding is a process of converting the data PDI from which the minimum value has been removed into a representative level. The allowable maximum value of the quantization distortion (referred to as maximum distortion) that occurs during this quantization is set to a predetermined value, for example 4.

FIG. 10A shows the case where the dynamic range DR is 8. In the case of (DR = 8), the central level 4 is the representative level L0, and the maximum distortion E = 4. That is, (0 ≦
When DR ≦ 8), the central level of the dynamic range is set to the representative level, and it is not necessary to transmit quantized data. Therefore, the required bit length is 0.
On the receiving side, decoding is performed with the representative level L0 as the restoration value from the minimum value MIN of the block and the dynamic range DR.

FIG. 10B shows the case of (DR = 17), the representative level is set to (L0 = 4) (L1 = 13), and the maximum distortion E is 4. Since there are two representative levels L0 and L1, the bit length is 1. In the case of (9 ≦ DR ≦ 17), the bit length is 1. The maximum distortion E becomes smaller as the dynamic range DR is narrower.

FIG. 10C shows the case of (DR = 35), and the representative levels are defined as (L0 = 4) (L1 = 13) (L2 = 22) (L3 = 31), respectively, and (E = 4) is there. Since there are four representative levels L0 to L3, the bit length is 2. In the case of (18 ≦ DR ≦ 35), the bit length is 2.

In the case of (36 ≦ DR ≦ 71), eight representative levels (L0-
L7) is used. FIG. 10D shows the case of (DR = 71), and the representative levels are (L0 = 4) (L1 = 13) (L2 = 22) (L3
= 31) (L4 = 40) (L5 = 49) (L6 = 58) (L7 = 67). The required bit length is 3 in order to distinguish the eight representative levels L0 to L7.

In the case of (72 ≤ DR ≤ 143), 16 representative levels (L0
~ L15) is used. FIG. 10E shows the case of (DR = 143), and the representative level is (L8 = 76) (L9 = 85) (L10 = 9).
4) (L11 = 103) (L12 = 112) (L13 = 121) (L14 = 13
0) (L15 = 139) (L0 to L7 are the same as the above values). Four bits are required to distinguish 16 representative levels (L0 to L15).

In the case of (144 ≦ DR ≦ 287), 32 representative levels (L0
~ L31) is used. FIG. 10F shows the case of (DR = 287), and the representative level is (L16 = 148) (L17 = 157) (L18
= 166) (L19 = 175) (L27 = 247) (L28 = 25)
6) (L29 = 265) (L30 = 274) (L31 = 283) (L0 ~ L15
Is the same as the value above). Five bits are required to distinguish 32 representative levels (L0 to L31).
Actually, since the input pixel data is quantized with 8 bits, the maximum value of the dynamic range DR is 255,
It is not quantized to the representative level (L28 to L31).

Since the television signals in one block have a three-dimensional correlation in the horizontal and vertical two-dimensional directions and in the time direction, in the steady part, the variation range of the level of the pixel data included in the same block. Is small. Therefore,
Even if the dynamic range of the data DTI after removing the minimum level MIN shared by the pixel data in the block is quantized with a quantization bit number smaller than the original quantization bit number, quantization distortion hardly occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original transmission bandwidth.

f. Modified example When performing coding adapted to the dynamic range, for example, when the dynamic range is divided into four and quantized into four representative levels, as shown in FIG. 11, the minimum value MIN and the maximum value are set as the representative levels. A value that matches the value MAX may be used. Further, in the case of variable length encoding, the representative level may be a fixed value for each bit length. Further, dynamic range adaptive coding with a fixed bit length may be used. Furthermore, in the present invention, a high efficiency coding method other than the dynamic range adaptive coding method may be combined.

〔The invention's effect〕

According to the present invention, the block size of the secondary block is increased and the average value is transmitted in the steady part where the change width of the brightness level is small, and the block of the secondary block is transmitted in the middle part of the change range of the brightness level. The size is reduced, the average value is transmitted, and further, the data for each pixel is transmitted in the portion where the change width of the brightness level is large. Therefore, the amount of data to be transmitted can be significantly reduced without causing deterioration of the received image such as block distortion.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a receiving side, and FIG. 3 is a schematic diagram used for explaining a block which is a unit of encoding processing. FIG. 5, FIG. 5 and FIG. 6 show an example of the configuration of the blocking circuit, schematic diagrams and timing charts for explaining it, and FIG.
FIG. 8 is a schematic diagram for explaining the next block formation, FIG. 8 is a block diagram of an example of a dynamic range detection circuit, FIG. 9 is a block diagram of an example of a quantization circuit, and FIGS. 10 and 11 are quantizations respectively. It is an approximate line figure used for explanation of an example and other examples. Description of main symbols in the drawings 1: Digital television signal input terminal, 2: Primary blocking circuit, 3: Dynamic range detection circuit, 4: Secondary blocking circuit, 5: Average value detection circuit, 7: Quantum Conversion circuit, 8: Frame conversion circuit.

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Claims (1)

[Claims] 1. A means for obtaining a dynamic range for each first block consisting of areas belonging to the same field or a plurality of consecutive fields of a digital image signal, and to a second block having a block size corresponding to the dynamic range. Means for converting the first block, means for calculating the average value of the pixel data included in the second block, means for quantizing the average value, information indicating the dynamic range for each block, and the above A high-efficiency encoding device comprising means for transmitting a quantized output.