JPH0823820B2 - Address overlap check processor - Google Patents

Description

DETAILED DESCRIPTION [Outline] An address generator and an overlap checker are provided, and a second operand address and a first operand
In a data processing device that advances processing while checking for overlap with an address, information obtained as a result of considering information from a bypass route supplied to an address generator in calculating a second operand address is described above. It is disclosed that the overlap checker is supplied so as to eliminate the processing delay when the contents of the base register are changed by the pipeline preceding instruction.

[Industrial applications]

The present invention has an address overlap check processing device, and in particular, has a function of performing a check by an overlap checker in performing processing such as reading and processing the contents of the second operand and storing it in the position of the first operand. In data processing equipment,
The present invention relates to an address overlap check processing device capable of adjusting an input supplied to a checker at an early stage.

[Conventional technology]

In a data processing device that performs pipeline processing, an instruction that reads the first operand and the second operand from the main storage device, performs an operation, and writes the result to the position of the first operand in the main storage device, An instruction or the like may be executed in which the operand is read from the main storage device and written in the position of the first operand on the main storage device.

When executing such an instruction, as a software interface condition, for example, in a data processing device in which one word consists of 8 bytes, in general, 1 byte operation which is a unit of address is sequentially executed and finally 8 bytes are obtained. It is assumed that the calculation result of is obtained.

However, in terms of hardware, operations are performed in 8-byte units, so there is a problem that the hardware conditions seen by software will not match, and it was necessary to apparently process in 1-byte units. .

As a specific example, consider a case where the second operand address differs from the first operand address by one byte in an instruction that transfers data from the second operand address to the first operand address. In this case, all "0s" are put in only the first 1 byte of the storage content (second operand) in the second operand address, and the second operand address and the first operand address are successively added to the above 1 byte. When this transfer instruction (in this case, an instruction that transfers in 1-byte units) is executed while shifting the amount, the storage contents (first operand) at the first operand address are sequentially incremented by 1 byte from the first byte. "0" is transferred, and finally "0" can be inserted in the total data length. Above software
As an interface condition, it is expected that "0" can be put in the total data length as described above even when data is transferred in 8-byte units that make up one word in a data processing device that consists of eight bytes. Has been done. Of course, if the transfer is performed byte by byte as described above, the expectation can be satisfied.

However, in actuality, when the entire 8-byte unit forming one word of the data processing device is put into the first 1 byte of the second operand as described above and this instruction is executed, 8 Data in which only the first 1 byte of the word of bytes is "0" but the other 7 bytes are not "0" is transferred from the second operand address to the first operand address. After that, the second operand address and the first operand address are shifted by 8 bytes each,
The entire data length of the first operand is transferred from the operand address to the first operand address in units of 8 bytes. As a result, the first operand becomes data in which the first two bytes are all "0" and the remaining bytes are not all "0", and the intended purpose can be achieved. Disappear.

As a countermeasure against this problem, the overlap check between the first operand address and the second operand address is performed, and if the two addresses overlap within a range of 8 bytes, for example, they are overlapped. It is necessary to adopt a method in which an operation with a byte length in a non-existing range is repeated for all data lengths (or write length when the operation result is written to the main memory). Then, conventionally, the overlap check is performed.

FIG. 3 shows the conventional structure, and FIG. 4 shows a time chart when the processing is interrupted.

In the figure, reference numeral 1 is an address generator, 2 is an address holding register, 3 is an overlap checker, 4 is an index register, 5 is a base register, 6 is a displacement register, and 7 to 9 are selectors, respectively. 10 is an instruction register, 11 is a general-purpose register group, and 12 is a bypass route.

In the conventional case, in the first flow, the first operand address is calculated by the address generator 1 and set in the register 2, and the main memory device is accessed based on the value set in the register 2 to set the first operand. After being read, the first operand is operated through the operation means, and the operation result is written in the main memory. Then, in the second flow, the second operand address is calculated by the address generator 1 and set in the register 2 to perform the subsequent processing, and is a generating element for generating the second operand address. The contents of the base register 5 and the contents of the displacement register 6 are input to the overlap checker 3 so that the contents are checked against the contents of the register 2.

The contents of the general-purpose register indicated by the base register designating section B1 of the instruction set in the instruction register 10 are supplied to the base register 5, and the displacement register 6 is supplied with the displacement of the instruction.
D1 is supplied.

In consideration of the case where the general-purpose register indicated by the base register designating part of the above instruction is changed by the pipeline preceding instruction, the second operand address can be determined early even in such a case. Therefore, the bypass route 12 is provided, and the contents of the bypass route are supplied to the address generator 1 via the selectors 7 and 8. That is, the information of the result calculated by the above-mentioned calculating means in the pipeline preceding instruction is supplied to the address generator 1 through the bypass route 12 at an early stage.

[Problems to be solved by the invention]

Conventionally, the above configuration has been considered, but the bypass
In the case shown in FIG. 3, the information from the route 12 is supplied only to the address generator 1 and not to the overlap checker 3. For this reason, as shown in the time chart of FIG. 4, when a change is made by the pipeline preceding instruction as described above, the result of the change is written in the general-purpose register group 11, and then the base register 5 The check by overlap checker 3 cannot be performed until it is reflected in.
In other words, since the information from the bypass route 12 is not supplied to the overlap checker 3, the result of the above change is once written in the general-purpose register group 11 and then read from the general-purpose register group 11. The check by the overlap wrap checker 3 cannot be performed until it is set to the base register 5. FIG. 4 shows this, and in the second flow, the base register 5
Is the same as waiting for the processing by the address generator 1 until the time when it is read from the general-purpose register group 11 and set. That is, until then, the second operand
An interruption occurs to determine the address and the overlap amount (Phase A in the second flow shown in FIG. 4).
The continuous part of is equivalent to the interruption).

[Means for solving problems]

The present invention solves this point, and FIG. 1 shows a principle configuration diagram of the present invention (which is also the configuration of one embodiment of the present invention). The symbols in the figure correspond to those in Fig. 3, where 1 is the address
Generator, 2 is address holding register, 3 is overlap checker, 4 is index register, 5 is base register, 6 is displacement register, 7 to 9 is selector, 10 is instruction register, 11 is general purpose register Group 12, represents the bypass route. There are other inputs (not shown) on the input sides of the selectors 7, 8 and 9 shown in the figure, but these inputs are not shown because they are not directly related to the present invention. . Then, which input is selected by each of the selectors 7, 8 and 9 to be supplied to the address generator 1,
It is determined by the content of the operation code of the instruction at that time.

In the case of the present invention as well, the main memory is accessed based on the value set in the address holding register 2 (of course, it may not be necessary to read from the main memory), and the main memory is read. The operands are calculated by the calculating means and then stored in the main storage device (of course, it may not be necessary to store them in the main storage device).

In the case of the present invention, the overlap checker 3 is input from the output stage side of the selectors 8 and 9. For this reason, when the information set in the general-purpose register group 11 is supplied to the address generator 1 via the bypass route 12 for the calculation of the second operand address, it is overwritten from the output stage of the selector 8. It is also supplied to the lap checker 3.

[Action]

Information that should be set in the general-purpose register group 11 when it is changed by the pipeline preceding instruction as described above is also supplied to the bypass route 12 (that is, set in the general-purpose register group 11 and then the general-purpose register group 11 is set). It is not read from the register group 11 but directly when it is set in the general-purpose register group 11), and is supplied to the address generator 1 in the state of performing the address calculation of the second flow, and the It is also supplied to the lap checker 3.

As a result, when the second operand address is calculated by being input to the address generator 1, the same information is also input to the overlap checker 3 and the first operand
The amount of overlap with the address (content of register 2) can be calculated early.

〔Example〕

Since the configuration of the embodiment of the present invention is substantially the same as the principle configuration diagram shown in FIG. 1, description will be avoided, but the description will be continued with reference to the time chart of one embodiment shown in FIG.

When the first operand address is set in the register 2 in the first flow and the above-mentioned change is made by the pipeline preceding instruction, the change result is calculated in the second operand address calculation at the timing shown in FIG. Although it can be supplied to the address generator 1 via the bypass route 12 to reflect it, the overlap checker 3 can perform the check at this same timing.

That is, as is clear from comparison between FIG. 4 and FIG. 2, it is sufficient that the interruption in the second flow is small.

〔The invention's effect〕

As described above, according to the present invention, the intended purpose can be achieved only by sharing the bypass route for supplying information by bypassing the address generator also for the overlap checker. For this reason, the control mode is also greatly simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a time chart of one embodiment of the present invention, FIG. 3 is an example of the structure premised on the present invention, and FIG. 4 is a case of the structure shown in FIG. A time chart is shown. In the figure, 1 is an address generator, 3 is an overlap checker, 4 is an index register, 5 is a base register, and 6 is a displacement register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-218567 (JP, A) JP 59-231652 (JP, A) JP 60-178539 (JP, A) JP 60- 204036 (JP, A) JP 54-41641 (JP, A)

Claims (1)

[Claims] 1. An address generator (1) for calculating an operand address, and further comprising:
The means for reading an operand from the main storage device based on the address calculated by the generator (1), the calculating means for performing an operation based on the read operand, and the value of the result calculated by the calculating means A means for storing the data in the main memory, at least the means for storing the data in the instruction register, and based on the instruction set in the instruction register at the time of setting, the processing is performed while accessing the main memory. And an overlap checker (3) for calculating the overlap amount between the second operand address and the function to execute an instruction to read at least the second operand and write the processed result to the first operand address. In the data processing device having the above, by the arithmetic means based on the pipeline preceding instruction, The value used for the address generation computed by the result,
The address generator (1) is provided with a bypass route capable of supplying to the input side of the address generator (1) at the time when the address generator (1) operates, and an index is provided as an input of the address generator (1). As a result of selecting the contents of the register (4) and the contents from the bypass route by the first selector (7), the contents of the base register (5) and the contents from the bypass route are changed to the second contents. Selector (8)
Result selected by, and displacement
The contents of the register (6) are supplied so that three of them are supplied, and the output of the address generator (1) previously performed and the address generator (1) are input as inputs of the overlap checker (3). To the address generator (1), which is the result of the selection made by the second selector at the time, and the contents of the displacement register (6) input to the address generator (1) at the time.
Address overlap check processing device characterized in that it is configured to be supplied by a user.