JPH0823851B2 - Control channel initialization control method - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Fig. 3) Problem to be solved by the invention Means for solving the problem (Fig. 1) Operation Example (Fig. 2) Effects of the Invention [Outline] In a computer system having a plurality of central processing units, a control channel initialization control system for preparing an interface that can be accessed independently of each central processing unit is described. An initial control channel capable of resetting the central processing unit system of the control channel designated by the reset designating unit by providing a reset designating unit corresponding to the central processing unit and providing an interface control register corresponding to each central processing unit In order to provide a generalized control system, each central processing unit is provided on the side of each central processing unit, and A corresponding reset designation means, a control channel designated and operated by each of the central processing units, and a port having only an interface control register corresponding to each of the central processing units; and the control channel. , A common circuit for controlling the control channel independently of the central processing unit is provided in accordance with an instruction output through each port, and when a reset instruction is issued from a certain central processing unit, the common circuit is The configuration is such that the portion of the control channel corresponding to the central processing unit for which a reset instruction has been issued is initialized.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control channel initialization control method for a computer system having a plurality of central processing units by providing an interface that can be accessed independently of each central processing unit.

[Conventional technology]

Conventionally, as shown in FIG. 3, specific data in memories 3 and 4 respectively connected to a plurality of central processing units (hereinafter abbreviated as CPUs) 1 and 2 are provided independently of the central processing units 1 and 2. In the case of writing on the disk 6 of the external storage device via the control channel 5 for the accessible external storage device, for example, to write the contents written in the address 3a of the memory 3 to the area 6a of the disk 6, It is processed as follows.

First, the CPU 1 outputs instruction information for writing the contents of the address 3a in the area 6a of the disk 6 to the control channel 5 side. In the control channel 5 which has received the instruction information, the instruction information is set in the interface control register 8 provided in the CPU1 system port 7 provided corresponding to the CPU1,
An interrupt is issued to the microprocessor unit (hereinafter abbreviated as MPU) 10 via the interrupt control circuit 9 of the CPU 1 system port 7. Based on the given instruction information, MPU10
Prepares writing to the disk 6, sets address length control information in the direct memory access (hereinafter abbreviated as DMA) control circuit 11 connected to the interface control register 8, and connects to the DMA control circuit 11. The contents of the address 3a of the memory 3 are written in the area 6a of the disk 6 via the disk control circuit 12.

When writing is completed,
An end interrupt is issued to the MPU 10, and after confirming the normality of the disk control and DMA control, the MPU 10 sets status information in the interface control register 8 and sets an interrupt instruction to the CPU 1 in the interrupt control circuit 9. When the CPU1 is interrupted, the CPU1 receives the interface control register 8
Read the contents of to confirm that the process was successful.

In such a control method of the control channel 5 of the external storage device, when the CPU1 system port 7 is reset, it is processed as follows.

First, the CPU1 sets the reset bit of the interface control register 8, the CPU1 system port 7 is hard-reset, and at the same time, it interrupts the MPU10.
Notify that the system 1 port 7 has been reset. As a result, MPU10 clears and initializes the control memory of CPU1 system port.

[Problems to be Solved by the Invention]

In the above-mentioned conventional control channel 5 and its initialization control method, the CPU1 system port 7, CP provided corresponding to each CPU 1, 2
Although it is possible to initialize each U2 system port 7a, the control channel 5 has a large circuit scale as a whole because the common control unit between each port is reduced and made independent. As a means for resetting each CPU 1, 2 and control channel, each CPU 1, 2 and each control channel are processed by issuing a reset instruction by a program for each corresponding portion, so that each CPU 1, 2 is always under control. It was necessary to store the control channel 5 that was stored. Therefore individual control channels 5
For resetting, it is necessary that the control circuit for setting the reset bit of each port 7, 7a prepared for CPU1 and 2 operate normally, and if an abnormality occurs in that part. If so, there is a problem that the control channel 5 is not reset.

The present invention has been made in view of the above problems, and a technical problem set for the purpose of solving the problems is to provide a reset designating unit corresponding to each CPU to each CPU and an interface corresponding to each CPU. A control register is provided to provide a control channel initialization control system capable of resetting the central processing unit system of the control channel designated by the reset designation means.

[Means for solving the problem]

As a means for solving the above problems, the present invention provides a control channel initialization method in a computer system including a plurality of central processing units and a control channel that is independently accessible from each central processing unit. , As shown in FIG. 1, reset designation means 15, 16, ... Provided on the side of the respective central processing units 1, 2, ... And corresponding to the respective central processing units 1, 2 ,. Central processing unit
Ports 20, 20 ... Provided on the control channel 18 designated and operated by 1, 2, ... And having only interface control registers 21, 22, ... Corresponding to each of the central processing units 1, 2 ,. , Which is provided in the control channel 18 and controls the control channel 18 independently of the central processing units 1, 2, ... In accordance with the instruction output via the ports 19, 20 ,. A circuit 24 is provided, and when a reset instruction is issued from a certain central processing unit, the common circuit 24 initializes a portion in the control channel 18 corresponding to the central processing unit that has been given the reset instruction. It was done.

Further, the control channel 18 in such a control channel initialization method is provided with an NMI control circuit 34 for notifying that there is a reset instruction from a certain central processing unit.
When the MI control circuit 34 outputs, each part is initialized to the part corresponding to the central processing unit for which the reset instruction has been issued.

Further, an AND circuit 33 for logically ANDing outputs of all the reset designating means 15, 16, ... Corresponding to each of the central processing units 1, 2 ,. When a reset instruction is issued from the processing devices 1, 2, ..., The entire control channel is initialized by the output of the AND circuit 33.

The common circuit 24 includes an interrupt control circuit 25 and a direct control circuit 25 that operate according to the outputs from the ports 19, 20 ,.
A memory access control circuit 26, an MPU 28 which is interrupted by the output of the interrupt control circuit 25, and a control circuit of an external storage device 32 which the MPU 28 operates in accordance with the output of the direct memory access control circuit 26. A circuit with 31 and 31 is preferred.

[Action]

According to the present invention, when the control channel 18 is reset, the reset bit is set by setting the reset bit in the reset designating means 15, 16 ,. CPU corresponding to the reset designating means 15, or 16, ...
The entire control system of the control channel 18 that reaches the common circuit 24 via the port 19 or 20, which belongs to the control target of ..., that is, the portion corresponding to the CPU for which the reset instruction is issued is reset to Perform initialization. In this case, the NMI control circuit 34 which detects that the reset bit has been set resets the portion corresponding to the central processing unit for which the reset instruction has been issued. Further, when all reset bits of each reset designating means 15, 16, ... Are set, when there is a reset instruction from all the central processing units, the output of the AND circuit initializes the entire control channel. To do.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the case of a control channel of a computer system provided with two CPUs.

As shown in Fig. 2, the computer system has CPUs 1 and 2 to which memories 3 and 4 are separately connected, and CPUs 1 and 2 are C and
The reset specifying means 15 including the reset registers 15a and 15b corresponding to the PUs 1 and 2 is provided, and the CPU 2 also includes the reset specifying means 16 including the reset registers 16a and 16b corresponding to the CPUs 1 and 2. The reset designating means 15 and 16 enable reset bits to be set by commands from the MPUs 1a and 2a incorporated in the CPUs 1 and 2, respectively.

Each CPU 1, 2 is connected to the input side bus 18a of the control channel 18 via the bus 17. A port for preparing an interface for CPU1 provided in control channel 18 (hereinafter CPU1
19) and a port 20 for preparing an interface for the CPU 2 (hereinafter abbreviated as CPU2 system port) 20 are respectively the interface control register 2
Only 1,22 are included. The interface control registers 21 and 22 are connected via the inside 23 to the interrupt control circuit 25 and the DMA control circuit 26 incorporated in the common circuit 24. The interrupt control circuit 25 and the DMA control circuit 26 are the internal bus 23.
And via internal bus 27 MPU28, ROM29, RAM30
And a disk control circuit 31 as an external storage device control circuit.
And connect the interrupt control circuit 25 to the MPU2 independently.
8 is connected to the input side, and the disk control circuit 31 is further connected to a disk 32 as an external storage device.

The output side of the reset registers 15a, 15b and reset registers 16a, 16b provided in each CPU 1, 2 is the control channel 18
Connected to the input side of the AND circuit 33 installed in the
Connect to the input side of the control circuit 34, further branch the output side of the reset register 15a to connect to the CPU1 side, branch the output side of the reset register 16b to connect to the CPU2 side, and AND Control channel 18 on output side of circuit 33
Connected to the internal bus 23 side of the NMI control circuit 34 and the output side of the NMI control circuit 34 to the internal bus 27, and also connected to the input side of the MPU 28. Or 16a and reset register 15
When the reset is instructed to b or 16b, each of the ports 19 and 20 of the control channel 18 and the interrupt control circuit 2 of the common circuit 24
5, DMA control circuit 26, MPU 28, and disk control circuit 31
To be able to hard reset everything.

When resetting each part of the control channel 18 associated with a particular CPU1,2, e.g. CPU1, when running the embodiment thus configured, first CPU1 is reset to reset register 15a or reset register 16a of CPU2. reset·
Set the bit. When the reset bit is set, the NMI control circuit 34 causes the NMI control circuit 34 to
(Non-maskable interrupt) is applied. The NMI applied MPU 28 clears and initializes the CPU 1-related parts of the interface control register 21, the interrupt control circuit 25, the DMA control circuit 26, the MPU 28, and the disk control circuit 31 in the control channel 18 related to the CPU 1. .

When the reset bits are set in the reset registers 15a and 15b and the reset registers 16a and 16b of each CPU 1 and 2, the reset switch 34 is activated via the AND circuit 33 and the control channel 18 Interface control registers 21, 22, interrupt control circuit 25, DMA control circuit 26,
The MPU 28 and the disk control circuit 31 are collectively reset at the same time.

Therefore, in this embodiment, due to its configuration, the reset registers 15a and 15b and the reset registers 16a and 16b corresponding to the CPUs 1 and 2 are provided in the respective CPU1 and CPU2, and in the control channel 18, the common circuit 24 is allocated. Embedded control circuit 25 and
DMA control circuit 26, MPU28, ROM29, RAM30, which is provided as a control device for accessing the CPU1 and CPU2 independently.
And built in together with the disk control circuit 31, each port
By providing only interface control registers 21 and 22 respectively to 19 and 20, each port 19 and 2 of control channel 18
0 is compact, and the control channel 18 can be downsized as a whole. Further, by providing the AND circuit 33 in the control channel 18 and inputting the outputs of the reset registers 15a and 15b and the reset registers 16a and 16b of the CPUs 1 and 2, respectively, the reset register 15a or 16a and the reset register
AND circuit 3 when register 15b or 16b is reset
The entire control channel 18 can be reset via 3.

The reset of the control system of the control channel 18 corresponding to any CPU 1 and 2 and the entire control channel 18 can be realized simply by setting the reset bit in the reset registers 15a and 15b and the reset registers 16a and 16b. Easy to control.

In the above embodiment, CPU1 and CPU2 are used to simplify the explanation.
The above described the case where two CPUs are provided. However, by providing an arbitrary number of CPUs and interface control registers corresponding to the CPUs and configuring them in the same way, the same action and effect can be obtained for a larger number of CPUs. To be

Further, although the control channel 18 for the disk 32 is illustrated in the above embodiment, the control channel 18 can be generally applied to the control channel of the external storage device and the line control channel, and the same operation can be applied to a larger number of control channels. , The effect is obtained.

〔The invention's effect〕

As described above, in the present invention, the reset designation means 15, 16, ... Is provided on each central processing unit 1, 2, ... Side, and the interface control registers 21, 22,
.. only, a portion necessary for controlling the common circuit 24 independently from the central processing units 1, 2, ..., For example, the interrupt control circuit 25, the DMA control circuit 26, the MPU 28, or the external storage device 32.
The control channel 31 is integrated into the control channel 18
Can be miniaturized, and the reset of the part corresponding to the central processing unit which has been instructed to reset the control channel 18 can be processed only by setting 1 bit of the reset designation means, which simplifies initialization by program control, The control channel 18 can be easily initialized. Therefore, the time loss due to the exclusive control between the central processing units is reduced, and the speeding up of the processing is promoted. Further, when an abnormality occurs in the system of a certain central processing unit, the port 19 of the control channel 18 belonging to the system,
Alternatively, it is possible to easily and quickly initialize 20 or so that the previous process is executed again, and the reliability of the device is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a control channel in a computer system of the present invention, FIG. 2 is a block diagram showing a control channel when a disk is used as an external storage device in an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a conventional disk control channel. 1,2 ...... CPU 15 ...... Reset specifying means 15a, 15b, 16a, 16b ...... Reset register 18 ...... Control channel 19,20 ...... Port 21,22 ...... Interface control register 24 ...... Common circuit 25 ... … Interrupt control circuit 26 …… Direct memory access control circuit 28 …… Microprocessor unit 31 …… (disk) control circuit 32 …… External storage device (disk) 33 …… AND circuit 34 …… NMI control circuit

Claims (3)

[Claims] 1. A computer system comprising a plurality of central processing units and a control channel that is independently accessible from each central processing unit, wherein the central processing unit is provided on each side of the central processing units. A reset designating means corresponding to each of them, a control channel designated and operated by each of the central processing units, and a port having only an interface control register corresponding to each of the central processing units; and the control channel And a common circuit for controlling the control channel independently of the central processing unit according to the instruction output through each of the ports, and when there is a reset instruction from a certain central processing unit, the common circuit Resets the portion of the control channel corresponding to the central processing unit that has received the reset instruction. Initialization control method of the control channel of symptoms. 2. The control channel is provided with an NMI control circuit for notifying that there is a reset instruction from a certain central processing unit, and when there is an output from the NMI control circuit, the central processing unit that has received the reset instruction The initialization control system of the control channel according to claim 1, wherein the corresponding part is initialized. 3. An AND circuit for logically ANDing outputs of all the reset designation means corresponding to each of the central processing units is provided, and when reset instructions are given from all the central processing units, the AND circuit is provided.
The control channel initialization control system according to claim 1, wherein the entire control channel is initialized by the output of the AND circuit.