JPH0824122B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention provides a second U-shaped groove between first U-shaped grooves for element isolation.
A groove is selectively formed and an insulating material is filled in the U groove, a polycrystalline semiconductor film is formed on the second U groove, and impurity ions are implanted to form a base lead electrode. And a method for manufacturing a bipolar transistor.

As a result, since the base electrode is formed on the U groove (thick insulating film), the parasitic capacitance between the base and the collector can be reduced, and the emitter and the base can be formed very close to each other in a self-aligned manner. Can be made extremely small. Therefore, it is possible to speed up the transistor operation and form an extremely small device.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device,
More specifically, the present invention relates to a method of manufacturing a bipolar transistor that can reduce the parasitic capacitance between the collector and the base.

[Conventional technology]

FIG. 2 is a cross-sectional view illustrating a bipolar transistor formed by a manufacturing method according to a conventional example. In the figure, 1 is a p-type Si substrate, and 2 is an n ⁺ buried layer selectively formed on the p-type Si substrate 1. Reference numeral 3 is an n-type epitaxial layer, 4 is a SiO ₂ film formed on the inner wall of the U groove portion opened for element isolation, and 5 is a PSG film filled in the U groove portion. Reference numeral 6 is a SiO ₂ film formed on the surface of the epitaxial layer. Further, 7 is a collector compensation diffusion layer, 8 is a p-type diffusion layer (base) formed by diffusing p-type impurities, and 9 is n formed by diffusing n-type impurities.
It is a type diffusion layer (emitter). In addition, E, B and C are an emitter electrode, a base electrode and a collector electrode.

[Problems to be solved by the invention]

The conventional manufacturing method has the following problems.

(1) Since the distance between the base electrode B and the emitter electrode E is long, the area of the base region is large. Therefore, the base
The collector junction capacitance increases, which causes a reduction in the operating speed of the transistor.

(2) Since the distance between the base electrode B and the emitter electrode E is long, there is a problem that the base resistance increases.

The present invention has been made in view of the problems of the conventional example, and an object thereof is to provide a method for manufacturing a baopolar transistor that makes it possible to reduce the parasitic capacitance and the parasitic resistance and form the device in a small size. To do.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an epitaxial layer of opposite conductivity type on a surface of a semiconductor substrate of one conductivity type, and excavating the epitaxial layer and the substrate to form a first U groove portion for element isolation. And the first U
Forming a second U-groove shallower than the first U-groove between the grooves, forming a first insulating film in the first and second U-grooves, and further insulating in the U-grooves After filling the material, a step of polishing the surface of the epitaxial layer, a polycrystalline semiconductor film is formed on the entire surface of the substrate, and a second insulating film is formed on the polycrystalline semiconductor film. Forming an opening in the insulating film to form a first opening, and forming a base extraction electrode by implanting first impurity ions into the polycrystalline semiconductor film through the first opening. Injecting second impurity ions of one conductivity type into the base extraction electrode through the first opening to form a base diffusion layer; and forming a third insulating film in the first opening. A second opening selectively exposing the insulating film and the base diffusion layer to expose the surface of the semiconductor substrate. A step of forming a portion, a step of forming a fourth insulating film on the inner wall of the second opening and forming a polycrystalline semiconductor film on the entire surface, and a step of forming a polycrystalline semiconductor film in the second opening. And diffusing third impurity ions of opposite conductivity type to form an emitter diffusion layer of opposite conductivity type in the base diffusion layer.

[Action]

According to the manufacturing method of the present invention, since the base extraction electrode is formed using the polycrystalline semiconductor film, the emitter diffusion layer and the base diffusion layer can be formed in a self-aligned manner. Therefore, the base resistance can be reduced. Further, since the second U groove (thick insulating film) is formed under the base extraction electrode, it is possible to reduce the parasitic capacitance between the base and the collector.

Further, according to the present invention, since the side surface of the base diffusion layer region is surrounded by the first U groove or the second U groove, the base-collector capacitance can be reduced.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view illustrating a method of manufacturing a bipolar transistor according to an embodiment of the present invention.

(1) First, an oxide film (not shown) on the p-type Si substrate 11 is patterned and opened to provide an opening, and n-type impurities are thermally diffused to form an n ⁺ buried layer 12, and the entire upper surface thereof is formed. An n-type epitaxial layer 13 is formed and an oxide film (not shown) is formed. Next, by patterning the oxide film, an opening is provided to form a collector compensation diffusion layer 14, and a SiO ₂ film 15 is formed in the opening.
Are formed ((a) in the figure).

(2) Next, the SiO ₂ film 15 is selectively excavated by the RIE technique to form a first U-groove portion 16 for element isolation and a second U-groove portion 17 is formed between the first U-groove portions 16. ((B) in the figure).

(3) Next, a SiO ₂ film 18 is formed on the inner walls of the first U-groove portion 16 and the second U-groove portion 17 by a CVD technique, and the PSG film 18 is filled in the first and second U-groove portions. The upper surface of the n-type epitaxial layer 13 is polished ((c) in the figure).

(4) Further, a non-doped poly-Si film 20 is formed on the entire surface of the polished n-type epitaxial layer 13, and then a SiO ₂ film 21 is formed.
To form. Next, the SiO ₂ film 21 is opened and an opening 22 is provided (FIG. 7D).

(5) Next, BF ₂ ions 23 are injected into the poly-Si film 20 through the opening 22 by the II technique to form a p ⁺ compensation diffusion layer (base extraction electrode) 24 (FIG. 8E).

(6) Further, B ⁺ ions 25 are injected into the n-type epitaxial layer through the opening 22 by the II technique to form a p-type diffusion layer (base) 26. It should be noted that it is formed deeper than the p ⁺ compensation diffusion layer (base extraction electrode) 24 ((f) in the same figure).

(7) Then, after forming the SiO ₂ film 27 in the opening 22, the SiO ₂
The film 27 and the p ⁺ compensation diffusion layer (base extraction electrode) 24 are opened, and an opening 28 for forming an emitter and an opening 29 for forming a collector junction are formed by the RIE technique (FIG. 9 (g)). ).

(8) Further, after forming a SiO ₂ film on the inner walls of the openings 28 and 29, a non-doped poly-Si film 31 is formed on the entire surface (FIG. 7 (h)).

(9) Next, As ⁺ ions are implanted by the II technique through the non-doped poly-Si film 31 in the opening 28 to form an n ⁺ diffusion layer (emitter) 33 (FIG. 9 (i)).

As shown in the figure, As ⁺ ions may be implanted also on the collector opening side.

(10) Next, a SiO ₂ film 27 is formed to form a base contact.
To form an opening, and thereafter an emitter electrode, a base electrode and a collector electrode made of an Al film are formed.

As described above, according to the method of manufacturing the bipolar transistor of the embodiment of the present invention, the base lead electrode 24 can be formed by using the poly-Si film 20, so that the n ⁺ diffusion layer (emitter) 33 and the p-type diffusion layer are formed. The (base) 26 can be formed in a self-aligned manner. As a result, the emitter and the base can be formed very close to each other, and the base resistance can be reduced.

Also, the second U-groove portion and the first under the base extraction electrode 24
Since the base region is surrounded by the groove portion 16 of, the base-collector junction capacitance can be reduced.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the parasitic capacitance between the base and collector of the bipolar transistor, the base resistance, and the device.

Therefore, according to the present invention, a fine bipolar transistor can be manufactured at high speed.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view illustrating a bipolar transistor according to a manufacturing method of a conventional example. (Explanation of symbols) 1,11 …… p type Si substrate, 2,12 …… n ⁺ buried layer, 3,13 …… n type epitaxial layer, 4,6,15,18,21,27,30 …… SiO ₂ film, 5,19 …… PSG film, 7,14 …… n ⁺ compensation diffusion layer, 8,26 …… p type diffusion layer (base), 9,33 …… n ⁺ diffusion layer (emitter), 24 …… p ⁺ Compensation diffusion layer (base extraction electrode), 16 …… First U groove, 17 …… Second U groove, 10,20,31 …… Poly Si film, 22,28,29 …… Opening Part, 23 …… BF ₂ ion, 25 …… B ⁺ ion, 32 …… As ⁺ ion, E …… emitter electrode, B …… base electrode, C …… collector electrode.

Claims (2)

[Claims] 1. A step of forming an epitaxial layer of opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, and excavating the epitaxial layer and the substrate to form a first U-groove for element isolation, and Forming a second U-groove shallower than the first U-groove between the first U-grooves, forming a first insulating film in the first and second U-grooves, and further forming the U-grooves Filling the inside with an insulating material, polishing the surface of the epitaxial layer, forming a polycrystalline semiconductor film on the entire surface of the substrate, and forming a second insulating film on the polycrystalline semiconductor film. A step of selectively opening the insulating film to form a first opening, and implanting first impurity ions into the polycrystalline semiconductor film through the first opening to form a base lead electrode. And a second impurity ion of one conductivity type is introduced through the first opening. Forming a base diffusion layer by injecting into the base extraction electrode; forming a third insulating film in the first opening; selectively opening the insulating film and the base diffusion layer to form a semiconductor substrate; Forming a second opening that exposes the surface; forming a fourth insulating film on the inner wall of the second opening, and forming a polycrystalline semiconductor film on the entire surface; and the second opening A third impurity ion of opposite conductivity type is formed through the polycrystalline semiconductor film of the other part to form an emitter diffusion layer of opposite conductivity type in the base diffusion layer. Production method. 2. A semiconductor substrate of one conductivity type is a p-type semiconductor, an impurity of opposite conductivity type is an n-type impurity, the insulating material is a PSG film, and the first, second, third and The fourth insulating film is a SiO ₂ film, the polycrystalline semiconductor film is a poly-Si film, the first impurity ions are BF ₂ , the second impurity ions are B ⁺ , and the third impurities are The method of manufacturing a semiconductor device according to claim 1, wherein the ions are As ⁺ .