JPH0824187B2 - Preventing electrostatic damage to semiconductor devices - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for preventing an active element such as a transistor from being destroyed by static electricity generated when a semiconductor device is manufactured on an insulating substrate.

[Prior Art] In recent years, active elements such as TFTs are often formed in a large-area semiconductor layer formed on an insulating substrate, such as a thin film transistor (TFT) active matrix circuit for driving a liquid crystal display. ing.

In TFT, a polycrystalline Si film is grown on an insulating substrate made of quartz or the like to form a source / drain region and a conductive channel, a gate insulating film is provided thereon, and a gate electrode is formed by using, for example, a polycrystalline Si film. Manufactured by forming.

For example, a TFT for driving a 2-inch color LCD TV
For matrix circuits, 140 cm on a substrate measuring 3 cm x 4 cm.
About 70,000 μm × 140 μm pixels are formed. Each pixel is composed of a transistor and a liquid crystal, and a liquid crystal display is controlled by turning on / off a transistor designated by a matrix to form a television screen.

FIG. 4 shows the positional relationship among a set of transistors 19, 20 and wiring electrodes and bonding pads out of 70,000 transistors.
The gate electrodes of the transistors 19 and 20 have a common second polycrystalline S
The second polycrystalline Si film 7 is formed of the i film 7, and is connected to the first wiring electrode 11 typically made of Al-based metal at the gate contact portion 23 on the transistor 19 side, and the first bonding Connected to pad 13. On the other hand, the drain region is connected to the second wiring electrode also made of Al-based metal at the drain contact portion 22 on the transistor 20 side,
It is connected to the second bonding pad 14. An anti-parallel diode is connected between the first bonding pad 13 and the second bonding pad 14, and when a high voltage is generated, it is absorbed and the transistor is destroyed by the high voltage. Is being prevented.

[Problems to be Solved by the Invention] By the way, in the process of manufacturing a semiconductor device, there is a process step of generating a large amount of static electricity, such as etching using plasma or CVD. The large area of the bonding pad results in the incorporation of a large amount of charge during these plasma processing steps. However, in a semiconductor device such as a TFT formed on an SOI (silicon on insulator) substrate, that is, a substrate in which a semiconductor layer is formed on an insulating substrate, accumulated charges can escape to the substrate. Instead, it flows to the first wiring electrode 11 and the second wiring electrode 12. Since these wiring electrodes 11 and 12 are made of low resistance Al-based metal, the voltage of the first bonding pad 13 is applied to the gate contact portion 23, and the voltage of the second bonding pad 14 is applied to the drain contact portion 22. It is transmitted within a short time. However, since the polycrystalline Si film 7 forming the gate electrode has a higher resistance than the Al-based metal, the gate contact portion 23 and the transistor 20
It takes a certain amount of time for the gates of the above to have the same potential. Therefore, even if the drain contact portion 22 of the transistor 20 has a high potential, there is a period in which the gate maintains the low potential of the old state. When a large potential difference occurs between the transistor 20 and the gate and drain in this way, this transistor is electrostatically destroyed.

[Means for Solving Problems] According to the present invention, a gate electrode connected to a first bonding pad and a second bonding pad are connected when an active element such as a TFT is formed on an insulating substrate. The source / drain electrodes are connected to each transistor by using a short-circuit pattern made of a conductive material layer common to the gate electrode, and after passing through a process step of generating static electricity, the short-circuit pattern is divided into It is a solution to the problem. Specifically, when patterning the gate electrode made of the polycrystalline Si layer, a short-circuit pattern for short-circuiting the gate electrode and the source / drain region is also formed at the same time.

[Operation] In the present invention, after the short circuit pattern is formed, the potential of the first bonding pad 13 is changed to the potential of the gate contact portion 23 and the potential of the second bonding pad 14 through a process step of generating static electricity. Even if occurs in the drain / contact portions 16 and 22, the potential difference between the gate and the source / drain does not occur because the gate and the source / drain regions are connected in a short circuit pattern in each transistor. Therefore, it is possible to prevent electrostatic breakdown of the transistor due to static electricity generated by plasma treatment or the like during the manufacturing process of the semiconductor device.

After the plasma treatment process is completed, the short circuit pattern between the gate and the source / drain is divided, so that the short circuit pattern does not affect the characteristics of the transistor.

[Embodiment] An embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is an enlarged top view of one transistor having a short circuit pattern formed by the electrostatic breakdown preventing method of the present invention, and FIG. 2 is a top view of two adjacent transistors. Further, FIG. 3 shows that the second PSG film 6 and Si ₃ N ₄ are formed on the entire surface of the substrate.
FIG. 3 is a schematic cross-sectional view showing a state in which the patterning of the photoresist film 9 for removing the film 8 and the later-described cut portion 10 has been completed, wherein the view A is the line AA ′ in FIG. 1 and the view B is the same. The lines BB 'and C show the parts corresponding to the lines CC' in FIG. 2, respectively.

As shown in FIG. 3A, the transistor is a normal SOI TFT formed on the first polycrystalline Si film 2 of the substrate 1 made of glass. On the first polycrystalline Si film 2,
The second polycrystalline Si film 7 is formed through the oxide film 3 which is the gate insulating film.
And a N ⁺ -type impurity is selectively introduced into the first polycrystalline Si film 2 to form source / drain regions.

The method for preventing electrostatic breakdown of a semiconductor device according to the present invention is shown in FIGS. 1 and 3A before performing plasma processing on a substrate.
As shown in Figure 2, the second polycrystalline Si forming the gate electrode
This is achieved by branching the film 7 in the middle to form a short-circuit pattern, which is connected to the second wiring electrode via the contact portions 17 and 18 to short-circuit the gate and the source / drain.

After that, a process such as plasma etching of the first PSG film 4 or deposition of the Si ₃ N ₄ film 8 by plasma CVD is performed on the substrate. During these processes, a large amount of charge is generated on the first bonding pad. 13 and second bonding pad 14. Gate contact part
The potential of 23 immediately becomes equal to that of the first bonding pad 13, and the potential of the drain contact portion 16 immediately becomes equal to that of the second bonding pad 14. Here, in the past, since the propagation path of charges to the gate was limited to the second polycrystalline Si film 7 connected to the gate contact portion 23, the gate of each transistor becomes the same potential as the first bonding pad 13. It took a long time until the gate / drain potential difference was generated, which caused electrostatic breakdown of the transistor. However, in the present invention, the second bonding
Electric charges also flow from the pad 14 to the gate through the contact portions 17 and 18 and through the short circuit pattern 7s provided for each transistor. That is, the potential of the gate of each transistor immediately becomes equal to the potential of the second bonding pad 14. Therefore, there is no fear that the transistor will be electrostatically damaged even if a process of forming the Si ₃ N ₄ film 8 by plasma CVD is performed in a later step.

After finishing the process step of generating static electricity, it is necessary to divide the unnecessary short-circuit pattern 7s. This division is performed at the same time when the windows of the bonding pads 13 and 14 are opened. That is, as shown in FIG. 3C, in order to form a contact hole for making a contact with the bonding pad 13, the photoresist film 9 is patterned to form an opening. And as shown in FIG. 3B, the cut portion 10 of the short-circuit pattern 7s.
An opening is also formed in the part facing the. Using this photoresist film 9 as a mask, the Si ₃ N ₄ film 8, the second PSG film 6 and the first PSG film 4 were continuously dry-etched. Here, the bonding pads 13 and 14 are exposed when the etching of the second PSG film 6 is completed, and the short-circuit pattern 7s is exposed when the etching of the first PSG film 4 is completed.

Then, the short circuit pattern 7s is dry-etched using an etching gas such as CF ₄ to remove the cut portion 10.

Since the anti-parallel diodes are connected between the bonding pads such as the first bonding pad 13 and the second bonding pad, even if an excessive voltage is applied between the bonding pads after the device is completed, The transistor will not be destroyed by being short-circuited by this diode.

[Effects of the Invention] According to the method for preventing electrostatic breakdown of a semiconductor device of the present invention,
The short circuit pattern can be formed by the same process as the gate electrode, and the only additional step to the normal process is etching for removing the cut portion 10. Therefore, electrostatic breakdown of the semiconductor device due to generation of static electricity during processing can be prevented while guaranteeing excellent economic efficiency and throughput.

[Brief description of drawings]

1 and 2 are top views showing a wiring pattern formed by the method for preventing electrostatic breakdown of a semiconductor device according to the present invention. FIG. 3 is a schematic cross-sectional view of each portion of a wiring pattern formed by the method for preventing electrostatic breakdown of a semiconductor device according to the present invention. FIG. 4 is a top view showing a part of a conventional TFT matrix circuit. 1 ... Substrate 2 ... First polycrystalline Si film 3 ... Oxide film 4 ... First PSG film 5,12 ... Second wiring electrode 6 ... Second PSG film 7 ... Second polycrystalline Si film 7s ... … Short-circuit pattern 8 …… Si ₃ N ₄ film 9 …… Photoresist film 10 …… Cutting part 11 …… First wiring electrode 13 …… First bonding pad 14 …… Second bonding pad 15,21 …… Source contact part 16,22 …… Drain contact part 17,18 …… (short circuit pattern and second wiring electrode) contact part 19,20 …… Transistor 23 …… Gate contact part

Claims (1)

[Claims] 1. A plurality of active elements are formed in a semiconductor layer on an insulating substrate, and a first region of the active element connected to a first bonding pad and the active element connected to a second bonding pad. Second active region is connected to each active element using a short-circuit pattern composed of a conductive material layer composing the first region and a common conductive material layer, and after passing through a process step of generating static electricity, A method for preventing electrostatic breakdown of a semiconductor device, characterized in that the short circuit pattern is divided to electrically separate the first region and the second region.