JPH0824190B2 - Method for manufacturing thin film transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film transistor, and particularly to a liquid crystal display (LCD), electroluminescence (E).
L) A method for manufacturing a thin film transistor suitable for use in an active matrix such as a display.

[Prior Art] FIGS. 6A and 6B show an example of the structure of a thin film transistor according to the prior art. This thin film transistor is used in an active matrix circuit or the like as shown in FIG.

FIG. 5 schematically shows a planar structure of the active matrix substrate. Gate lines G1, G2, G3, ...
.. runs and the source lines S1, S2, S3, ... Run in the vertical direction so as to intersect these gate lines, and the intersections form a matrix. Drain pads D11, D12, ... D21, D22 ... D31, D32 ... Are arranged corresponding to the respective intersections. These drain pads form the drive electrodes of the liquid crystal cell, for example. Insulated gate field effect transistors Tij are arranged between each drain pad and the corresponding source line Si and gate line Gj.
The voltage of the source line Si is applied to the drain pad Dij according to the signal of j.

These insulated gate field effect transistors T11, T12
..T21, T22 ... T31, T32 ... are shown in FIG.
It is formed by a thin film transistor using amorphous silicon as shown in FIG.

FIG. 6 (A) is an enlarged plan view showing the portion of the transistor T12 of FIG. 5, and FIG. 6 (B) is a plan view of FIG. 6 (A).
FIG. 6 is a sectional view taken along line VI B-VI B in FIG.

With reference to FIG. 6 (B), a conventional method of manufacturing a thin film transistor will be described.

A conductive film is formed on the glass substrate 1 and the drain pad 2 is formed.
And the lower gate electrode 3 is patterned. In order to prevent disconnection of the gate electrode, a conductive layer of a different material is further formed and the upper gate electrode 4 is patterned. Si on it
Insulating film 5 such as O ₂ and hydrogen-added amorphous Si (a-
Si: H) film 6, heavily doped n ⁺ type a-Si: H film 7
Are continuously deposited by the plasma CVD method and patterned into islands. Further, an electrode metal layer is formed and the source / drain electrodes 8a and 8b are patterned. Finally, the n ⁺ -type a-Si: H film 7 on the channel portion is etched to remove the a-Si: H film below.
A channel is formed, leaving only the membrane 6.

[Problems to be Solved by the Invention] However, such a thin film transistor has the following problems.

As understood from the plan view of FIG. 6 (A), the source electrode 8a extends by covering the step formed by the gate insulating film 5 and the a-Si: H films 6 and 7 twice for each bit. Exists A disconnection is likely to occur in these step portions, and a line defect is generated.

An object of the present invention is to provide a method of manufacturing a thin film transistor in which the disconnection of the source electrode is small, which can solve the above problems of the prior art.

The drain electrode 8b covers the step formed by the gate insulating film 5 and the a-Si: H films 6 and 7 and the step formed by the drain pad 2 once to make contact with the drain pad 2. A disconnection is likely to occur at this step portion, and the voltage may not be transmitted to the drain pad.

Another object of the present invention is to provide a method of manufacturing a thin film transistor in which the disconnection of the drain electrode is small, which can solve the problems of the conventional art.

When the gate insulating film 5 and the a-Si: H films 6 and 7 are deposited, the material of the drain pad (ITO or the like) may be damaged by plasma and the transparent electrode may become cloudy.

Still another object of the present invention is to provide a method of manufacturing a thin film transistor capable of solving such problems of the prior art and reducing the occurrence of clouding of the drain pad.

[Means for Solving the Problems] FIGS. 1 (A) and 1 (B) show a basic embodiment of the present invention in comparison with an example according to the prior art. 1A and 1B are sectional views taken along the source line. As can be seen from FIG. 5, the source line must intersect the gate line. FIGS. 1 (A) and (B) show a portion that covers and extends a step due to intersection.

In the figure, 11 is a substrate such as a glass plate, 13 is a lower gate electrode,
14 is an upper gate electrode, 13a is a lower source correction electrode, 14a is an upper source correction electrode, 15 is a gate insulating film, 16 is a channel layer made of a semiconductor thin film layer, 17 is a contact layer made of a high impurity concentration semiconductor thin film layer, 18a is a source electrode line.

In the case of the conventional technique, as shown in FIG. 1B, the source electrode line 18a extends so as to cover the large step h1 formed by the gate insulating film 15, the channel layer 16 of the semiconductor thin film layer, and the contact layer 17. It was

In the case of the embodiment of the present invention, as shown in FIG.
The lower source correction electrode 13a and the upper source correction electrode 14a are the gate insulating layer 15 and the channel layer 1 of the semiconductor thin film layer thereon.
6, formed adjacent to the contact layer 17. Therefore, the step difference for the source electrode is the first height h ₁ formed by the gate insulating film 15, the channel layer 16 of the semiconductor thin film layer, and the contact layer 17, and the lower source correction electrode 13a and the upper source correction electrode 14a. The difference Δh = h ₁ −h ₂ between the second heights h ₂ is small, which is small.

In addition, a drain pad protection electrode is formed on the drain pad with the same material layer as the lower gate electrode 13, and plasma CVD is performed.
Inside, the drain pad can be protected and then removed.

[Operation] The disconnection at the step portion strongly depends on the height of the step. If the step is small, the step coverage increases,
Breakage can be reduced.

Further, by preventing the drain pad from coming into direct contact with plasma during plasma CVD, accidents such as clouding of the drain pad can be reduced.

[Example] FIGS. 2 (A), (B), 3 (A), (B), and 4th.
A manufacturing method of a thin film transistor according to an embodiment of the present invention is shown in FIGS. In each figure, (A) is a plan view,
(B) shows a sectional view.

In FIGS. 2A and 2B, first, the drain pad 12 of the transparent electrode is patterned on the glass substrate 11.
Further, a conductive layer is formed, and the lower gate electrode 13, the lower source correction electrode 13a, and the lower drain correction electrode 13b are patterned. At this time, a drain pad protection electrode 13c is further formed on the drain pad 12. Then the upper gate electrode 1
4. The upper source correction electrode 14a and the upper drain correction electrode 14b are formed of a material different from that of the lower gate electrode 13 and patterned (not formed on the protective electrode 13c on the drain pad at this time).

Next, as shown in FIGS. 3A and 3B, the SiO ₂ gate insulating film 15 and hydrogen-doped amorphous silicon (a-
A channel layer 16 made of a Si: H) film and a contact layer 17 made of an n ⁺ type a-Si: H film are continuously deposited by a plasma CVD method.
These deposited films are patterned into an island shape by dry etching. At this time, the drain pad protection electrode 13c
Is also simultaneously etched (the lower side correction electrodes 13a, 13b are not etched because they are covered by the upper side correction electrodes 14a., 14b).

Next, as shown in FIGS. 4A and 4B, the source electrode 18a and the drain electrode 18b are patterned, and finally, the n ⁺ type a on the channel portion exposed between the source electrode 18a and the drain electrode 18b is formed. -The contact layer 17 of the Si: H film is dry-etched.

ITO, SnOx, or the like is used as the material of the drain pad, and is mainly formed by a sputtering method or a vapor deposition method. The film thickness is
For example, 1000 to 2000Å.

As the material of the lower gate electrode 13, Mo, Ti, W, Pt or the like that can be dry-etched with CF ₄ or the like can be used.
The film is formed mainly by the sputtering method and the vapor deposition method. The film thickness is
It is 1000 to 2000Å.

As the material of the upper gate electrode 14, Cr, Al, ITO, Au or the like which is not dry-etched with CF ₄ or the like can be used. The film is formed mainly by the sputtering method and the vapor deposition method. The film thickness is, for example, 1000 to 2000Å.

SiNx, SiOx, or the like is used as the material of the gate insulating film 15, and is mainly formed by the plasma CVD method. The film thickness is, for example, 3000 to 5000Å.

The thickness of the a-Si: H film 16 to be the channel layer 16 is, for example, 50.
The film thickness of the n ⁺ -type a-Si: H film serving as the contact layer 17 is 0 to 2000Å, for example, 100 to 300Å.

The material of the source electrode 18a and the drain electrode 18b is Mo, Al, Ti,
W, ITO or the like can be used, and the film is mainly formed by a sputtering method or a vapor deposition method. The film thickness is, for example, 3000 to 5000Å.

Examples of dry etching conditions include CF ₄ or CF ₄
Using + O ₂ gas, vacuum degree is 5-100pa, power density is 10-5
Use 0 mW / cm ² .

According to this embodiment, the following advantages are obtained as compared with the prior art.

(1) Reduction of source electrode disconnection Since most of the source electrode is formed at the same time with the same material as the gate electrode when forming the gate electrode, most of the source electrode is composed of a three-layer structure. The number of wire breaks in that part is smaller than that of No.

Further, at the intersection of the source electrode and the gate electrode, in the conventional one, the source electrode must cover the step difference corresponding to the film thickness of the gate insulating film and the two layers of a-Si: H film,
The disconnection often occurred at the step. However, in this embodiment, since the source correction electrode and the island of the a-Si film are formed in contact with each other, the step difference is reduced by the film thickness of the source correction electrode as shown in FIG. The number of electrode breaks is reduced.

(2) Reduction of disconnection of drain electrode Since the structure is such that the drain correction electrode is formed at the same time when the gate electrode is formed, the step difference of the drain electrode is reduced and the disconnection is reduced for the same reason as above.

(3) Preventing alteration of drain pad material The drain pad material (ITO, etc.) may become cloudy due to plasma during plasma CVD deposition. In this embodiment, since the drain pad is covered with the drain pad protection electrode 13c at the time of deposition, the drain pad does not become cloudy depending on the plasma conditions.

(4) No increase in the number of steps The source correction electrode, the drain correction electrode, and the drain pad protection electrode can be patterned simultaneously with the gate electrode by changing the shape of the photomask. The drain pad protection electrode on the drain pad is a dry a-Si film. Since the etching is performed at the same time as the etching, the number of steps is not increased as compared with the conventional one.

[Effects of the Invention] As described above, according to the present invention, the step difference of the step portion is alleviated by the source correction electrode, and the disconnection of the source electrode line can be reduced.

Similarly, the drain correction electrode can reduce disconnection of the drain electrode.

Further, the drain pad protection electrode can reduce alteration of the drain pad.

[Brief description of drawings]

1 (A) and (B) are cross-sectional views showing an embodiment of the present invention in comparison with the prior art, FIGS. 2 (A), (B), 3 (A), (B), 4 (A) and 4 (B) are views for explaining each step of the method for manufacturing a thin film transistor according to the embodiment of the present invention, in which (A) is a plan view, (B) is a cross-sectional view, and FIG. FIG. 5 is a diagram schematically showing an active matrix circuit, FIGS. 6 (A) and 6 (B) are enlarged diagrams showing a conventional thin film transistor portion in FIG. 5, and FIG. (B) is a sectional view. In the figure, 11 ... substrate 12 ... drain pad 13 ... lower gate electrode 13a ... lower source correction electrode 13b ... lower drain correction electrode 13c ... drain pad protection electrode 14 ... upper gate electrode 14a ... … Upper source correction electrode 14b …… Upper drain correction electrode 15 …… Gate insulating film 16 …… Channel layer 17 …… Contact layer 18a …… Source electrode 18b …… Drain electrode

Claims (2)

[Claims] 1. A method of manufacturing a thin film transistor in which a gate electrode layer, a gate insulating film, a channel layer, and a source electrode / drain electrode layer are laminated on a substrate, and the gate electrode and the gate are formed at the same time when the gate electrode layer is formed on the substrate. A step of forming a source correction electrode and a drain correction electrode at a position adjacent to the insulating film; and a step of forming a gate insulating film and a channel layer so as to cover the gate electrode and contact the source correction electrode and the drain correction electrode. And a step of forming a source electrode on the source correction electrode and the channel layer and forming a drain electrode on the drain correction electrode and the channel layer when forming the source electrode / drain electrode layer. Method of manufacturing thin film transistor. 2. A drain pad of a transparent electrode on the substrate, wherein the gate electrode layer is a lower gate electrode layer of a first material and an upper gate electrode layer of a second material different from the first material. And, in forming the lower gate electrode layer, a drain pad protective electrode is formed on the drain pad, the channel layer is formed by depositing amorphous silicon by plasma CVD, and then patterned by dry etching, The method of manufacturing a thin film transistor according to claim 1, wherein the protective electrode on the drain pad is also etched at the same time.