JPH0824249B2 - Control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit for a SEPP type power amplifier, and more particularly to a bias control circuit for keeping a bias current stable against temperature changes and switching a bias at high speed.

[0002]

2. Description of the Related Art Conventionally, a bias control circuit for keeping the bias of a power amplifier constant against temperature changes has been considered. FIG. 2 shows a block diagram of the general bias control circuit. The detection circuit 1 includes an output transistor TR1 of a power amplifier which constitutes a push-pull circuit of the power amplifier.
The voltage drop caused by the current flowing through the emitter resistances RE1 and RE2 of TR2 is detected, the difference between them is amplified and input to the peak hold circuit 2. The peak hold circuit 2 holds the maximum value during the output of the detection circuit 1 and inputs it to the error circuit 3. The output of the error circuit 3 controls the bias supply transistor 9 of the bias circuit 15 of the power amplifier so that the output power (hold voltage) of the peak hold circuit 2 becomes equal to the voltage of the reference voltage 4. This error circuit 3 generally takes the form of an integrating circuit. The bias supply transistor 9 also functions as a variable impedance element.

FIG. 3 shows the signal waveform of each part. The output signal a of the detection circuit 1 with respect to the power amplifier output signal VOUT
Is a signal waveform that causes a peak at the VOUT zero crossing as shown in the figure. This peak value is speaker 1
When the current 10 does not flow in 4, this value is the emitter resistance RE due to the bias current (idling current) when there is no signal.
1, corresponding to the value of the voltage drop at RE2.

[0004]

In the conventional bias control circuit, when the bias is switched according to the level of the input audio signal, it can be achieved by changing VR of the reference voltage 4 in FIG. However, there is a non-linear peak hold circuit in the bias control circuit loop. As shown in FIG. 4, the hold circuit has different time constants between the charge path and the discharge path. In the peak hold circuit, the time constant t2 of the discharge path is longer than the time constant t1 of the charge path. Generally, the value of t2 is the lower frequency of the voice band (20H
z), the hold signal has a ripple of about several seconds so that there is no problem. Therefore, when the reference voltage 4 is switched to the direction in which the bias increases (the idling current increases), the followability of the bias control circuit becomes extremely poor. Further, since the bias control circuit may act so as to correct the variation (ΔVBE≈−2 mV / ° C.) of the power transistors TR1 and TR2 due to the temperature of VBE1 and VBE2, the bias control circuit loop itself has a slow system configuration. ing.

[0005]

SUMMARY OF THE INVENTION The present invention is a feedback bag.
Switch the level of the detected signal in the control circuit
Hold the peak or Min level through the output circuit
Hold circuit and the hold circuit
The error of comparing the signal level with a predetermined reference level to get an error.
Switching between the output of the difference circuit and the output of the error circuit
Equipped with a switching circuit that switches the control level for control
The level of the control signal output from the error circuit.
And change the feedback control loop gain to about 1
It is a control circuit configured to maintain a constant value . Also, the present invention
The voltage drop due to the current flowing through the emitter resistance of the power transistor is detected, and the peak hold or Mi of the detected voltage is detected.
A bias control circuit that performs n-holding and controls the bias voltage so that the hold voltage becomes equal to a preset reference voltage . Controlled system
Along with obtain cut conversion by the control output of the first attenuator,
A control circuit for an earlier SL first gain changing amount of correction of the attenuator to the second attenuator in front of the peak hold (or Min hold) circuit.

[0006]

In the control circuit for bias or the like having the above-mentioned structure,
The bias level can be switched without changing the reference voltage 4, and the hold voltage does not have to follow the bias switching at this time, so that bias control can be performed at high speed.

[0007]

1 is a block diagram of an embodiment of the present invention. In the figure, the output transistor TR of the power amplifier
The detection circuit 1 detects the current indicated by Vout in FIG. 3 from both ends of the emitter resistors RE1 and RE2 of 1 and TR2. The detected signal shown in a of FIG. 3 is peak-held by the peak hold circuit 2 via the second attenuator 5 as shown in FIG. 3b, and is compared with the reference voltage 4 by the error circuit 3 to determine the first attenuator 6 Is connected to the bias supply transistor 9 of the bias circuit 15 via the output circuit 7 and operates to determine the bias of the output transistors 7TR1, 8TR2. The switching signal generation circuit 19 is
The input signal Vin is amplified by the amplifier 16 and the peak detector 1
The comparator 18 determines the state of the level of the input voice signal VIN through the comparator 7, and generates a switching signal. There are the following three signal level states for determination. No signal and minute signal level Normal audition signal level (output about 1 W) Large output signal level Next, in the states of to, the first attenuator 6 inserted after the error circuit 3 and before the bias circuit 15,
And the second attenuator 5 inserted in the preceding stage of the peak hold circuit 2 are switched by the interlocking operation switch 12 and switch 13, respectively.

At the time of and, the switch 13: ON ... The first attenuator: 1 /
N (= R2 ′ / (R1 ′ + R2 ′)) switch 12: OFF ... Second attenuator: 1 In this state, the output of the detection circuit 1 is gain-multiplied by 1 in the second attenuator 5 and peak-held. It Mistake
The difference circuit 3 outputs the control voltage so that the peak hold voltage and the reference voltage VR become equal. This output has its gain increased by 1 / N in the first attenuator 6 and is input to the bias circuit to stabilize the bias. The voltage generated at the emitter resistors RE1 and RE2 at this time is VB. This V
The value of the bias current IB due to B is small, and the power amplifier operates in class AB.

At this time, switch 13: OFF ... First attenuator: 1 switch 12: ON ... Second attenuator: 1 /
N (= R2 / (R1 + R2)) In this state, the gain of the first attenuator is N times that of the above cases and. Therefore, the bias circuit 15 is controlled N times, and the bias voltage becomes NVB. At this time, the detection voltage of the detection circuit 1 also increases N times, but the second
Since it is multiplied by 1 / N by the attenuator, the operating voltage of the peak hold circuit 2 and the error circuit 3 in the subsequent stage does not change. Therefore, the peak hold circuit 2 and the error circuit 3 need only follow the variation of VBE due to the temperature change of the power transistors 7 and 8. Emitter resistance RE
1, the bias current IB is applied to the voltage NVB generated in RE2.
Of the value increases, the power amplifier performs the A-class operation.

In the above-described embodiment, the peak hold circuit as shown in FIG. 4 is used, but the two inputs of the detection circuit 1 are reversed and the peak hold circuit 2 is replaced by the Min hold circuit. However, a similar bias control circuit can be realized. Further, the attenuators 5 and 6 are configured as shown in FIG.
By making it possible to determine the signal level of the internal comparator 18 in a plurality of patterns,
Furthermore, it is possible to switch a plurality of bias current values.

[0011]

As described above, according to the present invention, since the control loop gain is held substantially constant even when the bias is switched, the peak hold voltage and the error circuit output are in a stable state and the control loop gain is immediately increased. The circuit operation is kept stable and high-speed switching is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a bias control circuit of the present invention.

FIG. 2 is a block diagram of a conventional bias control circuit.

FIG. 3 is an operation waveform of a bias control circuit.

FIG. 4 is a peak hold circuit.

FIG. 5 is a configuration diagram of an attenuator.

[Explanation of symbols]

1 Detection Circuit 2 Peak Hold Circuit 3 Error Circuit 4 Reference Voltage 5 Second Attenuator 6 First Attenuator 7, 8 Power Transistor 9 Bias Supply Transistor 10, 11 Constant Current Source 12, 13 Changeover Switch 14 Speaker 15 Bias Circuit 16 Amplifier 17 Peak detector 18 Comparator 19 Switching signal generation circuit

Claims (2)

[Claims] 1. A feedback control circuit comprising a circuit for switching the level of a detected signal,
Is a hall circuit that holds the Min level,
Signal level held by the field circuit and a predetermined reference level
An error circuit that obtains an error by comparing
Switch the output and switch the control level for feedback control
Equipped with a switching circuit for switching, and output from the error circuit
The level of the control signal
The control loop gain should be kept approximately constant.
And a control circuit characterized by: 2. A voltage drop due to a current flowing through an emitter resistance of a power transistor is detected, peak hold or Min hold of the detected voltage is performed, and a bias voltage is controlled so that the hold voltage becomes equal to a preset reference voltage. A bias control circuit, which detects the input audio signal level, determines the state of the signal level, and
A control output supplied to the first attenuator and a peak hold (or Min hold)
The earlier SL to a second attenuator in front of the circuit 1
Control circuit according to JP <br/> Features performing the gain switching component of the correction of the attenuator.