JPH0827330B2 - Integrated circuit test method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to integrated circuit test circuits.

2. Description of the Related Art As integrated circuits have become larger and larger, multi-functional blocks have been integrated into one chip.

With the multi-functional one-chip technology, it is possible to reduce the mounting area and downsize the device, and the application fields of integrated circuits are expanding.

With the multi-functionalization into one chip, a circuit in which an output signal of one functional block becomes an input signal of another functional block is generated. When testing such a large scale integrated circuit (LSI), it is necessary to operate one functional block so that the logic level of the signal to the next block becomes "H" and "L". . This requires a long test pattern and a long test time.

Problems to be Solved by the Invention When an integrated circuit including a plurality of functional blocks is tested as one chip, an increase in the number of test patterns and an increase in test time become problems. As a test method for eliminating this inconvenience, a method of individually testing a plurality of functional blocks can be considered. According to this method, the test time can be shortened, but the number of test terminals increases.

Means for Solving Problems The present invention has an object to enable a test for each functional block without adding a test terminal to shorten the test time and improve the testability.

In the test mode, the terminals that are directly input or output from the outside to the tested functional block to be tested are used as they are as the input terminals or output terminals of the test signal,
The input signal from the other functional block to the tested functional block is used as the input terminal by switching the terminal used as the output terminal of the functional block other than the tested functional block in the normal operation mode. Input signal directly from the outside, output signal from the functional block under test to other functional block is output by switching the terminal used as the input terminal of the functional block other than the functional block under test in the normal operation mode. It is used as a terminal and directly output to the outside.

Operation According to the integrated circuit of the present invention, the terminal used in the normal use mode is used as the test terminal in the test mode, and the test signal is time-divided. Without adding to
It is possible to test integrated circuits, improving testability and reducing test time.

Embodiment (Embodiment 1) FIG. 1 shows an integrated circuit composed of two functional blocks. In the normal operation mode, the terminal A is an input terminal of the block 1, the terminal B is an output terminal, the terminal C is an input terminal of the block 2, and the terminal D is an output terminal. Between blocks 1 and 2, there are input and output signals, respectively. 2 and 3 show an embodiment of the present invention in which a test circuit for individually testing is added to two functional blocks.

Note that FIG. 2 shows an example of a mode for testing the block 1.

When testing the block 1, the contact of the changeover switch SW is opened and closed as shown in the figure, and the test timing signal T1 becomes "H" and the test timing signal T2 becomes "L".
Becomes The input signals of the block 1 are a signal directly input from the terminal A and a test signal input from the D terminal. By the input of this test signal, the block 2 is operated in the normal operation mode, and the same condition as when the output thereof is input to the block 1 is established. The output signal from block 1 is
Since the test timing signal T2 is "L", it is directly output from the terminal B.

That is, in the normal operation mode, the signal output from the block 1 to the block 2 is output as a test signal to the C terminal at the test timing, and this signal can be tested.

Therefore, in testing the block 1, the output of the block 1 can be directly tested without operating the block 2 by inputting the output of the block 2 into the block 1.

FIG. 3 shows an example of testing block 2. When testing the block 2, the test timing T2 becomes "H" and T1 becomes "L". Further, the changeover switch between the block 1 and the block 2 is also changed so that the SW has an opening / closing relationship opposite to that in the test of the block 1.

When testing the block 2, signals are input from the terminals B and C and signals are output from the terminals A and D.

That is, the test signal can be directly input and output to the block 2 without going through the block 1. As shown in FIGS. 2 and 3, in the normal operation mode,
By using the terminal that is the input terminal as the output terminal in the test mode, and by using the terminal that is the output terminal as the input terminal in the test mode in the normal operation mode,
The terminals used in the normal operation mode are shared in the test mode, so there is no increase in special terminals for test signals, and the input and output terminals are used as they are as input and output terminals. The number of switches is smaller than that of the case, and the circuit for switching the switches is simple. Thereby, the increase in chip size can be suppressed as much as possible. Further, since the signal between the blocks is directly input and output from the terminal and tested, the testability can be improved and the test time can be shortened.

In the normal operation mode, the test timing signals T1 and T2 become "L", and the changeover switch between the blocks is switched to the connection in the normal operation mode (connection in FIG. 1).

(Embodiment 2) FIG. 4 shows an integrated circuit composed of three blocks. The terminals E, G, I are input terminals for the blocks 3, 4, 5 and the terminals F, H, J are output terminals for the blocks 3, 4, 5.

FIGS. 5, 6, and 7 show an embodiment of the present invention in which each functional block is tested, a test signal is time-divisionally sent to the same signal line, and a plurality of signals are sent and received.

FIG. 5 shows an example in which a test circuit for testing the block 3 is added.

When testing the block 3, the test timing signal T3 becomes "H" and the test timing signals T4 and T5 become "L". When the block 3 is tested, signals are input to the block 3 from the terminals E, H, and J, and the output of the block 3 is output through the terminals F, G, and I.

FIG. 6 shows a test circuit diagram when the block 4 is tested. When testing the block 4, the test timing signal T4 becomes "H" and the test timing signals T3, T5
Becomes “L”. During the test mode of block 4, terminal G, terminal F and terminal J are input terminals, and terminal H and terminal E
And the terminal I becomes an output terminal.

FIG. 7 shows a test circuit diagram when the block 5 is tested. In the test mode for testing the block 5, the test timing signal T5 becomes "H" and the test timing signals T3 and T4 become "L". When testing the block 5, terminal I, terminal F, and terminal H are input terminals, and terminal J
The terminals E and G serve as output terminals. In the normal operation mode, all of the test timing signals T3, T4, T5 are set to "L", and the changeover switch SW is changed so that signals are transmitted and received between the blocks to establish the circuit state of FIG.

Although the integrated circuit of the two functional blocks and the three functional blocks is shown in the above embodiment, the test signal line should be used in a time division manner when the number of functional blocks is increased and the number of signal lines between the blocks is increased. As a result, the effect of reducing the number of test terminals becomes more remarkable.

Advantageous Effects of Invention According to the integrated circuit test method of the present invention, the signal terminal in the normal operation mode and the test terminal in the test mode are shared, and the test signal is used in a time division manner.
It is possible to test an integrated circuit composed of multiple blocks for each functional block without specially adding terminals for test signals, improving testability and reducing test time. It can be measured.

[Brief description of drawings]

FIG. 1 is a diagram showing an integrated circuit having two functional blocks, FIG. 2 is a diagram showing an example of a test circuit in a mode for testing one block of an integrated circuit composed of two functional blocks, and FIG. FIG. 4 is a diagram showing an example of a test circuit in a mode for testing the other block of an integrated circuit composed of functional blocks, FIG. 4 is a diagram showing an integrated circuit having three functional blocks, and FIG. 5 is an integrated circuit composed of three functional blocks. FIG. 7 is a diagram showing an example of a test circuit in a mode for testing a first block of the circuit, FIG. 6 is a diagram showing an example of a test circuit in a mode of testing a second block of an integrated circuit including three functional blocks, and FIG. The figure is a diagram showing an example of a test circuit in a mode of testing a third block of an integrated circuit including three functional blocks. A to J ... terminals, SW ... switching switch.

Claims (1)

[Claims] 1. A system comprising two or more functional blocks,
When testing an integrated circuit that has a signal that spans each functional block, in test mode, the pin that is directly input or output from the outside to the functional block under test is directly used as the input or output pin of the test signal. The input signal from the other functional block to the tested functional block is used as the input terminal by switching the terminal used as the output terminal of the functional block other than the tested functional block in the normal operation mode. Output from the functional block under test to another functional block by switching the terminal used as the input terminal of the functional block other than the functional block under test in the normal operation mode. A test of an integrated circuit characterized by being used as an output terminal and outputting directly to the outside. Method.