JPH0827466B2 - Display device - Google Patents

Description

The present invention relates to a display device, and more particularly to a display device suitable for liquid crystal display.

[Conventional technology]

TFT for each pixel in a liquid crystal display TFT panel
There is known an active matrix panel with built-in peripheral circuits in which elements and peripheral circuits for driving them are formed on the same substrate. For example, Japanese Patent Laid-Open No.
2088, JP-A-60-26932 and the like.

Further, a configuration is known in which a plurality of TFT elements are arranged in one pixel in order to give redundancy to the TFT panel and improve the yield of a large screen panel. Japanese Patent Application Laid-Open No. Sho 63
-186216, JP-A-61-21034 and the like can be mentioned.

Further, as a division exposure method as a method for manufacturing a large-screen TFT panel, there is JP-A-61-180275.

[Problems to be Solved by the Invention]

In the above-mentioned conventional technology, no special consideration is given to the structure of the TFT for each pixel and the TFT for the peripheral circuit, and therefore it is difficult for both TFTs to have the best characteristics. There is.

An object of the present invention is to provide a display device having excellent characteristics.

Another object of the present invention is to provide a TFT for each pixel and a TFT for peripheral circuits.
In order to provide a panel exhibiting excellent properties, the optimum structure is formed by a simple method.

[Means for solving the problem]

A feature of the present invention for achieving the above object is that a display region and a peripheral circuit region for driving the display region are formed on the same substrate, and the display region is composed of a plurality of first regions arranged in a matrix. It has a semiconductor element, and the peripheral circuit region has a plurality of second semiconductor elements, and the minimum processing dimension of the first semiconductor element is smaller than the minimum processing dimension of the second semiconductor element. The withstand voltage of the first semiconductor element is smaller than that of the second semiconductor element. Furthermore, the first
The leak current of the semiconductor element is smaller than that of the second semiconductor element.

The above-mentioned objects / features of the present invention and objects / features of the present invention other than the above will be more apparent from the following description.

[Action]

In order to achieve the above object, the fine processing rule of the TFT of the pixel portion is formed to be smaller than the fine processing rule of the TFT of the peripheral circuit portion. Here, the fine processing rule is the minimum processing dimension (size of Si island, width and length of gate, contact hole, width of wiring layer) for forming a TFT and a margin for mask alignment of these. Means dimensions.

Further, therefore, in the photolithography process in the manufacturing process, the peripheral circuit portion having a large processing rule is subjected to the batch exposure, and the pixel portion having the small processing rule is subjected to the fine processing by the divided exposure.

In an active matrix panel with a built-in peripheral circuit for a liquid crystal display device, the features of the pixel portion and the peripheral circuit portion are as follows.

(1) If the TFT size of the pixel portion is reduced, the aperture ratio can be increased and a clear image can be obtained. In high-definition display devices, this tendency is strongly desired. On the other hand, the peripheral circuit portion has few restrictions on the processing size of the TFT, and a relatively large element can be used.

(2) As shown in FIGS. 1 (b) and (c) described later, the pixel portion is a two-dimensional repetition of the same pattern, and the photolithography process is divided into a plurality of times for one substrate. Fine processing is possible by repeating alignment and exposure. On the other hand, in the peripheral circuit portion, the same pattern is often not repeated, such as the lead-out wiring portion, and the photomask needs to be changed each time the divided exposure is performed, resulting in poor workability. For this reason, it is desirable that the peripheral circuit region for one panel on the substrate be subjected to a single exposure and a batch exposure method.

(3) In terms of TFT characteristics, the leak current (off-current) can be reduced in the pixel portion by reducing the TFT size, and a clear image can be obtained. In the peripheral circuit part, the size of the TFT can be increased to increase the breakdown voltage between the source and drain and increase the drive capability.

(4) As the substrate for the TFT panel, a glass substrate having a strain point of about 550 to 650 ° C. is generally used. This glass substrate is deformed by heat treatment during the manufacturing process. In particular, the problems of bending and shrinkage are large, and the dimensional shift is large in the peripheral portion of the glass substrate. Since the pixel part is located in the center of the glass substrate, microfabrication is easy and the TFT size can be reduced, but the peripheral circuit part is located in the peripheral part of the glass substrate. It can be easily created by increasing.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIGS. 1 (a), (b), (c) and (d) are schematic plan views of a TFT substrate for liquid crystal display having a built-in peripheral circuit according to an embodiment of the present invention, which is a partial exploded perspective view and its plan view. FIG. 3 is a perspective sectional view of a pattern and a color liquid crystal display device. Reference numeral 10 is a glass substrate having a strain point of 645 ° C. and a size of 60 ^□ × 1.1t. Reference numeral 11 is a pixel area which is a display area in which TFTs for switching of each pixel are arranged in a matrix, and is 48 mm in width and 36 mm in height. Each pixel of 50 μm ^□ is 960 dots in width, 720 dots in height, and a total of 690,000 are arranged. Has been done. A polycrystalline silicon TFT with a minimum size of 3 μm is installed in this pixel. TFT
Is a MOS structure and its processing dimensions are gate length 10 μm and gate width 3
μm. Reference numerals 12 and 13 denote peripheral circuit regions which are regions other than the display region for driving the pixel TFT, and about 20,000 polycrystalline silicon TFTs having a minimum dimension of 6 μm are arranged. 12 is a scanning line driving circuit including a vertical shift register,
A signal line drive circuit 13 is composed of a sampling transistor, a division matrix and a horizontal shift register. Typical TFT processing size is load MOS gate length 30μ
m, gate width 10 μm, driver MOS gate length 6 μm, gate width 50 μm.

The active matrix substrate formed in this embodiment is used as a color liquid crystal display device as shown in FIG. 1 (d). A thin film transistor 502 is formed in the vicinity of an intersection of the signal electrode 504 and the scanning electrode 503 formed in a matrix on the glass substrate 501, and drives the pixel electrode 501 made of a transparent electrode. A counter electrode 506 made of a transparent electrode and a color filter 507 are formed on a glass substrate 508 facing each other with a liquid crystal layer 506 being an electro-optical material interposed therebetween, and a polarizing plate 5 is provided so as to sandwich the pair of glass substrates 501, 508.
05 is provided. As a result, a pixel serving as a display body is formed. By adjusting the transmission of light from the light source at the pixel electrode 501, a color liquid crystal display device driven by a thin film transistor (TFT) is formed.

FIG. 2 shows a schematic sectional view of the TFT. Pixel TFTs and peripheral circuit TFTs are also manufactured in exactly the same process except for the plane dimensions (patterns).

A 60 nm thick polycrystalline silicon film is formed on the surface of the glass substrate 20.
21 is formed by a low pressure CVD method with a substrate temperature of 550 ° C, and further 600 ° C, 20
After annealed in a nitrogen atmosphere for a period of time, patterning was performed by photolithography. This patterning size differs between the pixel TFT and the peripheral circuit TFT as described above. Next, a silicon oxide film 22 having a film thickness of 120 nm as a gate insulating film and a polycrystalline silicon film 23 having a film thickness of 200 nm as a gate electrode were deposited and patterned by photolithography.
The pattern size is the above-mentioned dimension, and the minimum processing dimension of the pixel TFT section is smaller than that of the peripheral circuit TFT section. After that, the source region 24 and the drain region 25 were formed by ion implantation / annealing of phosphorus by the self-aligning method which is widely used today. Then, a transparent ITO electrode and an aluminum wiring layer were formed.

Table 1 shows the characteristics of the TFT formed by the above method. 1
The average value of 5 points on the board and the measurement of 3 boards is shown. Pixel part TFT
The feature is that the off current is small, which is due to the fine processing of the TFT. On the other hand, the characteristics of the TFT in the peripheral circuit part are that the breakdown voltage between the source and drain is high, and the carrier mobility is high. This is because the TFT size is large and local breakdown and punching of the polycrystalline silicon film are caused. This is because the through can be prevented and the loss of carrier mobility on the surface of the polycrystalline silicon layer is reduced. As for the breakdown voltage, the TFT for the pixel section is about 10 to 20V, and the peripheral drive circuit TFT
About 30V or more is desirable.

Example 2 Next, the screen size is 14 ″ (commonly known as the size, 268.8 mm to be exact).
An example applied to a large screen liquid crystal display device having a size of × 187.2 mm and a diagonal of 12.9 ″ will be described with reference to FIG.

Using the glass substrate 30 having a size of 300 × 235 mm ^2, a TFT panel with a built-in peripheral circuit was formed in the same manner as in Example 1. However, the size of one pixel is 240 × 80 μm ² , the number of pixels is 1120 × 780, and the TFT size of the pixel part 31 is 50 μm in gate length, 8 μm in gate width, and TF in the peripheral circuit part 32.
The size of T is 50 μm in gate length and 50 μm in gate width, the minimum wiring width is 10 μm in both, and the aperture ratio of the pixel is 60.5%.
Is.

The manufacturing process is the same as that of the first embodiment, but in the photolithography, as shown in FIG.
The (scanning line drive circuit and the signal line drive circuit) were collectively exposed, and the pixel portion 31 was divided into 12 times. That is, first, the scanning line drive circuit and the signal line drive circuit are exposed by collective exposure, and then the pixel portion 31 is divided into 12 sections indicated by dotted lines using a 5 ″ photomask. In order to prevent the disconnection of the scanning line and the signal line at the boundary of, the following method is used as shown in Fig. 4. First, the photoresist is a negative type,
The area of divided exposure was exposed by overlapping by 10 μm or more ((a) in FIG. 4) which is the same as the wiring width W. As a result, it is possible to leave the photoresist in the ultraviolet irradiation portion (hatched portion b) in the first divided exposure and the ultraviolet irradiation portion (hatched portion c) in the second divided exposure at least once. It is possible to prevent wiring breakage.
The double-irradiated portion of the ultraviolet light is almost surrounded by the normal single-irradiated portion of the ultraviolet light, which does not adversely affect the pattern accuracy. As a result, good wiring connection can be achieved without special consideration for the shape of the connection pattern at the boundary of the divided exposure areas.

This method enables highly precise pattern formation on large screen substrates.

In Example 2, the pixel division was tried as a method for improving the yield of the TFT panel. In addition, to improve the TFT characteristics, especially to reduce the off current, the gate division structure (multi-gate structure)
TFT is adopted.

FIG. 5 shows a plane pattern of pixel division. The manufacturing method is the same as that of the second embodiment, but one pixel 50 is divided into two upper and lower regions by the scanning line 51, and two TFTs 52 are provided, one in each region.
Installed a and 52b. As a result, even if one TFT is damaged, half the area of one pixel is turned on and off, making the defect less noticeable. The structure of the TFTs 52a and 52b is also the gate electrode.
53a and 53b were divided into 3 by 8 μ pitch. In addition, 54 is both TFT52
Signal lines 55a and 55b common to a and 52b are transparent electrodes (ITO) connected to the source region of the TFT. With this structure, the aperture ratio of one pixel 50 is 49.7%, and practically sufficient brightness can be obtained. The gate division structure (multi-data electrode structure) can reduce the off current by half,
A high-quality image can be obtained with a small change in brightness on the screen as a liquid crystal display device.

The present invention relates to a pixel portion and a peripheral circuit in a liquid crystal display device.
Not only TFT, but also various sensors with built-in drive circuit, for example,
It can also be applied to image sensors, pressure sensors that utilize the piezoresistive effect of silicon single crystals, and thermal recording heads.

Further, FIGS. 6 and 7 are photomask plane pattern diagrams showing different pattern sizes of the pixel portion and the peripheral circuit portion of the TFT-LCD.

It is clear that the size of the Si island and the width of the Al wiring are different between the pixel portion and the peripheral circuit portion.

That is, FIG. 6 shows the pattern of the area A shown in FIG. 1 (c), and FIG. 7 shows the pattern of the area B shown in FIG. 1 (c).

Some of the features of the present invention are listed as follows: 1. In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is built on the same substrate, the processing size of the transistor in the pixel portion is smaller than that in the peripheral drive circuit portion. What I did.

2. In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is built in on the same substrate, the breakdown voltage of the transistor in the peripheral drive circuit section must be higher than that of the pixel section.

3. In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is built in on the same substrate, the leak current of the transistor in the pixel part is smaller than that in the peripheral drive circuit part.

4. The thin film transistor should consist mainly of polycrystalline silicon.

5. In the manufacturing method of the thin film transistor panel, the peripheral drive circuit section should be a batch exposure method and the pixel section should be a divided exposure method.

6. To connect the wirings near the boundary of the divided exposure, use a negative photoresist and expose by overlapping the dimension of the wiring width or more.

7. Form a liquid crystal display device using a thin film transistor panel.

According to the present invention, it is possible to form the peripheral circuit section and the pixel section of the TFT active matrix panel for liquid crystal display into appropriate configurations without increasing the number of steps in the manufacturing process.
Therefore, it is possible to form a high-definition panel, form a large-screen panel with high precision, and improve yield by applying a redundant system.

In other words, in principle, one defect of one substrate in LCD TFTs is rejected.

In LSI, since a Si wafer is pelletized into small pieces, even if there is a defect in one wafer, only that pellet becomes defective and the other pellets can be made good.

Therefore, 1) methods to prevent defects, 2) methods to operate even if there are defects, and redundancy methods are being studied.

Examples of the redundancy system (system) are as follows: a) A plurality of TFTs are created for one pixel, and even if one is defective, the other operates to show a normal image.

b) Even if the wiring is broken, double wiring ensures normal operation.

c) When the gate electrode and the drain electrode are short-circuited, cross-shaped defects (pixels in one row and one row in the vertical direction are all destroyed) occur. However, by inserting an appropriate resistance value between the gate line and the gate electrode, It can be a defect (only one pixel).

and so on.

In the present invention, there is no particular new redundant idea, but the above redundant idea can be easily incorporated by distinguishing the pattern accuracy.

A supplementary explanation of the terms used in this specification is the processing size, which is the size of fine processing such as the size of the Si island for TFT (gate width and gate length) and the width of the wiring layer.
Width of 24, width of Figure 4, b, c.

The breakdown voltage is the breakdown voltage between the source and drain of a TFT having a MOS structure (the factors that determine the breakdown voltage are the size of the Si island (gate length), the thickness, the impurity concentration, etc.).

The same substrate corresponds to the Si wafer in the glass substrate LSI process, which is the first starting material in the TFT process.

When adjoining or adhering another substrate, it is possible to make a TFT on each substrate by a separate process.

Leakage current is the off-state current of TFT (source-drain current when gate voltage (negative bias in n-channel) is applied).

Originally, the batch exposure and the divided exposure are the method of performing the alignment and the exposure on the entire surface of one substrate by using one photomask at one time. Divided exposure is a method that is performed separately.

Here, it means a method in which the peripheral circuit region is divided into a single alignment and exposure, and the pixel region is divided into a plurality of alignment and exposure.

The wiring width refers to a scanning bus line and a signal bus line.

〔The invention's effect〕

According to the present invention, it is possible to provide a display device having excellent characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) and (c) are schematic plan views of a TFT panel for explaining an embodiment of the present invention, and FIGS. 1 (b) and (d) are liquid crystal display devices. FIG. 2 is a sectional perspective view, and FIG. 2 is a TF of an embodiment of the present invention.
Schematic sectional views showing the T structure, FIGS. 3 and 4 are schematic plan views of a TFT panel of another embodiment of the present invention and its local enlarged view, and FIG. 5 is a liquid crystal showing another embodiment of the present invention. 6A and 6B are schematic plan views of the pixel portion of the display device, and FIGS. 6 and 7 are plan views for explaining the pattern formed on the substrate. 10,30 …… Substrate, 11,31 …… Pixel area, 32 …… Peripheral circuit area, 50 …… Pixel.

Claims (7)

[Claims] 1. A display device having a display region and a peripheral circuit region for driving the display region on the same substrate, the display region comprising a plurality of first semiconductor elements arranged in a matrix. The display device is characterized in that the peripheral circuit region has a plurality of second semiconductor elements, and the minimum processing dimension of the first semiconductor element is smaller than the minimum processing dimension of the second semiconductor element. . 2. A display device having a display region and a peripheral circuit region for driving the display region on the same substrate, wherein the display region is a plurality of first semiconductor elements arranged in a matrix. The peripheral circuit region has a plurality of second semiconductor elements, and the withstand voltage of the first semiconductor element is smaller than the withstand voltage of the second semiconductor element. 3. A display device having a display region and a peripheral circuit region for driving the display region on the same substrate, wherein the display region is a plurality of first semiconductor elements arranged in a matrix. The peripheral circuit region has a plurality of second semiconductor elements, and the leakage current of the first semiconductor element is smaller than the leakage current of the second semiconductor element. 4. The display device according to claim 1, wherein the first and second semiconductor elements formed in the display area and the peripheral circuit area are formed in the same plane layer. . 5. A display device according to claim 1, 2, 3 or 4, wherein the first and second semiconductor elements are thin film transistors. 6. The display device according to claim 1, wherein the second semiconductor element formed in the display region is a thin film transistor having polycrystalline silicon as an active layer. 7. The display device according to claim 1, wherein a liquid crystal layer is formed on the display region.