JPH0827596B2 - Method for manufacturing active matrix array - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix array having active elements such as thin film transistors (hereinafter referred to as TFTs) and pixel electrodes connected to the active elements in a matrix on a substrate and a method for manufacturing the same. The present invention relates to an active matrix array that drives an image display material such as a liquid crystal material.

2. Description of the Related Art In recent years, liquid crystal display devices have gradually become larger and higher in density. Amorphous silicon (amorphous silicon)
Since the TFT using can be formed on an inexpensive glass substrate at a relatively low temperature of about 300 ° C and in a large area, it has been often used for an active matrix array for liquid crystal display devices.

FIG. 3 is a circuit diagram of a main part of a liquid crystal display device using an active matrix array by TFT (hereinafter abbreviated as TFT array). Pixels (broken line 14
(Parts surrounded by) are repeatedly formed in a matrix. A TFT 11 is built in each pixel, the gate electrode of the TFT is connected to the gate electrode wiring 3, the source electrode is connected to the source electrode wiring 6, and the drain electrode is a capacitor.
It is connected to Cs and the pixel electrode 2. For image display, the TFT 11 is switched by the scanning signal applied to the gate electrode wiring 3, the image signal applied to the source electrode wiring 6 at this time is transmitted to the capacitor Cs and the pixel electrode 2, and the counter electrode 12 and the pixel electrode 2 This is done by driving the liquid crystal 13 sandwiched between them. The capacitor Cs is used for storing the image signal. A portion other than the counter electrode 12 and the liquid crystal 13 in the broken line WXYZ is formed as an active matrix array on one substrate. Reference numeral 15 is a peripheral circuit.

When an active matrix array using an amorphous silicon TFT is formed by forming a thin film and photoetching using a photomask, it is generally advantageous in terms of yield and cost to make the conductive thin film as few times as possible. Therefore, in the case of a transmissive amorphous silicon TFT array for liquid crystal display devices, a non-translucent conductive thin film (for suppressing the photoconductivity of amorphous silicon for the TFT electrode wiring (gate electrode wiring and source electrode wiring)). A non-translucent conductive thin film is often used for light shielding) and a conductive thin film is not formed in addition to the transparent conductive thin film for pixel electrodes. A structure in which wiring and electrodes such as connecting electrodes are also made at the same time has been often used.

The present invention is deeply concerned with the active matrix array having the above-mentioned structure, and the active matrix array for a transmissive liquid crystal display device will be described below in detail with reference to the drawings.

FIG. 4 (a) is a partial plan view of a TFT array using amorphous silicon for a transmissive liquid crystal display device having the above-described configuration, and FIG. 4 (b) is FIG. 4 (a).
It is sectional drawing in the AB line part. FIG. 4 shows the TFT 11 in the pixel 14 of FIG. 3, a portion of the gate electrode wiring 3, a portion of the source electrode wiring 6, a portion of the common electrode wiring 9 (denoted as 9c in FIG. 4) and a translucent conductivity. 2 shows a configuration of the pixel electrode 2 made of a conductive thin film.

 The procedure for making this TFT array is as follows.

A non-translucent conductive thin film is formed on the glass substrate 1, and the gate electrode wiring 3 and the common electrode wiring 9c are selectively formed at the same time by using this. Next, an amorphous silicon thin film of the gate insulating film 4 is formed, and the amorphous silicon 5 which will be the channel portion of the TFT is selectively formed. After that, a transparent conductive thin film is selectively formed to form the pixel electrode 2, and further a conductive thin film is selectively formed to form the source electrode wiring 6 and the drain electrode 7 to complete the TFT array.

Problems to be Solved by the Invention In order to effectively reduce the number of times a conductive thin film is formed, the conventional method
As shown in the figure, the gate electrode wiring 3 and the common electrode wiring 9c are simultaneously formed, and then the gate insulating film 4 and the pixel electrode 2 are formed.

Generally, in most cases, the pixel electrode 2 in an amorphous silicon TFT array for a transmissive liquid crystal display device has I
A transparent conductive oxide represented by TO (oxide of In and Sn; In _x Sn _y O) is used. ITO thin films are formed by various methods, but the film is stabilized by heat treatment in an oxygen atmosphere after thin film formation on the substrate, and the film is resistant to plasma and chemicals during resist removal and cleaning used for photoetching. As a result, the process resistance during the fabrication of the TFT array is improved and the process margin is increased. FIG. 5 is a result of an experiment conducted by the inventors of the present invention, which shows the heat treatment dependence of the sheet resistance of an ITO film having a thickness of 1000 A formed on a glass substrate by a reactive sputtering method in an oxygen atmosphere. is there. As you can see from this figure, 400 ℃
At the above temperature, the sheet resistance is quickly stabilized to a small value. Further, the plasma resistance and the chemical resistance are improved with the stabilization of the sheet resistance. However, in the conventional TFT array having the configuration as shown in FIG. 4, the heat treatment of ITO cannot be sufficiently performed and the ITO cannot be sufficiently stabilized for the following two reasons.
The first reason is that in FIG. 4, the amorphous silicon 5 is formed before the ITO is formed, and in this case, the amorphous silicon is deteriorated at a temperature exceeding 400 ° C.
It does not work as T. Therefore, the amorphous silicon can be heated only to a temperature of about 250 ° C to 300 ° C, which is stable in an oxygen atmosphere. The second reason is the problem of expansion and contraction of the glass substrate. FIG. 6 also shows the results of experiments conducted by the inventors of the present invention. Some typical thin film materials for an amorphous silicon TFT array on a glass substrate (Corning, Inc., 7059 substrate, thickness 1 mm). Is a measured value of the expansion and contraction of the substrate when the film was deposited (markers were placed at intervals of 3 inches on the substrate and changes in the interval were measured before and after the deposition of the thin film). IT
After forming the O film, heat treatment at 450 ° C. for stabilizing the ITO causes a very large shrinkage of the substrate. Due to the problem of expansion and contraction of the substrate, ITO could not be heat-treated at a sufficiently high temperature with the conventional structure.

 Expansion and contraction of the substrate causes the following inconveniences.

As can be seen from FIG. 6, the glass substrate (for example, Cr) expands and contracts even when the thin film is not necessarily formed by the heating process. When a large number of such thin film materials are laminated to form a TFT array, the expansion and contraction of the substrate are integrated, and the size is often not negligible. Furthermore, it is necessary to consider variations due to the glass substrate used at each time (varies depending on the glass substrate preparation conditions, the surface polishing method, and the heating process involved). Therefore, when the glass substrate is used, it is necessary to design the TFT array by sufficiently setting the expansion / contraction margin of the substrate as described above. If this margin is not taken sufficiently, for example, the superposition of the patterns of the gate electrode and the source / drain electrodes will shift due to the expansion and contraction of the substrate, and will not work as a TFT, or the overlapping capacitance of the gate electrode and drain electrode will vary due to expansion and contraction Therefore, the displacement component of the image signal due to the overlapping capacitance varies within the substrate, and accurate signal transmission becomes impossible, or even if the counter substrate uses a color filter or a black stripe for shielding the TFT, the substrate shrinks. Therefore, the position shift from the counter substrate occurs. All of these phenomena lead to image defects and deterioration.

Further, the expansion and contraction of the glass substrate becomes a big problem in a large-sized and high-density TFT array. The inventors of the present invention have created a TFT array having a screen size of 3 inches with a conventional configuration as shown in FIG. 4 by using a thin film as shown in FIG.
Although the heat treatment was performed at 250 ° C.), there was a variation depending on the glass substrate, but the shrinkage of the substrate caused a pattern of 3 to 4 μm between the gate electrode wiring patterned first and the source electrode wiring patterned last. Alignment has occurred. If this is left as it is on a large screen size TFT array, it will be 14 inches (A4 size), for example.
The misalignment was about 20 microns, and it was necessary to take a very large margin for mask pattern overlay in the conventional TFT array.

In view of the above points, the present invention measures the stability of the ITO thin film by heating at a high temperature, while improving the process resistance at the time of creating the TFT array, the expansion and contraction of the glass substrate relating to the performance is made smaller than the conventional one, The purpose of the present invention is to provide a more stable manufacturing process and to easily increase the size and density of the TFT array.

Means for Solving Problems The technical means of the present invention for solving the above problems are:
First, create a transparent conductive oxide thin film such as ITO for pixel electrodes on a glass substrate and heat it at a high temperature before the first patterning to stabilize ITO and thermally expand and contract the substrate. After sufficiently performing the patterning, the pixel electrode is patterned, and then the insulating thin film and the common electrode wiring are formed to form the capacitor Cs.

What really matters in the fabrication of a working TFT array is the stretching that occurs after the initial patterning. Therefore, in the configuration of the conventional example, the ITO deposition and heat treatment were performed after patterning the gate electrode wiring, and the expansion and contraction at this time was a problem, whereas the method of the present invention formed the ITO deposition and Since the expansion and contraction that occurs during the heat treatment is before the first patterning, the expansion and contraction of the substrate at this time can be completely ignored. In particular, in the structure of the present invention, since the step of forming the pixel electrode is not included between the formation of the pattern of the gate electrode and the source / drain electrode of the TFT, the expansion and contraction can be ignored, and the pattern of the gate electrode and the source / drain electrode The overlay margin can be reduced.

FIG. 7 is also the result of an experiment conducted by the inventors of the present invention, which is a glass substrate (Corning Co., Ltd., 7059 substrate, thickness 1 m).
(m) shows the expansion and contraction of the glass substrate when only heat treatment was performed at 450 ° C without a thin film (markers were placed at 3 inch intervals on the substrate and changes in the distance were measured before and after heat treatment). . From this figure, it can be seen that although the glass substrate shrinks greatly during the initial hour, the amount of change in shrinkage decreases with time. Taking advantage of this property, if heat treatment is sufficiently performed before the first patterning to complete the expansion and contraction of the substrate to some extent, the amount of expansion and contraction at that time will be the same even if heating is performed in other steps after that. It is smaller than the ones.

Thus, by using the present invention, it is possible to provide a process capable of both stabilizing the ITO and suppressing the expansion and contraction of the substrate caused in the process after the first patterning is made small, and it is possible to provide a process between the patterns described above. The defects due to mismatching are reduced, which is very effective in practice. In addition, the margin of superimposition between the patterns becomes small, and it becomes easy to create a TFT array with a larger size and higher density.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a partial plan view of a TFT array for a liquid crystal display device according to a first embodiment of the present invention, and a sectional view taken along the line CD is FIG. 1B. As for the circuit, the same portion as that of the conventional FIG. 4 is shown.

 The procedure for making this TFT array is as follows.

Glass substrate 1 (Corning, 7059 substrate, thickness 1mm)
An ITO thin film with a film thickness of about 1000 A was formed on the upper surface by reactive DC sputtering, and then a heat treatment at a temperature higher than 400 ° C, which is considered appropriate based on the results of Figs. 5 and 6, was performed at 450 ° C here. Heat treatment in oxygen atmosphere for 45 minutes. Next, the ITO is patterned by photoetching to form the pixel electrode 2. Next, a SiO ₂ film 8 having a film thickness of about 2000 A is formed as an insulating layer of the capacitor Cs. Then, a Cr thin film having a film thickness of about 1000 A is formed by DC sputtering, and this is photoetched to simultaneously form the gate electrode wiring 3 and the common electrode wiring 9a in the region where the pixel electrodes 2 are arranged in a matrix. Next, as a gate insulating film, the SiNx thin film 4 with a film thickness of about 4000 A has a film thickness of about 500 A.
Amorphous silicon of about 300 ℃ by plasma CVD method
It forms continuously at the temperature of. Next, the amorphous silicon 5 is patterned by photoetching. And form contact holes for connection between each conductive thin film,
Finally, the source electrode wiring 6 having a two-layer structure (however, represented by one layer in the figure) of low-resistance amorphous silicon containing impurities of about 500 A and a conductive thin film of about 7000 A in thickness
And the drain electrode 7 are formed. The inverted staggered TFT is used because the gate electrode functions as a light shielding layer.

When the inventors of the present invention created a TFT array having a screen size of 3 inches with the configuration as shown in FIG. 1, there were variations due to the glass substrate, but there was variation due to the glass substrate The pattern mismatch between the source electrode wirings 6 caused by the shrinkage of the substrate is about
Only 1.5-2 microns were produced. This was about half the value of the conventional configuration.

Obviously, by using the present invention, the ITO has low resistance and is stabilized, the process resistance is improved, and the pattern misalignment due to the expansion and contraction of the substrate, which leads to defects, is reduced.

 Next, a second embodiment of the present invention will be described.

FIG. 2 (a) is a partial plan view of a TFT array for a liquid crystal display device according to a second embodiment of the present invention, and a sectional view taken along the line EF is FIG. 2 (b). The circuit shows the same portion as that in FIG.

The same components as those in FIG. 1 are designated by the same reference numerals. The manufacturing process is almost the same as that of the first embodiment, and the different point is that the common electrode wiring 9b is simultaneously manufactured with the wiring material of the source electrode wiring 6. Therefore, the two insulating layers of the SiNx thin film 4 and the SiO ₂ thin film 8 are used for the capacitor Cs, and the pixel electrode 2 and the common electrode wiring 9b are short-circuited as compared with the first embodiment, and dot-like defects are generated. It is configured to reduce the probability of occurrence.

Also in the second embodiment, ITO has a low resistance and is stable, the process resistance is improved, and the pattern misalignment due to the expansion and contraction of the substrate, which leads to a defect, is reduced.

EFFECTS OF THE INVENTION As described above, by implementing the present invention, ITO has low resistance and is stable, and the process resistance is improved, and the pattern misalignment due to the expansion and contraction of the substrate, which leads to defects, is reduced, and the production of the TFT array. The property is improved. This also helps in making large, high density TFT arrays.

 Moreover, the following effects were also produced.

That is, when the present invention is carried out, the pixel electrode 2 is always covered with the insulating layer. Therefore, the leakage current to the liquid crystal layer is smaller than that of the conventional one, and the image quality is improved.

Further, in the case of the embodiment of the present invention, the SiO ₂ thin film 8 functions to suppress the diffusion of impurities such as alkali ions from the substrate, which is a problem in the nature of using the glass substrate, and
It has the function of equalizing the physical properties of the substrate surface before the formation of the TFT gate electrode wiring, and also produces the effect of creating a TFT array with little variation in the TFT characteristics.

To obtain the same two effects as above with the conventional configuration,
In the TFT array, it is necessary to further form an insulating layer for passivation on the pixel electrode 2 and an insulating layer interposed between the TFT and the substrate. In other words, in the present invention, the number of steps of forming the insulating layer 8 is increased in terms of the structure, but in order to actually obtain the same effect in the conventional structure, it is necessary to form two more insulating layers, which is rather effective. It can be considered that the number of steps is reduced in the present invention.

Further, in the embodiment of the present invention, since the insulating layer is formed between the pixel electrode 2 and the TFT electrode wiring, the pixel electrode 2 is closer to the source electrode wiring 6 than the conventional one shown in FIG. Since it can be built up, the aperture ratio becomes large (pixel electrode 2
Area increases). That is, in FIG. 4 of the related art, the pixel electrode 2 and the source electrode wiring 6 are at the same level and a margin of d is provided as an interval to prevent a short circuit. For example, in FIG. Since there is an insulating layer between them, the probability of short circuit is very small.

As described above, the present invention is very effective in practice.

[Brief description of drawings]

1A is a partial plan view of a TFT array for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 1B is a CD view.
2A is a partial plan view of a TFT array for a liquid crystal display device according to a second embodiment of the present invention, and FIG. 2B is a sectional view taken along line EF. FIG. 3 is a circuit diagram of a main part of a typical liquid crystal display device, FIG. 4 (a) is a partial plan view of a conventional TFT array for a liquid crystal display device, and FIG.
Fig. 5 is a cross-sectional view taken along line -B, Fig. 5 shows the heat treatment dependence of the sheet resistance of the ITO thin film, Fig. 6 shows the stretchability of the glass substrate due to thin film formation, and Fig. 7 shows the heat of the glass substrate. It is a figure showing expansion and contraction. 1 ... Glass substrate, 2 ... Pixel electrode, 3 ... Gate electrode wiring, 4 ... Gate insulating film, 5 ... Amorphous silicon, 6 ... Source electrode wiring, 7 ... Drain electrode, 8 ...
… Insulating thin film, 9,9a, 9b, 9c …… Common electrode wiring, 11 …… TF
T.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shigenobu Shirai, 1006 Kadoma, Kadoma City, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (72) Yutaka Miyata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. ( 72) Inventor Takao Chikamura, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-55-89817 (JP, A) JP-A-57-154280 (JP, A) JP Sho 58-25689 (JP, A)

Claims (6)

[Claims] 1. A pixel electrode made of a translucent conductive oxide thin film arranged in a matrix on a glass substrate is formed in a step involving heating, and then an insulating thin film is formed on the pixel electrode. A common electrode wiring is formed on the pixel electrode and a part of the common electrode wiring overlaps at least the insulating thin film, and the transistor is formed after forming the insulating thin film on the pixel electrode. A method for manufacturing an active matrix array, which comprises forming an active element of a type. 2. In a region where pixel electrodes are arranged in a matrix, a part of electrode wiring connected to an active element and a common electrode wiring are simultaneously formed from the same conductive thin film. 2. A method for manufacturing an active matrix array according to claim 1. 3. The pixel electrode is formed by selectively patterning a translucent conductive oxide thin film, and a heating step is performed before patterning the pixel electrode. 3. A method for manufacturing an active matrix array according to either the first or second range. 4. The method of manufacturing an active matrix array according to claim 1, wherein the active element is a thin film transistor, and the electrode wiring formed at the same time as the common electrode wiring is a gate electrode wiring. 5. The method for manufacturing an active matrix array according to claim 4, wherein the thin film transistor is a thin film transistor using amorphous silicon. 6. The transparent conductive oxide thin film contains In, Sn and O as main components, and the heating step performed when the transparent conductive oxide thin film is formed is 400 ° C. or higher. The method for manufacturing an active matrix array according to claim 4, wherein the method is performed at a temperature.