JPH0827762B2 - Common memory controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common memory control device for a common storage device connected to one or more processing devices in a central control system such as an electronic exchange.

[0002]

2. Description of the Related Art Generally, in a processing apparatus such as an electronic exchange that is required to perform processing in real time, while permitting access from a plurality of processing apparatuses in order to guarantee processing in real time. The storage device has two storage devices whose stored contents match each other. As a storage device having such a duplex structure, for example, Japanese Patent Laid-Open No. 53-12142.
No. 9 publication.

In this type of device, a plurality of devices, for example, two devices, are used.
The two storage devices (shared storage devices) are connected to each other and these shared storage devices and a plurality of processing devices are connected by an interface of the same specification, and an access activation request signal from the processing device or other By providing a selection circuit for selecting an access activation request signal from the storage device of the system, the writing contents from the processing device can be made the same between the shared storage devices.

In general, the shared storage device is operated in a mode in which the memories of both systems have the same contents as described above in system operation (hereinafter referred to as " both system same content mode"). Unthinkable , one common memory
There are also cases where you want to access only the device. For this reason,
For example, by providing the same content mode flag for both systems ,
Enables offline configuration of the common storage device by turning off the same content mode on both systems, and allows access to one common storage device
It is.

By the way, in the device having the above-mentioned configuration,
And on the state of both systems the same content mode to match the memory contents of both systems, off-line configuration of the memory device has only the OFF state of both systems the same content mode present systematically. Therefore, when it is necessary to take over to the new operation program without stopping the exchange operation itself like when updating the current operation program in the electronic exchange, the following takeover method is used.

(1) A storage device of one system is separated from an online system to be an offline system, and a new operation program is written in this storage device. The off-line system is a system in a state other than the original operation of the system (for example, a fault system or a diagnostic system).

(2) After this writing is completed, this storage device is operated as a new online system by a new operation program.

[0008]

However, in this case, the following points become problems.

That is, while the new program is being written in the offline storage device, the online storage device has a single configuration as seen from the system. If a failure occurs in the online system in this state, the failure to be recovered cannot be recovered by the switching operation to the offline system, and the system goes down. As shown in FIG. 2, a normal exchange program generally has a two-layer structure of a current operation file 5 and an old operation file 6, because the old operation file is This is because it is essential as a guarantee file when the current operation file becomes inoperable. Therefore, rewriting the old operation file of both systems to the new operation file means that the guarantee file is lost, which is not preferable in terms of system reliability.

Further, securing a memory capacity capable of accommodating all three current, old, and new operational files is not economically superior at present when the operational files themselves are becoming larger in scale. .

The present invention is more said storage device during operation file update so that the undesirable reliability of the system becomes single configuration and problem that, both systems the same content is in a write operation of both systems If you try to save the old file while the mode is on, you have to expand the memory space,
It was created to solve the problem of being economically inferior. That is, the object of the present invention is to enable access to only the storage device of the standby system and rewrite only the old file of the standby system to the new file while the same content mode of both systems is on. It is an object of the present invention to provide a common memory control device which is excellent in reliability and economical in that a new operation file can be written in a storage device without damaging the duplicated structure of the current operation file even during file updating.

[0012]

Common memory control of the present invention
In order to solve the above-mentioned problems, the apparatus has the following means in each of the redundant storage devices connected to the processing device.
Is configured to have.

That is, each storage means is (1) a storage area
In both the act and standby storage devices.
A dual access area where simultaneous access is executed,
A single processing device that only allows access from the processing device
Access memory and (2) processor
Indicate whether the misaligned storage device is an act system or a standby system
Memory logical rank information and stand-alone access
And access Sumemori Kaii information which indicates whether or not, act system
Dual memory in both standby and standby storage devices
Both systems have the same content mode that instructs access to the access area.
Input information capturer that captures access mode information whether or not
And the logical floor of the memory that the (3) input information capturing means has captured.
Position information, access memory rank information and access mode information
Information and the access request address from the processor are duplicated.
For the access area or the processor-only access area
From the confirmation result of whether or not
If it is accepted, and if it is accepted
A processing device access receiving means for outputting an operation command,
(4) On the side of the storage device of the other system,
Sending operation commands to memory or from other storage devices
To receive the operation command of the
Other system memory control means connected, and (5) Processor unit
Access command from access acceptance means and other system memory control means
Arbitration means for arbitrating the operation command received by (6)
Whether the operation command from the arbitration means is the processor access acceptance means
Address from the processing unit, if
When the redundant access area is specified,
Access to other system from other system memory control means.
The operation command to the storage device of the
Dual access area of memory in both storage devices
Area, and the operation command from the arbitration means is processed.
If it is from the physical device access acceptance means
Address from the processor is the access area for the processor alone.
Access the local memory when specifying the area
In addition, the operation command from the arbitration means is sent to the other system memory control means.
Other system if it is for the received operation command
In cooperation with the memory control means, access the own memory
Memory control means.

Then, the same content mode of both systems is instructed.
Even in the standby memory
Single access to the processing device single access area
It is characterized by

[0015]

In the common memory control device of the present invention , the input information is
The information capture means is both an act storage system and a standby storage device.
Access to the redundant access area of the memory
Even if you capture the access mode information shown
If the input information acquisition means is a standby system,
Memory logical floor that directs stand-alone access
Position information and access memory rank information is taken in and processed
The address requested to be accessed by the
Access area, if it is for
The process acceptance means does not accept access by the processing device.
It is determined that the operation is performed and the operation command is output.

Such an operation command is issued by the arbitration means.
Arbitrated with the operation command received by the other system memory control means.
After that, it is output to the memory control means at a predetermined timing.
It The memory control means that has received this operation command is a processing device.
Addresses from the processor point to the processor-only access area
Therefore, only the memory of the self system, that is, the standby system is activated.
Set.

As a result, the same content mode for both systems is designated.
Memory of the standby system by the processor even if
Access to the memory access area of the device
Access is possible.

On the other hand, the input information fetching means is an act system and
Memory duplication in both standby storage devices
Access mode information that directs access to the access area.
In case of importing, the input information importing means
Logical rank information indicating that is an act system
And access memory rank information that instructs access
Address that was fetched and requested to be accessed by the processing device
Is for a dual access area,
The processing device access acceptance means is an access by the processing device.
Is determined to be accepted and an operation command is output.

Such an operation command is sent to the arbitration means as it is.
And is output to the memory control means. But this
Upon receiving the operation command, the memory control means receives the operation command from the processor.
Since the dress points to the redundant access area,
Memory and access by other system memory control means.
Then, the operation command is sent to the storage device of the other system. Let this Yo
Other storage devices that are given a different operation command
According to the decree, access the memory of its own system.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a common memory control device according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a duplicated dual system common storage device is shown.
Although the storage device (hereinafter, simply referred to as a storage device) is provided, the storage devices of both systems have the same configuration, and therefore the configuration of the other storage device is denoted by reference numeral A and description thereof is omitted. Well
In addition, FIG. 1 shows only the control configuration of the memory.
The input / output configuration of data such as data lines is omitted.

[0022] These two storage devices 100,100A
Is configured such that when one becomes an act system which is responsible for the original operation of the system at that time, the other becomes a standby system (slave system) which is always replaced by the act system.

Further, the common memory control device of this embodiment
Intended to be connected to the central processing system of an electronic exchange
The memory 60 of each storage device 100 stores the current operation file.
Files and old operation files are stored. Current operation file
The storage area for files is 2 so that duplication works effectively.
Writing or the like is executed almost simultaneously in one storage device 100.
This is the area to be processed. The old operation file area is the memory of both systems
The current operation files of the devices 100 and 100A are both incorrect.
In some cases it will be accessed on its behalf,
Such a thing is rare, and it is rewritten to a new operation file.
It has a great significance as a field to be covered.

[0024] The receiving conditional decision circuit 10, access memory Kaii specified line 1 from the processor, the address data specified line 2, along with the memory access designating line 3 is connected,
The output of the COPY FF 80, which is set by a memory maintenance instruction from a processor ( not shown), and the output of the ACT FF 90, which indicates the memory logical rank, are connected as inputs.

Here, the memory logical rank is a description of its own system.
This is information that indicates whether the storage device 100 is an act system or a standby system.
is there. For example, ACT FF = 0 indicates a standby system
Then, ACT FF = 1 indicates the act system. In addition,
Access to access level 1 of access memory is stun
It indicates whether it is a bi-system memory device or an act-system memory device.
is there. Both systems have the same content mode and access
When the memory rank indicates an act storage device
Means that the standby storage device is also accessed.
I'm tasting.

The flag COPY FF has been described above.
Indicates whether or not both systems have the same content mode
And the memory access designation lines 3 and 3A became significant.
Occasionally, it is taken into the acceptance condition determination circuit 10. Current operation file
When accessing mainly the storage area of files,
Both systems have the same content mode so that the redundant function works effectively.
Is set.

The address data designation line 2 is an address data
For inputting data into the storage device 100, 100A
It is. For address data, act system or standby system
The storage devices 100 and 1 of both systems
There is also a data part that distinguishes 00A.

[0028] Receptionist condition judging circuit 10, the input information described above
After determining the acceptance condition based on the information, the common memory control unit 30 in the subsequent stage is activated. example
For example, when the address data of the storage device of another system is input
It is determined that the condition is not met. Also, for example, if the self
It is a storage device of
Area that can be accessed in the same content mode on both systems (example
If the address of the current operation file area) is entered
It is determined that the condition is satisfied, and the common memory control unit 30
The output signal 31 is made significant. Furthermore, for example, if the self
A standby system of storage peripherals, both systems the same content mode
Is set, and standby access is instructed.
If the common memory control unit 30
The output signal 32 from is significant.

The address data designating line 2 has an address comparing circuit 20 for determining whether the address designated by the processing device is a standby region and an accessible region, and an address in the memory 60. It is also connected to a memory control circuit 50 for sending data.

The address comparison circuit 20 is as described above.
When the specified address is a standby system
Judge whether the area is accessible only to
The signal is output to the AND circuit 21.

[0031] The common memory control unit 30 creates the operation timing and check timing in an output signal 31 when normal memory access (hereinafter referred to as "ACT Access"), alone access to the standby system (hereinafter "SBY
It is configured to output the output signal 32 at the time of "access". In addition, the normal memory access A
CT access must be enabled for access so that duplication works effectively.
Both the standby and standby storage devices 100 and 100A
Means to access.

The output of the determining whether the AND circuit 21 SBY access address condition is satisfied on the basis of the output of the S BY access time of the output signal 32 and the address comparing circuit 20, an output signal 31 at the time of ACT access Is input to the OR circuit 22, and the output of the OR circuit 22 is input to the arbitration circuit 40. Therefore, from the OR circuit 22,
When the ACT access is accepted and the standby system
The address of the accessible area is entered only when
Significant signal on accepted SBY access
Is output.

The other-system memory control unit 70A of the other-system storage device 100A and the other-system memory control unit 70 of the own-system storage device 100 are connected via a confounding bus 72, and the other-system memory control unit. From other system (act system) received at 70
The access operation request signal is used as the other system operation instruction signal 71.
The data is input to the arbitration circuit 40.

The operation instruction signals arranged in order by the arbitration circuit 40 are connected to the memory control circuit 50. The memory control circuit 50 connects the address data bidirectional bus 5 with the memory 60 and the other system memory control unit 70.
1 are connected respectively.

Next, the operation of the embodiment of the present invention constructed as above will be described.

First, at the time of ACT access, the acceptance condition determination circuit 10 determines that the access is a normal access, and the common memory control unit 30 outputs a normal access signal 31. The normal access signal 31 input to the arbitration circuit 40 via the OR circuit 22 does not need to receive access from the standby storage device 100A when the storage device 100 is the act system (from the standby system). To act system
There is no operation command ), as it is, the memory control circuit 50
Is input to, if in both systems the same content mode (entered
The address data bidirectional bus 51 is used to perform writing and activation to the memory 60 and the other system memory control unit 70. By this, the memory 6 of both systems
0 and 60A are accessed.

On the other hand, in the SBY access in the same content mode for both systems , the condition that the own storage device is the standby system (ACT FF = 0) in the acceptance condition determination circuit 10 and the access memory rank designation from the processing device are specified. Line 1 is SB
Upon recognizing that the Y access is designated, the common memory control unit 30 is activated.

At the same time, the address comparison circuit 20 determines whether or not the address portion of the address data designating line 2 from the processing device has an address larger than (other than) the designated area.
The AND circuit 21 takes an AND condition between this output signal and the standby system access activation signal 32, and the output is input to the arbitration circuit 40 via the OR circuit 22.

In the case of a standby system storage device (for example, 100) in the same content mode of both systems , the memory write operation instruction of the standby system storage device output from the other system memory control unit of the act system storage device is other. System memory controller 7
It is output to the other system memory write instruction signal 71 via 0. Then, the standby system access activation signal 32 and the write instruction signal 71 input to the arbitration circuit 40 carry over to the memory control circuit 50 the result given by simply selecting the time condition (first-come-first-served priority).

As described above, in the standby storage device, the memory access operation from the act storage device,
The standby access operation from the processor coexists, and the accept operation can be performed.

Regarding the address comparison circuit 20,
Area limitation can also be controlled by program control on the processing device side, in which case the address comparison circuit 20 on the storage device side becomes unnecessary.

[0042]

In summary, according to the present invention, both systems
By permitting a single access of the standby storage device from the processing device in the double accessible state , the processing device can write desired information in a limited area area of the storage device.

Therefore, the current operation file of the storage device in online operation can be duplicated (act system and standby system), and the old file on the act system side can be stored in the standby system storage device whose area is limited. You can write a new file without destroying.

Therefore, the safety of the system and the economy of the memory capacity of the storage device can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a common memory control device according to the present invention.

FIG. 2 is a configuration diagram showing a replacement program.

[Explanation of symbols]

1 access memory rank designation line 2 address data designation line 3 memory access designation line 10 acceptance condition determination circuit 20 address comparison circuit 30 common memory control unit 40 arbitration circuit 50 memory control circuit 60 memory 70 other system memory control unit

Claims (1)

[Claims] 1. A dual storage connected to a processing unit.
Each device has a storage area as an act system and a standby system.
Redundancy in which almost simultaneous accesses in storage devices are performed
Only access from the access area and the processor is allowed
A memory having a processing device independent access area, and which of the storage devices is an act system from the processing device.
Memory logical rank information that indicates whether it is a standby system,
An access message that indicates whether or not a stand-alone access is
Mori rank information and the above-mentioned notes of act system and standby system
Memory to the redundant access area of the memory.
Access whether both systems have the same content mode to instruct access
Input information capturing means for capturing mode information, and memory logical rank information captured by the input information capturing means.
Information, access memory rank information and access mode information
And the access request address from the processing device is
For a dual access area or a single processing area access area
Based on the confirmation result of whether the
Access is accepted and accepted
Output an operation command to the memory if
The processing device access accepting means and the storage device side of the other system in the storage device of the other system.
To send operation commands to the memory or to
Correspondence of other systems, such as receiving operation commands from storage devices
Another system memory control means interconnected with the element, an operation command from the processing device access acceptance means,
Arbitration and output of operation commands received by other system memory control means
And an operation command from the arbitration means for receiving the processor access
In the case of the operation command from the attachment means,
When these addresses point to the duplicated access area
To access the memory of its own system and
An operation command is sent from the system memory control means to the storage device of another system.
Both of the act and standby storage devices that are sent out
Access the redundant access area of the memory in
And the operation command from the arbitration means is the processing device.
In the case of an operation command from the access receiving means ,
The address from the processor is the access area for the processor alone.
Access only the memory of the local system when specifying the area
In addition, the operation command from the arbitration means is transmitted to the other system.
In the case of the operation command received by the memory control means,
In cooperation with the memory control means of another system, the memory of the own system can be accessed.
Memory control means for accessing the standby mode, even if the same content mode is specified for both systems.
B) The processing device independent access in the memory of the storage device
A common memory control device, which enables independent access to a process area .