JPH0828810B2 - Image data scaling processor - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to an image data scaling device used in an image scanner, a digital copying machine, a facsimile, or other image processing devices.

[Prior art]

FIG. 8 shows an external appearance of a conventional image reading apparatus. This image reading device has a shape like a top of a copying machine. A document is placed on the contact glass 2 and pressed by the document pressure plate 3. The operation unit 4 includes
It is equipped with several types of keys such as the reading start button and density selection key, and several types of displays that display the setting status and operating status, so that various functions can be set. By pressing the start button, reading can be started and an image signal can be obtained. 9 and 10 show a typical configuration of the image reading apparatus shown in FIG. 8, particularly a reading optical system.
The figure shows the optical system when using a contact image sensor,
FIG. 10 shows an optical system when a reduction type image sensor is used. Other than this, there is a document whose document is moved and the optical system is fixed. When the contact image sensor as shown in FIG. 9 is used, the optical system is a 1 × optical system. The original surface on the contact glass 2 is illuminated by the fluorescent lamp 5 and its reflected light 8
Enters the image sensor 7 through the self-hook lens 6. The image sensor 7 has a width equal to or larger than the document width (the depth direction in FIG. 9, that is, the main scanning direction X), and the image data of one line in the width direction is read at one time. Number of lines sampled and sampling pitch
Px is determined by the number of pixels of the image sensor. After reading one line of data, the carriage 8 that integrates the fluorescent lamp 5, the self-hook lens 6 and the image sensor 7 is integrated.
Is driven in the direction of the arrow (sub-scanning direction Y), and the next line is read. There is also a mode in which the carriage 9 is continuously driven in the sub-scanning direction Y. The pitch Py between lines is determined by the speed of the carriage 9, the charge storage time of the sensor 7, etc., but is normally set to the same sampling pitch Px as described above. When a reduction type image sensor is used as shown in FIG. 10, the lens 14 reduces the original width of the optical image so as to match the size of the image sensor. In FIG. 10, three mirrors are used, but two or five mirrors are also conceivable. Regarding reading in the main scanning direction X,
This is the same as when using a contact sensor. In the sub-scanning direction Y, a first fluorescent lamp 10 and a first mirror 11 are integrated into a first unit.
The carriage and the second carriage that integrates the mirrors 12 and 13 are independently driven so that the optical path length from the original on the contact glass plate 2 to the lens 14 becomes constant. Here, the conventional scaling method is performed by changing the optical path length of the optical system to change the reduction ratio in the main scanning direction X, and changing the speed of the moving body in the sub scanning direction Y. I was doing in. However, this method
It cannot be used when the contact type sensor as shown in FIG. 9 is used. Even in the case of the reduction type sensor shown in FIG. 10, the range of the variable magnification is structurally limited, such that the variable magnification does not change so much even though the amount of movement for changing the position of the lens 14 and the sensor 7 is large. In addition, a precise mechanism must be used for the movement accuracy of the lens 14 and the sensor 7 and a position adjusting mechanism, and a coarse mechanism has a big problem that the read image is deformed. In consideration of these conventional problems, recently, instead of optical scaling, image processing to obtain scaled image data by predictively calculating the scaled data from the same-magnification read data, so-called electrical scaling is used. I'm starting to be seen. However, the currently proposed electrical scaling has a problem in the precision of the scaling, and if the scaling is performed with high accuracy, the hardware becomes complicated, and so-called zoom scaling such as 1% increments and wide range zooming are possible. There was a problem that it was difficult to deal with variable magnification. Such a problem is that the data clock DCLK indicating the pixel unit division of the original image data is counted and the count value is set to the position i of the scaled image data, and i increases by 1 every time one pulse of DCLK occurs. 100i / specified scaling factor R% = Ji + Ri, an integer Ji and a small number Ri are calculated to sample the image data at the position x = Ji of the original image data and the image data adjacent thereto, and the sampled original image Calculate the scaled image data with the data and a small number of Ri
This is improved by defining the scaled image data at the i-th position in DCLK units. That is, according to this, the scaled image data is obtained in synchronization with the data clock DCLK of the original image data, and the scaled image data is printed, transferred or transmitted by raster scanning synchronized with the reading or transfer of the original image data. It can be processed. Moreover, the scaling factor R can be set in fine 1% units, and the range of R can be set wide.

[Problems to be Solved by the Invention]

With this method, every time one pulse of the data clock DCLK of the original image data is generated, that is, every time the original image data is shifted by one pixel, the sampling position x = Ji of the original image data and the scaled image data position i Between the position x and the position x
Is calculated, the data clock
DCLK frequency is limited. That is, the sampled original image data and Ri
One cycle of the data clock DCLK must be sufficiently longer than the sum of the times for calculating the scaled image data based on the above. Since the cycle of the data clock DCLK depends on the image reading speed, lengthening DCLK means lowering the image reading speed.
The transfer and transmission speeds will also be reduced. For example, in the image data obtained by the image reading apparatus shown in FIG. 9 or FIG. 10 (hereinafter referred to as original image data), the number of pixels in the main scanning direction X is N, and the number of pixels in the sub scanning direction Y is M. , The distribution of image data corresponding to the original image can be considered as shown in FIG. R in the main scanning direction in FIG.
[N × R / 100] new data (hereinafter referred to as scaled image data) can be generated by scaling at a magnification of%. Here, three typical scaling algorithms will be described. Here, since the electrical scaling is performed only in the main scanning direction, the following description also applies. First, in any method, it is necessary to confirm the position of the new sampling point 0 after the scaling and obtain the original image data of the old sampling points of several pixels around the new sampling point 0 and their distances. As shown in FIG. 12, the new sampling point 0 is between Sij and Sij ₊₁ of the original image data, and the distance between them is 0.
Let r ₁ and r ₂ , and let P be the sampling pitch of the original image data. Closest pixel replacement method This is a method of setting the original image data at the position closest to 0 as the scaled image data of 0 points, and if r ₁ ≦ r _{2 in} FIG. 12, 0ik = Sij r ₁ > r ₂ Then, it is a method of replacing 0ik = Sij ₊₁ . That is, the image data of the sampling point of the original image closest to the sampling point 0 of the scaled image is set as the scaled image data 0ik of the point 0. This is a method of allocating density levels according to the distance linear distribution method between adjacent pixels and 0 and the distance between adjacent pixels of the original image data. Scaled image data 0i in Fig. 12
k _{is, 0ik = (1-r 1} / P) Sij + (1-r 2 / P) Sij +1 ···
Obtained from (1). Cubic function convolution method Interpolation calculation is performed using an interpolation function h (γ) as shown in FIG. h (γ) is the γ that has been qualified with the sampling pitch P
Is approximated as follows. h (γ) = 1-2 | γ | ² + | γ | ³ 0 ≦ | γ | ≦ 1 h (γ) = 4-8 | γ | ² +5 | γ | ² − | γ | ³ 1 ≦ | γ ｜
≦ 2 h (γ) = 0 2 ≦ | γ | ... (2) Using this h (γ), the scaled image data 0ik is 0ik = [h (1 + r ₁ / P) Sij ₋₁ + h (r _{1 / P) Sij + h (} r 2 / P) Sij +1 + h (1 + r 2 / P) Sij +2 ] /
Calculating a _{[h (1 + r 1 / P} ) + h (r 1 / P) + h (r 2 / P) + h (1 + r2 / P) ] + h (1 + r2 / P ) ] (3). In addition to the above, and the like, there are methods such as the proximity pixel distance inverse proportional method and the proximity pixel area allocation method, but since they are relatively similar, the above is considered as a representative example. All of these methods have been known for a relatively long time, and have been put to practical use mainly in the field of computer image processing. For computer image processing, etc., when image data is stored in a high-capacity memory such as a page memory and then scaling processing is performed, these methods can be easily used, but there is no page memory and dedicated hardware is used. There are various restrictions for performing these processes. When performing scaling with a digital copier or facsimile, etc., it is necessary to perform raster scanning (line unit) on the data input in raster scanning (line unit) even after scaling processing.
The data clock (pixel sync pulse) needs to be constant at any scale factor. In other words, the data after the scaling process must be in the same format and at the same speed as the optical scaling.
That is, real-time processing is required. This is different when the magnification of the digital copying machine or the entire facsimile is considered. For example, if the printing speed of the printer can be changed during zooming, the data clock after zooming can also be changed. Further, in a system that performs transmission, it does not need to be raster scan data after scaling. However, when the scaling is considered as an image reading apparatus or by independently performing the scaling processing, the raster scanning processing is limited as described above. The present invention provides a variable power device applicable to a reading device subject to these restrictions. FIG. 6 and FIG. 7 are examples of time charts of pre-scaling data and post-scaling data that satisfy this restriction. In these, LSYNC is a horizontal cycle signal (line synchronization pulse: sub-scanning synchronization pulse) and reads image data of one line in the main scanning direction during one cycle of this signal. DCLK is a data clock (pixel synchronization pulse). At the timing shown in FIG. 6, it is assumed that pre-scaling data (pixel unit) Y is input to the scaling processing section from Si ₀ to Si _N in synchronization with DCLK within the period of LSYNC. As a result, the scaled data Z
Is output, the output Z may be delayed from the data Y, but it must be synchronized with DCLK. The delay time (t ₂ −t ₁ ) is not particularly limited, but it should not change between lines, and t ₂ and t ₁ should always be constant.
In addition, when inputting / outputting data in line units,
As shown in the figure, the read data (output) of the line buffer memories RAM1 and RAM2 may be later than the write data (input). Anyway, the most important and most difficult thing is to synchronize the scaled image data to DCLK at any magnification. This requirement is relatively easy to achieve if the magnification is changed with several fixed magnifications, but especially in recent copying systems, a wide range of magnification and a small magnification of about 1%, which is called zoom magnification, are used. It is required to change the magnification all the time, and it has become necessary for digital copying machines and facsimiles to meet these demands. Therefore, it is difficult to meet the above-mentioned requirements when actually applying the above-described scaling method. The present invention realizes a high-precision, fine, wide-range zooming ratio, and makes a scaling processing device having a simple configuration, which does not change the input data clock and the output data clock of image data even at the time of scaling. With the goal.

[Technical Means for Solving the Problems]

The scaling device of the present invention is based on the designated magnification R%,
Calculating means for calculating the original image data sampling position information and the position difference information indicating the difference between the original image data sampling position and the variable image data sampling position, which is associated with each variable image data sampling position i; Magnification processing information memory means for storing the original image data sampling position information and the position difference information corresponding to the data sampling position i; i is set to 1 in synchronization with the data clock DCLK of the original image data.
Reading means for reading the original image data sampling position information and position difference information corresponding to i from the scaling processing information memory means; data clock DCLK when R ≧ 100, image data clock when R <100 Sampling means for counting the data clock 2DCLK having twice the frequency of DCLK and extracting the original image data specified by the read original image data sampling position information and one or more original image data adjacent thereto; and Scaled image data setting means for determining scaled image data at the position i based on the correlation between the extracted original image data and the read position difference information in synchronization with the data clock DCLK.

[Action]

According to this, the original image data sampling position information and the positional difference information corresponding to the scaling percentage R are set in the scaling processing information memory unit by the computing unit; the reading unit stores these information in the original image data. Reading in synchronization with the data clock DCLK; and the sampling means in synchronization with the data clock DCLK,
Original image data is extracted based on the read original image data sampling position information; the variable-magnification image data setting means synchronizes with the data clock DCLK to read the positional difference information and the extracted original image data. Based on the predetermined logic, for example,
The variable-magnification image data is set by processing such as. The reading means, the sampling means and the scaled image data setting means are all provided with the data clock DC of the original image data.
Since it operates in synchronization with LK, the scaled image data is in synchronization with the data clock DCLK. That is, variable-magnification image data can be obtained by real-time processing. Therefore, it is possible to process the scaled image data in a raster scan type. When the original image data is transferred in synchronization with the data clock DCLK,
That is, at the time of image reading, the original image data sampling position information and the position difference information already written in the scaling processing information memory means are transferred to the data clock in this way.
Since the data is read in synchronization with DCLK, the time for calculating these pieces of information is saved, and the period of the data clock DCLK may be shortened accordingly. That is, the image reading speed and / or the transfer speed and the variable-magnification image data transfer speed corresponding thereto can be set high, which is suitable for high-speed image processing. In a preferred embodiment of the present invention, the computing means is 100i /
[Specified magnification R (%)] = Ji + Ri, i = 0 to R−1, 0 ≦ Ri <1, Ji is an integer, and an integer Ji and a small number Ri are calculated, and Ji is calculated when i is smaller than 1. The value Ji _-1 is held, and the R value and Ji are used as the original image data sampling position information.
−Ji ₋₁ Data Ai indicating the sampling position change amount of the original pixel data corresponding to the value is calculated and Ri as position difference information is calculated.
It is assumed that the data Bi indicating which one of the small area divisions 0 to 1 is in is calculated. According to this, the scaling factor R% can be set to any number and range with 1 as the minimum unit. That is, zoom magnification in units of 1% is realized, and the zoomable range can be set extremely wide. In the embodiment of the present invention described later, the scaling factor is set to 1%, and R = 50% to 400% is set as the settable range. Further, since the original image data sampling information written in the scaling processing information memory means is the data Ai indicating the difference between the previous sampling position Ji _-1 and the current sampling position Ji, that is, the pitch between two sampling positions (the number of pixels). The image data may be extracted at the pitch indicated by the data Ai, and the sampling position counting from the line start point as a base point becomes unnecessary. Further, since the position difference information written in the scaling processing information memory means is the data Bi indicating which one of the small area divisions belongs, a very small number of operations are omitted in the scaling image data calculation, Hardware is simplified, and the scaled image data calculation speed is increased. According to one embodiment of the present invention, in accordance with the use of these data Ai and Bi, the sampling means is a buffer memory means for storing the original image data for one line; the buffer memory means is alternately set to write / read. Means; address counting means for giving write / read position to the buffer memory means; data clock DCLK is given as a count pulse to the address counting means when writing to the buffer memory means, and data clock DCLK when reading from the memory means I is changed by 1 in synchronism with, and when R <100, one of the data clock 2DCLK and the data cronk DCLK having twice the frequency of the data clock DCLK corresponding to Ai is used as a count pulse for the address counting means. When R ≧ 100, the address of the data clock DCLK corresponding to Ai It shall be made in; and the application / interruption of the count means, the sampling position specifying means for specifying a reading position x of the original image data. That is, in this embodiment, the original image data of one line is stored in the buffer memory, and the read address is controlled to perform the read sampling of the original image data to obtain the scaled image data. The change amount of the read address of the image data at the time of reduction, that is, the read pitch of the original image data corresponding to the scaling ratio is the count clock to be given to the read address counter of the buffer memory, which is the data clock DCLK and twice the frequency thereof. Data clock 2 DCL
Perform by switching to K. In another embodiment of the present invention, the sampling means is a buffer memory means for storing the original image data for one line; a means for alternately setting the buffer memory means for writing / reading; an address counting means; an up / down counting means; Adder means for giving the sum of the count data of the address count means and the count data of the up / down count means to the buffer memory means as address data; when writing to the buffer memory means, the data clock DCLK is given to the address count means as a count pulse , When reading from the memory means, i is changed by 1 in synchronization with the data clock DCLK and R
In the case of <100, the up / down counting means is instructed to up, the data clock DCLK is given to the address counting means as a count pulse, and DCLK is applied / cut off to / from the up / down counting means according to Ai. In the case of 100, the up / down counting means is instructed to down, the data clock DCLK is given to the address counting means, and the data clock DCLK is applied / blocked to / from the up / down counting means in correspondence with Ai to obtain the original image. Sampling position specifying means for specifying the data read position x. That is, in this embodiment, the line buffer memory is provided as in the above-mentioned embodiment, but the read address is
Address count means; up / down count means; and addition means for giving the sum of the count data of the address count means and the count data of the up / down count means to the line buffer memory as address data. The sampling position designating means, when writing to the memory means, supplies the address counting means with a data clock DCLK that determines the pixel unit of the original image data as a count pulse, and when reading from the memory means, R <100. In the case of, the up-down counting means is instructed to up, and the address counting means
DCLK is given as a count pulse, and Ai is Ji-Ji _-1 =
When the value is 2, the up / down counting means is also supplied with the data clock DCLK. When Ai indicates Ji-Ji _-1 = 1, the up / down counting means is not supplied with a count pulse. , The up / down counting means is instructed to down, the data clock DCLK is given to the address counting means, and when Ai indicates Ji−Ji ₋₁ = 1 the data clock DCLK is not given to the up / down counting means. , Ai indicates Ji−Ji ₋₁ = 0, the up / down counting means also has a data clock.
It is assumed that the read position x of the original image data is designated by giving DCLK. That is, the read number x of the line buffer memory is determined by increasing or decreasing the count number of the data clock DCLK according to the scaling factor. Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

【Example】

 Referring to FIG. 1a, the device shown in FIG.
(Except for digital PRTs), even for digital copiers,
An image reading device that can also be used for facsimiles
It is installed in the exterior shown in FIG.
It The scanner SCR scans A3 originals at 400 dpi (pixels / images).
H) density, read at 6 bits / pixel (64 gradations),
This 6-bit data is adjusted by fading correction, MTF correction, etc.
Whether the original image data is "1" for printer or transmission
This is a device that converts into a binary signal / pixel of "0" and outputs it.
Note that these reading densities and the number of gradations are examples,
It does not have to be 400dpi and 64 gradations. The document surface DOC is illuminated by the light from the light source 5, and its reflected light
To read the A3 original lateral direction (297 mm) at 400 dpi,
The pixel image sensor 7 receives it. The image sensor 7 converts the optical signal of the document DOC into an electrical signal.
Then, the signal is amplified to a predetermined level by the amplifier 22.
Next, depending on this concentration, analog signals with different voltage levels
The A / D converter 23 is a 6-bit digital signal,
It is converted into image data. Next, there are variations in the sensitivity of each element of the 5000 pixel sensor 7.
Also, a system for correcting uneven illuminance of the light source 5 in the A3 document horizontal direction
Fading correction is performed in circuit 24. In the embodiment shown in FIG.
Perform after wading correction. Shading correction
Things to do before circuit 24 and after the next MTF correction circuit 29
Is also possible. After the scaling process, the circuit 29 performs MTF correction.
And the binarization circuit 30, "1" depending on a certain threshold level
Binarized to "0" or printer part or transmission processing
Output to the department. Or, the gradation processor 31
Converted to a certain “1” or “0” and output to the transmission processing unit
It It should be noted that Fig. 1a shows a mode of outputting to the printer PRT.
are doing. In such a flow of image data, the scaling process
In the figure, the parallel 6-bit latch 25
Calculator 28, microprocessor 35, RAM3 and sampling
It is executed by the scaling processing device composed of the circuits 64 and 65. This scaling processing apparatus uses the new sampling point i after scaling.
The function to determine the position, the original image data around the new sampling point i
Function to extract original image data at data position x
The pulling point i and the extracted original image data position x (Ji)
Magnified image data is calculated from the distance and extraction data
Have the function of In FIG. 1a, first, the latch 25, the data distributor 26, and the
RAM1 and RAM2 as in-buffer memory and data
In the future, the rectifier 27 determines the sampling point x and determines the image data.
When extracting the data and calculating the scaled image data,
Multiple original image data to be referred to for double image data calculation
In order to extract each time
Interpolation method (embodiments shown in FIGS. 1a, 2a and 4)
Then, for every 2 pixels, the interpolation method with 4 peripheral pixels (see Fig. 3a
In the embodiment, it is a group for every 4 pixels.
For example, in Figure 12, the new sampling point0Is Sij and Sij₊₁Between
Data selector 27, Sij and Sij₊₁(The first
Examples shown in FIGS. 1a, 2a and 4) or Sij
_-1, Sij, Sij₊₁， Sij₊₂(At the example of FIG. 3a) at a time
It means to start out. Here, the above-mentioned method and
Inter-method (Examples shown in FIGS. 1a, 2a and 4)
The formula is the interpolation method using the four surrounding pixels (the embodiment of FIG. 3a).
It The specific method is to sequentially synchronize with the data clock DCLK.
Latch the input original image data Y (Fig. 6) with DCLK
25 memories (DCLK1 pulse cycle delay memory)
Can be implemented by If there are 2 pixels, one stage of latch 25 (1a
(Examples shown in FIGS. 2a and 4) 3 for 4 pixels
Stage latch 25₁~twenty five₃Can be realized by (Example of Figure 3a)
Noh. Next are RAM1 and RAM2 for line memory.
Is 2 pixels (the implementation shown in FIGS. 1a, 2a and 4)
Eg) or a group of 4 pixels (embodiment of FIG. 3a) 50
It is a memory that stores 00 pieces, and has a two-stage configuration for input and output.
When one (RAM1) is input, the other (RAM2) is output,
With the configuration that I / O is reversed when one line is finished
is there. This is an inversion operation with the line sync pulse LSYNC.
The output a of the T flip-flop 36 is applied to the data distributor 26.
Therefore, when a is H, the data distributor 26 is used as A output and RA
Designate M1 for writing (W) and output another output b
When the data is given to the rectifier 27 and b is L, the data selector 27 is set to B.
Performed by reading RAM2 as output (R)
Be done. The address of this line memory RAM1, RAM2
When input (write), counters 38 and 43 are counted in synchronization with DCLK
Use the address obtained by uploading as it is, but output
At the time of reading (reading), this address is changed. When outputting
The dress is just the sampling point i of the scaled image data.
The previous original image data sampling position x = Ji. When there is a sampling point i of the scaled image data, Sij
And Sij₊₁, And the next sampling point is
Once Sij and Sij₊₁Read address counter
Stop, Sij₊₂And Sij₊₃If you move between
Advance the dress counter by two, Sij₊₁And Sij₊₂Moved between
In this case, the read address counter is incremented by 1 as usual.
It When expanding (R ≧ 100), the operation to increment the counter by one
And the action of stopping the counter causes a new sample
Determine the position of the dot. At the time of shrinkage (R <100), the coun
By the combination of the action of advancing one
Determine the position. Reduction is considered up to 50% with this device
Therefore, the counter may be advanced by one or two.
However, if the reduction is less than 50%, proceed 3 or more.
There is also a possibility. Where and how many read address counters to increment
This information is calculated by the microprocessor 35 according to the magnification R%.
It is calculated in advance. Sampling points of scaled image data
For the original image data position x immediately before i, the start position is set to 0.
The sampling pitch P of the original image is 1 and the magnification is R
(%), 100i / R = Ji + Ri ... (4) i = 0,1,2,3, ... Ji: integer, Ri: decimal integer Ji. That is, the sampling point i is Sij and Sij₊₁Is between
Then, the sampling position x of the original image data is Ji.
It Therefore, as i increases, the integer part Ji of 100i / R becomes 1
When the number increases, the read address counter is also incremented by 1,
If the integer part Ji of 100i / R increases by 2 as i increases,
Unta has also advanced two, and 100i / R's integer part Ji has not advanced one
In this case, the counter may be set not to advance. Well
In addition, the fractional part Ri of 100i / R is the distance r between Sij and the i-corresponding position 0.
₁become. This distance data r₁Is the scaled image data calculation after
Will be used in. The microprocessor 35 uses i = 0 to R in the above equation (4).
Calculate to -1. That is, the expression (4) is performed at i = 0.
Integer J by arithmetic₀And minority R₀Calculation of equation (4) when i = 1
An integer J by₁And minority R₁, i = 2 for calculation of equation (4)
According integer J₂And minority R₂, ・ ・ ・, (4) with i = R-1
Integer J by arithmetic operation_R-1And minority R_R-1Is calculated. This
Such as i = 0 to R-1, only an integer Ji and a small number Ri
If only is calculated, this is the entire line length of the original image data.
Applicable to That is, in all cases, the scaled image data
Since the sampling point of the data has a cycle of every R, i =
The value of i = 0 for R, the value of i = 1 for i = R + 1, and the value of i = 1
= R + 2, the value of i = 2 is divided by ...
You can guess. In all the embodiments of the present invention described below, Ji and i = 0 to R-1
And Ri are calculated by multiplying the magnification R before the start of reading operation.
(%) Is specified, Ji and Ri are
Converted into data Ai and Bi that match the hardware
Written to RAM3. When image reading starts,
That is, during the scaling processing, i is synchronized with the data clock DCLK.
Is changed to a value that is incremented by 1 and the data corresponding to i (Ai, B
i) is read from RAM3. Note that, as another embodiment, a dedicated
A microprocessor or arithmetic means is provided to change the magnification.
In parallel with the process, the equation (4) is synchronized with the data clock DCLK.
Calculate and calculate the integer part Ji of 100i / R, that is, the original image data sample
The ring position x is directly used as the address, and the fractional part Ri is changed.
Distance data r which is a parameter for double image data calculation₁age
May be used. Next, the original image data from the line buffer RAM1 and RAM2
A description will be given of the relationship between the reading of 1 and the calculation of the scaled image data. The embodiment shown in FIGS. 1a, 2a and 4 has two pixels.
Original image data of Sij and Sij₊₁And image scaling based on Ri
Data is calculated (or). Line memory RA
6-bit original image data in M1 and RAM2 in line units
Alternately input as it is in synchronization with DCLK and input to this input.
In addition, the latch 25 is used to obtain Sij and the latch 25
Not in Sij₊₁To obtain 6-bit Sij and Sij respectively₊₁To
1-word 12-bit data as side-by-side 12-bit data
Alternately write to RAM1 and RAM2 line by line and write one
One word (12 bits) from the other when
Since the data is read in units, Sij
(6 bits) and Sij₊₁(6 bits) is given. In the embodiment of FIG. 4, the three-stage latch 25₁~twenty five₃Have
Latch data Sij of them_-1, Sij and Sij₊₁And latch
Data not through Sij₊₂But each 6 bits are parallel 24 bits
And written to RAM1 and RAM2,
Parallel 24 bits are read from them simultaneously. did
Therefore, the arithmetic unit 28 is_-1(6 bits), Sij
(6 bits), Sij₊₁(6 bits) and Sij₊₂(6 bits
Is given. In addition, the latch 25,25₁~twenty five₃Calculate with data selector 27
6-bit data only in RAM1,2
One line may be read and written. like this
When set to 1, the transmission of the scaled image data for one line is
Elementary (in case of Fig. 1a) or 3 pixels (Fig. 3a vs.
There is a delay, but the memory capacity of RAM1 and RAM2 is
Even if the number of pixels is 6 bits x 1 line each,
Becomes Therefore, a delay shift of several pixels is a problem.
The line buffer memory capacity is
It is effective in reducing the amount. Here, when the RAM1 is in the writing state (a = H, b = L), normal operation is performed.
The address counter 38 advances in the cycle of DCLK.
However, when RAM1 is in the output state (a = L, b = H)
Image of sampling position x (Ji) of original image data of mushroom
About the read address setting method for reading data
And explain. First, the first method is to count to the address counter.
This is a method of changing the clock frequency. Data black
Clock DCLK frequency to F₀Then, the frequency f at R% scaling_R
Is f_R= F₀・ 100 / R (Hz) ・ ・ ・ (5) In this scheme, F₀Against f_RThe difference between the original image and zoom
Accurate because it will be the deviation of the sampling point of the image itself
And certain. When reading RAM1 and 2, address count
F_RAnd sample the outputs of RAM1 and 2 with DCLK again.
(Latch) to obtain the desired combined data
be able to. With this method, equation (4) described above is used.
The information about the integer Ji is unnecessary in the calculation result of. Only
Then, in this embodiment, the scaling factor R% is set to, for example, 50 to 400%.
If the minimum unit of R is 1%, 350 pairs of pulses f_R= F
₀・ 100 / R is required. This is a dedicated microprocessor
Create with the service. The second method is to adjust the calculation result of equation (4) above.
Paying attention to the number Ji, the previous scaling image data sampling position Xi
_-1And the sampling position Xi this time, (1) When reduced, the integer part is increased by one (Ji-Ji_-1= 1) when Ai ＝
H The integer part is increased by 2 (Ji-Ji_-1= 2) When Ai ＝
L (2) At the time of expansion The integer part is increased by 1 (Ji-Ji_-1= 1) when Ai ＝
H The integer part has not increased (Ji-Ji_-1= 1), the sequence [Ai] of Ai = L is defined from i = 0 to R-1 and stored in RAM3.
Write in (before reading). This is Fig. 1a, 2a
Common to all of the embodiments of Figures, 3a and 4
It Then, in the embodiment of FIG. 4, which is an embodiment of the present invention,
Is the data pulse DCLK and DC
Prepare a pulse 2DCLK with twice the frequency of LK. Scaled image
During data operation, Ai is read from RAM3 and read
Read i = 0 to R-1 repeatedly. The fruit of this Figure 4
In the example, the line memory (RAM1
Or an address counter (38 or
The count pulse of 43) is switched so that it becomes DCLK when Ai = H and 2DCLK when Ai = L. When expanding (R ≧ 100), add
The count pulse of the response counter 38 or 43 is Ai and DCLK.
By ANDing, when Ai = H, cow
Count up, do not count when Ai = L, and do like
It All embodiments of the invention have RAM3, which is a micro
Based on the result of the equation (4) calculated by the processor 35,
Store Ai. This RAM3 also has different data in each embodiment.
It also stores the data Bi. The contents of Bi will be described later. In this way, Ai is stored in RAM3 before image reading,
This is read during image reading and read-out based on Ai.
When the dress is set, it is adjacent to RAM1 and RAM2 at the same time.
Data Sij and Sij₊₁But (the fruit of Figures 1a, 2a and 4
Example), or simultaneously with adjacent data Sij_-1, Sij, Sij₊₁， Sij₊₂
(In the embodiment of FIG. 3a), in conjunction with being read,
As will be described later, the calculator 28 for calculating the scaled image data
Simpler configuration. In the count pulse switching method of the embodiment shown in FIG.
When large (R ≧ 100), when Ai = L, ENAB of counters 38 and 43
The LE terminal may be set to L to stop counting. The third method is performed by the embodiment shown in FIG. 1a.
is there. The address counters 38 and 43 themselves use the data clock D
Continue counting up with CLK. And address
Unta 38,43 and another one up and down cow
, 38, 43, and specify down when expanding (R ≧ 100),
When reducing (R <100), specify up. And this
The up-down counters 39 and 44 count only when Ai = L.
Input, AND (logical product) of DCLK and Ai. With this, for example, when reducing, the first Ai = L
Set the down counters 39 and 44 to 1 and adder 37 and 42
Add 1 to the values of the dress counters 38 and 43 and read RAM1 and RAM2.
Use as the origin address. Furthermore, up / down with the next Ai = L
Set the counters 39 and 44 to 2, and set the counters of the address counters 38 and 43 to
Unt value is added, and so on
Determine the location x (Ji). For enlargement, read address
The address must be read without shifting the address.
Counters 38 and 43 count up, so compensate for this
Therefore, on the contrary, pull one by one with Ai = L.
The down counters 39 and 44 are decremented. Next, a method of calculating the scaled image data will be described. First
The example shown in Figure 1a implements the method described above.
Yes, the embodiment shown in Figure 2a implements the method described above.
The embodiment shown in FIG. 3a is the same as the method described above.
Is what you do. Explain how to perform these methods
I do. Closest pixel setting method (embodiment of FIG. 1a) The calculation method of this method is relatively simple. In Figure 5, Si
j and Sij₊₁Of the scaled image data sampling position i (
In 12 figures0) Should be selected closer to.
Based on equation (4), the integer Ji and the minority Ri are
When calculated by the processor 35, the minority Ri is0And Sij
Distance r₁/ P (P is the sampling pitch of the original image data
In the embodiment, if P = 1) is 0.5 or less, Sij is selected.
If it is larger than 0.5, Sij₊₁You should choose
Yes. In the embodiment shown in FIG. 1a, the microprocessor 35
When Ji and Ri are calculated and Ai described above is calculated
, R₁If / P is 0.5 or less, set Bi = H and be greater than 0.5
For example, if Bi = L, the sequence Bi is also calculated, and Bi together with Ai is RA.
Write to the same address on M3. This is the process before image reading
Is. When image reading starts, data clock DCLK
Ai and Bi are read from RAM3 in synchronization with
As a rect signal, Sij is selected when Bi = H and Sij is selected when Bi = 1.
₊₁Of the data set that constitutes the arithmetic unit 28 in this embodiment.
Giving to Lector 28a. Proximity Pixel Distance Linear Allocation Method (Example of Figure 2a) This method becomes more complicated. The above formula (1)
This is because it is necessary to perform arithmetic. In this case the problem
Is the distance r₁/ P or r₂It is the accuracy of / P. Decimal point
You may think up to the first place, that is, in 0.1 increments
It is necessary to see it in detail, or as P is divided into 4
In other words, is it okay if it is about 0.25
It This problem is caused by image reading devices and digital copiers.
How much accuracy do you need as a fax machine?
This is a problem of image reading equipment, digital copying machines,
It corresponds to the required image quality in Axsimile. Arithmetic processing
Seen from r₁/ P, r₂/ P is the reciprocal of the power of 2
Is preferred. This is for operations such as 1/2, 1/4, 1/8, ...
This is because it is possible only by bit shifting the data. So
First, from the calculation result of equation (4), Ri = r₁/ P to 0.25 (
1/4) Divide into small pieces. That is, the smallest unit of Ri
Is 1/8, and the Ri area division is 1/4. As an example,
Try to divide it as follows. 0 ≦ r₁Ri / r when / P <1/8₁/ P = 0, Bi = 0 1/8 ≦ r₁Ri / r when / P <3/8₁/ P = 1/4, Bi = 1 3/8 ≦ r₁Ri / r when / P <5/8₁/ P = 1/2, Bi = 2 5/8 ≦ r₁Ri / r when / P <7/8₁/ P = 3/4, Bi = 3 where 7/8 ≦ r₁When / P <1,0And Sij₊₁As much as
Since it is a place, make such a classification and Bi = 4
However, in this case, Bi requires 3 bits.
Therefore, from the hardware configuration, x in this case
Raise it by 1, increase the integer Ji by 1 and increase the decimal Ri by0
And then0Is Sij₊₁And Sij₊₂Between them, set Bi = 0
It is preferable that Bi is a 2-bit signal. the above
Similarly, write this Bi along with Ai to the same address in RAM3.
Imprint In Figure 2a, which implements this method, the distance is divided into four
Depending on the separation (Bi = 0-4), A ・ Sij + B ・ Sij₊₁= 0ik (6) where A is r₁Coefficient corresponding to / P, B is r₂Coefficient corresponding to / P, Sij, Sij₊₁Is the content of 6-bit data, 0ik is the content of scaled image data (6 bits), and A and B of are determined, so there are four types of A · Sij and B · Sij.₊₁
, And select one by one for Bi-compatible data selector
28b, 28c, adder 28d to select the scaled image data
Get 0ik. In the embodiment shown in FIG. 2a, the function corresponding to Bi is
The numbers A and B are set as shown in Table 1 below. The reciprocal of a power of 2 such as 1/2, 1/4 is the bit number of the signal line.
The hardware configuration is very easy because
It A modified example of the arithmetic unit 28 shown in FIG. 2a is shown in FIG. 2c. 2c
The arithmetic unit 28 shown in the figure comprises a ROM 28g. Beforehand Sij
(6-bit minimum value to maximum value), Sij₊₁(6 bits
Scaled image data determined by the minimum and maximum values and Bi
0ik is calculated and it is written in ROM28g. Picture
During image reading-magnification processing, Sij, Sij₊₁ROM 28g address
The variable-magnification image data 0ik is read as a scan. Sij is 6 bits
To, Sij₊₁Is 5 bits (the coefficient B is 1 or less, so
ROM is 28g because Bi is 2 bits.
Is an 8k x 8-bit ROM with an address of 13 bits.
Then, the calculation to be done in advance can be done without much difficulty. Strange
The hardware configuration for double image data calculation is very simple.
It Cubic function convolution This method is very complicated as shown in the above equation (3).
It requires calculation and seems unsuitable for hardware implementation.
However, even with the above-mentioned method, accurate scaling is possible.
it can. Similar to this method, the problem of distance accuracy
But here as well as γ₁/ P is divided into four
Consider the case. The division method is exactly the same. The above equation (3) can be simply rewritten as A. Sij_-1＋ B ・ Sij ＋ C ・ Sij₊₁＋ D ・ Sij₊₂＝ 0ik ・ ・
・ It becomes (7). Note that the denominator of equation (3) is a normalization coefficient.
Can be excluded from the parameters. From the above equation (2), γ₁/ P = 0,1 / 4,1 / 2,3 / 4
The calculation of A, B, C and D in the case is as follows.Based on this coefficient,
Similarly, there are four types of A ・ Sij_-1, B ・ Sij, C ・ Sij₊₁, D ・ Sij₊₂
(Sij, etc. is 0-63), prepare one by Bi
There is a method of selecting one and adding four. However, in this case
, Is different from each time, and each calculation is a little troublesome.
Yes, the hardware is a little more complicated. There hard
Coefficients A, B, C and
And D are approximated as shown in Table 2 below and rewritten. However
At this time, it is necessary that A + B + C + D = 1.
is there.This is because the denominator of the coefficient is less than 8 and depends on the hardware.
Counting will be much easier. The embodiment shown in FIG.
2 Use the coefficients in the table to calculate the scaled image data of
I am trying. Also in this example, it is possible to use the ROM as shown in FIG. 2c.
Conceivable. To do so, please refer to Figure 3c.
Use ROM63. The address of ROM63 is Sij_-1To 3
6 bits to Sij, Sij₊₁5 bits for Sij₊₂3 bits
2 bits for G and B, making a total of 17 bits. 128 memory
Since it becomes k bytes, the data stored in advance in ROM 63
The calculation of data is a little difficult. But this way
The hardware for computing scaled image data
Become. Next, the hardware configuration and operation of the embodiment of the present invention will be described.
I do. First, a description of FIGS. 1a, 1b, and 1c
I do. The original image data read by the scanner SCR is 1
The shading correction circuit 24 for each line
For data, parallel 6 bits (6 bits are 1 screen
It is given to the serial in units of 1 word indicating the elementary concentration).
Circuit 24 has a similar data structure and a similar transfer type.
In the formula, 1 line during 1 cycle of line sync pulse LSYNC
Minutes, each word in the line is synchronized to the data clock DCLK
And supplies it to the latch 25 and the data distributor 26. Circuit 25
The output of is the pixel data Sij₊₁Latch 2 when
The output of 5 is the data Sij one pixel before that, and these data
Data Sij and Sij₊₁However, parallel 12-bit data distributor 26
Given to. On the other hand, the T flip-flop 36 outputs the line sync pulse LS.
Output Q of each pulse of YNC,QSignal level of
Since the data of the first line is given,
Data distributor 26 provides the 12-bit input to RAM1.
And RAM1 is designated for writing. At this time, the data
The lector 27 gives the 12-bit data of the input terminal B to the arithmetic unit 28.
Well, RAM2 is designated for reading. Second line data
Is given to the data distributor 26,
26 provides the input 12 bits to RAM2, and RAM2
It is specified. At this time, the data selector 27 operates at the input terminal A 12
Bit data is given to the calculator 28, and RAM1 is designated for reading
Is done. In this way, the data of two adjacent pixels on the nth line
Written in RAM1 in parallel, next to the n-1th line
The data of two adjacent pixels are read out from RAM2 in parallel.
The data of the adjacent two pixels of the (n + 1) th line is RAM2 in parallel.
, The data of two adjacent pixels on the nth line is written
It is read from RAM1 in parallel. Similarly, RAM1 and
RAM2 is switched by line sync pulse LSYNC and alternates
Is specified for writing and reading. In this way
Data of adjacent two pixels on the n-th line are combined in parallel
When writing 12-bit data to RAM1 or RAM2,
Combine the data of two adjacent pixels of the n-1th line in parallel
12-bit data is read from RAM2 or RAM1.
It is given to the calculator 28. That is, the arithmetic unit 28 has a circuit
Just one line behind the data output by 24,
The original image data is given in the form of the data of adjacent 2 pixels.
Be done. In this way, the data buffer memory RAM1, RAM2
Read data from the input to
Udo is delayed by one line. The sampling circuit 64 stores the read / write address of RAM1.
The sampling circuit 65 determines the read / write address of RAM2.
Meru. First, the sampling circuit 64 will be explained.
When writing is specified, the signals a = H and b = L.
And gate 40 is off (gate closed) and up
The count pulse is not given to the down counter 39,
The output of will remain at 0. To address counter 38
Data clock DCLK is given as a count pulse
Therefore, one data clock DCLK pulse arrives
Und up. The adder 37 is of the counters 39 and 38.
Add the count data and add the sum data to RAM1.
Given as data. As a result, the data of two adjacent pixels
12-bit data in parallel with the data clock
Data is sequentially written to RAM1 in synchronization with DCLK. Ie 1
All data for the line is written to RAM1. When RAM1 is designated for reading, a = L, b
= H, the AND gate 40 operates when the signal c is L.
When it is on (gate is open), data is stored in the up / down counter 39.
The clock DCLK is given as a count pulse. signal
It counts up when d = H (reduction), and d = L (enlargement).
Down). Signal c already explained
It is the data Ai that was
Of. When reading, the counters 39 and 38
The sum of the count values becomes the read address of RAM1. c =
In case of L, when d = H, every time DCLK appears 1 pulse
Then, the counter 39 counts up by 1 and the RAM1 is read.
When the address advances by 2 and d = L, DCLK has 1 pulse
Each time it appears, the counter 39 counts down by 1 and RA
Note that the read address of M1 stalls.
c = Ai. The sampling circuit 65 has exactly the same configuration as 64,
The difference is that the AND gate 45 receives the a signal instead of the b signal.
It This is because RAM1 is read (b = H, a = L)
Write to RAM2 and write to RAM1 (b = L, a
= H), read RAM2 and read
Address as the sum of the count values of counters 44 and 43.
It is. Here, Ai will be described. Microprocessor 35
Responds to the image reading start instruction (ST changes from L to h).
Answer the specified scaling factor R% and based on this
And play Ji and Ri for each of i = 0 to R-1
If R <100 (reduction), Ji-Ji-1 ≧ 2 and A
Let i be L, Ji-Ji-1 ≦ 1 and Ai be H, and R ≧ 100 (expansion
In the case of (large), Ji−Ji−1 ≧ 1 and Ai is H, and Ji−Ji−
When 1 ≦ 0, Ai is L, and when Ri ≦ 0.5, Bi is H and R
When i> 0.5, set Bi to L and set Ai and Bi to RAM3
Store in dress R-i. In this memory operation, the microprocessor 35
Data A corresponding to i = 0₀And B₀OR gate before writing
1 pulse is given to 49, and the data indicating R is
Load it to your computer 48. And A₀And B₀To RAM3
And give one pulse to OR gate 51, and address counter
Increment 48 by 1 and data A corresponding to i = 1₁And
B₁Is given to RAM3, and then one pulse is given to the OR gate 51.
It Such an operation is performed until i = R-1. This
Data A corresponding to i = 0 at address 0 of RAM3₀And B₀
But the data A corresponding to i = 1 at address 1₁And B₁But,·
..Data A corresponding to i = R-1 at address R-1_R-1And
B_R-1Will be written. Then, the scanner SCR is instructed to read the image and the image is actually printed.
When starting image reading, use line sync pulse LSYNC.
The data indicating the specified magnification R% is set in the address counter 48.
Each time the data clock DCLK appears one pulse
Counter 48 increments by 1 and DCLK shows 1 pulse.
Each time it is read, the read address is increased by one, i
= 0 corresponding data A₀And B₀To i = day for R-1
Type A_R-1And B_R-1Are sequentially read out and the data Ai is transmitted.
No. c is given to the sampling circuits 64 and 65,
The data Bi is given to the data selector 28a of the calculator 28.
It The data selector 28a outputs Sij when Bi = H and when Bi = L
Sij₊₁Is output as scaled image data 0ik. This output motion
The operation is synchronized with the data clock DCLK. The scaled image data 0ik is given to the MTF correction circuit 29,
29 to the binarization circuit 30 and the gradation processor 31.
In this embodiment, the gradation processor 31 has 64 types of density compatible
ROM with gradation expression data distribution pattern and 64 counts
Cyclic line counter and 64 cows to initialize with
Sun clock data clock counter to be initialized
The read address of the ROM is 0i
k, line count data and data clock count
Set with data. That is, one pattern of ROM is specified by 0ik.
The main scan address of the pattern
The counter and the sub-scanning address can be specified by the line counter.
Read the 1-bit image data in the pattern
You Microprocessor 35 directs the output of binary data
(I = H), the gate circuits 32 to 34 are binarized.
The output of the circuit 30 is instructed to output the gradation data (i =
L), the output of the gradation processor 31 is output to the printer PRT.
Force Next, the scaling processing control operation of the microprocessor 35
Description will be made with reference to the drawings and FIG. 1c. First see Figure 1b
I do. The power is turned on (Step 1:
(The word "up" is omitted) and the microprocessor 35
Set the I / O port to the standby level and
Data, counters, timers, flags, etc. (2).
Next, read the data R that indicates the specified scaling ratio R%, and register
Store in Rs (3) and set L to output port g
(4). That is, when AND gate 50 is turned off (gate closed)
Then, the address counter 48 has an external count pulse.
Set so that it is not given from. Next, output port n
, The data stored in the register Rs and indicating the specified scaling ratio Rs%
Set (5) to preset the address counter 48
A data input terminal P is added. Then, one output port f
Rout is output (6) and Rs is set low to the address counter 48.
To This initializes the address counter 48 (initial
The address has been set). The microprocessor 35 then sets RAM3 to write
(7), which indicates 0 in the contents of the internal address register i
(Register clear) (8). Due to this
I = 0 is set. Then clear register j
Then, H is set in the registers Bi and Ai (9). So
And store the contents Bi and Ai of registers Bi and Ai in RAM3.
(10). At this stage, i = 0, so the RAM3 address
Dress R, B₀= H and A₀= H has been written
It Then, the contents of register i are incremented by 1 (1
1). This will change the value of i to a value that is one greater than the previous
It has been done. Then at this stage i = 1 and
100 i / Rs = J because i ≧ Ri + 1?
i + Ri integer Ji and minority Ri calculated (13)
Math register Ji_-1Move the contents of the calculated value register Ji to
(14a), the integer value Ji is stored in the calculated value register Ji this time.
(14b), then in steps 15-17, set Bi and
Set Ai at steps 18-25. And one output port h
(22) RAM3 write address is 1 ink
The write address, advance the write address, and
Write the set Bi and Ai in the RAM3. Same as below
Then, change i to a value one larger (11) and play Ji and Ri.
Calculate (13) and set Bi and Ai based on them and Rs
(15 to 25), update the write address of RAM3 (22),
Write Bi and Ai to RAM3 (10). In this way, i
= Rs + 1, it corresponds to each of i = 0 to Rs-1.
Since all Bi and Ai are written in RAM3,
Proceed from step 12 to the scaling process control during image reading in Fig. 1c.
Mu. When you proceed from step 8 to step 9,
Dress 0 to A₀= H is written, but this is Ji-Ji_-1To
Does not correspond exactly. Because at this stage Ji_-1Unknown
Because it is. However, when i is Rs-1,
Indicates the Rs countover of the counter 48 next (i = Rs).
Initialize the counter 48 and reset i to 0
Therefore, i = 0 and i = Rs are the same. Therefore, i = 0
In A₀Can be replaced by that of i = Rs. And i
= J when Rs-1_R-1Ji_-1Can be used as. Therefore,
In step 12, until i = Rs, calculation of Ai and Bi and RAM3
To see how the memory is completed to. That is, i = 0 to
It is sufficient to store Ai and Bi up to Rs-1, but i = Rs
(This is synonymous with i = 0) also calculates and stores Ai and Bi
I am trying. At this i = Rs, the counter 48 controls Rs.
The write address of RAM3 is set to 0 due to the overrun
So B written in step 9₀And A₀But B_Rs, A_Rto s
It will be rewritten. This will allow steps 9 and 10
A written₀Has been updated to the correct value. Snap 12 to control scaling processing when reading the image in Figure 1c
Then, the image reading start instruction signal ST indicates the start of reading.
Wait until it reaches H (26) and do not receive the reading start instruction.
While it is idle, read the input magnification instruction data R
Check if is the same as the value stored in register Rs
Yes (27). If it is not the same, the designated magnification R has been changed.
So, go back to step 3 in Figure 1b and repeat
Of the data Bi and Ai corresponding to the new designated magnification R
Calculate and write to RAM3. When the image reading start instruction signal ST becomes H, scan
Check if SCR is ready (28), printer PRT
Check whether it is ready (29) and either
If it is not a day, wait for both to become ready. If both SKYANA SCR and printer PRT are ready,
Binary image processing (document: text image processing) is instructed
If it is, set H to output port i (31)
The output of the binarization circuit 30 is applied to the printer PRT so that the
Tone circuits 32 to 34 are set and gradation image processing (photo image processing)
Is set, set L to output port i
(32) The output of the gradation processor 31 is applied to the printer PRT.
Set the gate circuits 32-34. Next, the microprocessor
The server 35 refers to the contents of the specified scaling register Rs and
Check if a small amount or an enlargement is specified.
(33), output port when reduction is specified
Set d to H (34), and up / down counter 39
And 44 are set to upcount. Magnification specified
If it is, set L to the output port d (35).
Set down counters 39 and 44 to down count
I do. Next, set RAM3 to read (36), and output port g
Set H (37) and turn on AND gate 50 (gate
Open). Next, scan the SKYANA SCR and printer PRT
Give the bell start signal ATS (38). Sukiyana SCR reads the image in response to ATS becoming H
Start the line sync pulse LSYNC, data lock DCLK and
And original image data are serially output line by line.
Write the data of the odd-numbered line to RAM1.
The data on the even-numbered line is written to RAM2 and the odd-numbered line is written.
IN data is being written to RAM1 and even
Data on the even numbered lines are read out from RAM2.
Data on the odd numbered lines when the data is being written to RAM2.
Is read from RAM1. That is, in the form shown in FIG.
Image data is written to the line buffer memory RAM1 and RAM2.
And read from it. During this image reading, the address counter 48
Pulse LSYNC and the count-over generated by itself
B signal (issued each time the specified magnification Rs% is counted
Data clock DC
Count up LK. This allows the address counter
The address given to RAM3 by 48 is the line sync pulse LSYNC.
Becomes 0 when 1 pulse arrives, and then DCLK becomes 1 pulse.
Each time it is called, the value will increase by 1 and next to the maximum value Rs-1.
Is started by the count-over of the address counter 48.
It becomes 0 again and becomes 1 more value every time DCLK arrives.
It This is repeated during one cycle of the line sync pulse LSYNC.
Will be returned. RAM3 is set to read, so Ai
And Bi, i = 0 to R−1 are read from RAM3 sequentially from i = 0.
If it is read out and read up to i = R-1, then i = 0 again
It is read out sequentially, in synchronization with DCLK.
Ai is output as the signal c to the inverters 41 and 46,
Bi is provided to the data selector 28a. c = Ai = H (Ji-Ji when reduced_-1≦ 1, Ji-Ji when expanded_-1≧
In 1), AND gates 40 and 45 are off (gate
(Closed), the count values of counters 39 and 44 do not move,
Same sampling pitch (P = 1) as the original image data
The scaled image data is sampled at the sampling pitch.
It In this period, the image magnification is 1. That is, scaling
The image data is the original image data (thinned,
I did not write it twice.) c = Ai = L (Ji-Ji when reduced_-1≧ 2, when expanded Ji-Ji_-1
In the case of <1), the counters 39 and 44 are
Address counters 38 and 43 are
Counter 39,44 counts as if it hung up
Since it goes up, reading of RAM1 and 2 at the arrival of one DCLK pulse
The output address is increased by 2 and the original image data is skipped by 1 pixel.
It will be sampled every time. Cow at the time of expansion
Address 39,33 are down-counting,
Counters 38 and 43 count up, while counters 39 and 44
Counts down, so even if DCLK arrives, RAM1 and RAM2
The read address does not move and the same pixel of the original image data
The data will be repeatedly sampled. Corresponding to the specified magnification R by the above sampling operation
Original image data is sampled at different pitches, Bi = H
When (Ri = ≦ 0.5), the data selector 28
Sij of the pulled original image data is set to 0ik, and Bi = L (Ri
> 0.5), the data selector 28 is
Sij of the original image data₊₁Is output as 0ik. As shown above, in the case of FIG. 1a, the method described above is used.
The scaled image data is set. 2a and 2b will be described. Fig. 2a Smell
The calculator 28 calculates the scaled image data 0ik as described above.
I do. That is, the four types of coefficients A in Table 1 and the image data Si
The data multiplied by j (0 to 63) is stored in the data selector 28b.
Applied to input ports a-d. Note that these a to d are the first
Corresponds to a to d in the right column of the table, where a is all Sij
I.e., Sij is the upper 5 bits of Sij in b
Data indicating the sum of 4-bit data, that is, 3/4 Sij
₊₁However, in c, the above 5 bits of Sij, that is, 1 / 2Sij, is
Is given the upper 4 bits of Sij, that is, 1/4 Sij. In addition, the four types of coefficients B in Table 1 and the image data Sij_-1And
The multiplied data is input port a to the data selector 28c.
applied to d. Note that a to d are also a to d in the right column of Table 1.
Data corresponding to each of d, indicating 0 in a, and b in b
Is Sij₊₁Upper 4 bits of 1/4 Sij₊₁But c is Sij
₊₁Upper 5 bits of 1/4 Sij₊₁However, d is Sij₊₁of
Data indicating the sum of upper 5 bits and upper 4 bits of data
Ie 3/4 Sij₊₁Is given. The outputs A and B of the data selectors 28b and 28c are
One of the inputs a to d depends on the signal Bi given to them.
If the data is one, and Bi is 0, the input a
Are output A and B, and when Bi is data showing 1, input
When force b is output A and B, and Bi is data showing 2
Is the data of which input c is output A and B, and Bi is 3.
Input d is output A, B. The value of this Bi is the first
It is shown in the table. The adder 28d outputs the data A from the data selector 29b and the data
The data indicating the sum of the output B of the rector 28c is used as the scaled image data 0
Output as ik. The selection data Bi of the data selectors 28b and 28c is RAM3.
In addition, it is pre-read before the image is read. The scaling processing control operation of the microprocessor 35 shown in FIG. 2a.
The work is similar to that of Figures 1b and 1c, except that
Scaled image data calculation by step 15 to 17 in Fig. 1b
Instead of setting the data Bi for the steps shown in Figure 2b
41 to 50, the data for calculating the scaled image data by
Data Bi (from Table 1) is set. You
That is, the decimal number Ri calculated with each value of i is 0 ≦ Ri
<1/8, 1/8 ≤ Ri <3/8, 3/8 ≤ Ri <5/8, 5/8 ≤ Ri <7/8, and
And 7/8 ≤ Ri <1, in steps 41-47.
If 0 ≦ Ri <1/8, the register Bi shows 0.
Set data (42) and register when 1/8 ≤ Ri <3/8
Set the data indicating 1 to the data Bi (44), and 3/8 ≦ Ri <5/8
In case of, the data indicating 2 is set in the register Bi (4
6) When 5/8 ≤ Ri <7/8, the data indicating 3 in register Bi is displayed.
Setting (48). When 7/8 ≤ Ri <1, Ri
Round up to 1 and update the contents of register j by 1
Then (49), 0 is set in the register Bi. like this
Bi set to is written in RAM3 together with Ai. The other scaling processing control operations are the same as those in FIGS. 1b and 1c.
Therefore, during image reading, the data set in this way
Bi is read from RAM3 together with Ai and data selector 28b
And given to 28c. As a result, the output of the adder 28d
The scaled image data 0ik is calculated by the above equation (6).
It will be. FIG. 2c shows a modification of the arithmetic unit 28 shown in FIG. 2a. this
In the example, ROM28g, Sij 0 ~ 63, Sij₊₁0 to 63, Table 1
4 types of coefficient A shown in Table 1 and 4 types of coefficient B shown in Table 1
As a parameter, the scaled image data calculated by equation (6) above is used.
Data 0ik stores those parameters as addresses
Has been done. The read address of ROM28g is the data selection
Sij, Sij output from Kuta 27₊₁And Bi, B
Coefficients A and B specified in i (Table 1) and Sij, Sij₊₁
Then, the scaled image data 0ik calculated by equation (6) is ROM 28g.
Read out. 3a and 3b will be described. Fig. 3a Smell
The calculator 28 calculates the scaled image data 0ik as described above.
I do. That is, each of the four types of coefficient A in Table 2 and the original
Image data Sij_-1Data multiplied by and is the data selector 5
2 shows each of the four types of coefficients B in Table 2 and the original image data S
The data obtained by multiplying ij and
Each of the four types of coefficients C and the original image data Sij₊₁Multiply by
The selected data is sent to the data selector 54 and the four types in Table 2
Each of the coefficients D and Sij₊₂The data multiplied by
Data selector 52 and that of the data selectors 52-55.
Coefficients A to D, each of which is specified by the data Bi (Table 2)
Indicates the value calculated by one type (4 types for each: Table 2)
The data is output and the sum of them is added to the scaled image data.
It is output from the adder 56 as data 0ik. Note that the complement device 57 converts the subtraction data (-1/8) into the addition data.
To convert data (convert subtraction to addition)
It The outputs A to D of the data selectors 52 to 55 are given to them.
One of the inputs a to d, depending on the signal Bi
When Bi is data indicating 0, the input a is the output A to
When the data is D and Bi is 1, the input b is output.
If the data are forces A to D and Bi is 2, input
When c is the output A to D and Bi is data indicating 3
Has an input d as outputs A to D. This Bi value is shown in Table 2.
Is shown in. The adder 56 is the data selector 52
Data indicating the sum of outputs A to D of
Output as k. The selection data Bi of the data selectors 52 to 55 is stored in the RAM3 as an image.
It is pre-read before reading. The scaling processing control operation of the microprocessor 35 shown in FIG. 3a.
The work is similar to that shown in Figures 1b and 1c.
However, the scaled image data according to steps 15 to 17 in Fig.
Instead of setting the data Bi for data calculation,
Steps 41 to 50 are used to calculate the scaled image data.
Data Bi (for Table 2) for setting
There is. That is, the small number Ri calculated with each value of i
However, 0 ≦ Ri <1/4, 1/4 ≦ Ri <1/2, 1/2 ≦ Ri <3/4, 3/4 ≦ Ri
<7/8 and 7/8 ≤ Ri <1, step 4
Check 1 to 47, and if 0 ≦ Ri <1/4, register Bi
Set data indicating 0 (42), and when 1/4 ≦ Ri <1/2
Sets data indicating 1 to register Bi (44), and
When ≦ Ri <3/4, set the data indicating 2 to register Bi.
(46), and when 3/4 ≤ Ri <7/8, 3 is shown in register Bi.
Set data (48). When 7/8 ≤ Ri <1
Rounds Ri up to 1 and increments the contents of register j by 1.
It is updated to a number (49) and 0 is set in the register Bi.
The Bi thus set is written in the RAM 3 together with Ai. The other scaling processing control operations are the same as those in FIGS. 1b and 1c.
Therefore, during image reading, the data set in this way
Bi is read from RAM3 together with Ai and data selector 52-
Given to 55. This causes the output of adder 56
The doubled image data 0ik is roughly calculated by the above equation (7).
Will be things. FIG. 3c shows a modification of the arithmetic unit 28 shown in FIG. 3a. This
In the example, ROM63, Sij_-10-63, Sij 0-63, Sij₊₁
0 ~ 63, Sij₊₂0 to 63, 4 types of coefficient A shown in Table 2,
Parametric 4 types of coefficient B, 4 types of coefficient C and 4 types of coefficient D
Scaled image data calculated by equation (7) above as a meter
0ik is stored with those parameters as addresses
ing. The read address of RAM63 is the data selector 2
Sij output from 7_-1, Sij, Sij₊₁， Sij₊₂And Bi
The coefficients A to D (Table 1) specified by Bi and Sij
_-1, Sij, Sij₊₁， Sij₊₂Then, the scaled image calculated by equation (7)
Data 0ik is read from ROM63. Fourth Embodiment (FIG. 4) Only the components of the fourth embodiment different from those of the first embodiment are
Shown in the figure. In this fourth embodiment, the sampling circuit 64 and
And 65, and the other parts are the first real
Same as the example, except the sampling circuits 64 and 65
May be the same as in the second and third embodiments. The sampling circuit 64 shown in FIG.
When specified (a = H, b = L), AND gate 6
8 and 69 are off, and gate 67 is on
To count up the address counter 38 with DCLK.
It In other words, each time DCLK arrives, the original image data is
Data into RAM1. When RAM1 is specified for reading
(A = L, b = H), the AND gate 67 is off.
And, when it is reduced (d = H), AND gate 68 is also off.
Yes, corresponding to the data Ai, when it is H, DCLK
2DCLK when Ai is L, AND gate 71 or 72
And orgate 70 and andgate 69 and orage
Give to the counter through To 66. When enlarged (d = L)
DC is when AND gate 69 is off and Ai is high.
LK through AND gate 68 and OR gate 66
It is given to the counter 38, and when Ai is L, the clock is
Not given to Unta 38. The sampling circuit 65 has the same configuration as 64, but the signal a
And and b are swapped and given to AND gate 74, 75 and 76
I am trying to get it. This is because when writing to RAM1
When reading from RAM1, reading from RAM1 does not mean writing to RAM2.
This is because that. Configuration and operation of the above sampling circuits 64 and 65
Thus, in the fourth embodiment also, the first embodiment (Fig. 1a)
In the same manner as the above, writing to RAM1 and 2 and reading from RAM1 and 2 are performed.
Sampling is performed. That is, in the first embodiment,
Up / down counters 39 and 44 and adders 37 and 42
DCLK is duplicated when sampling original image data one by one.
Counts to 2 and advances the address by 2 for each DCLK pulse
However, in the fourth embodiment, in this case,
2DCLK is given to the address counter, and 1 pulse of DCLK is issued.
The address counter is incremented by 2 when
So that the address is advanced by 2 for each DCLK pulse.
I have to. In each of the embodiments described above, the scaling in the main scanning direction X is performed.
Is to do. The scaling in the sub-scanning direction Y is 100Li / R = Lj + Lr, where Li is the scaling image data sampling line No., Lj
Is an integer, Lr is a decimal, and an integer Lj and a decimal Lr
When Lr is 0.5 or less, the above-mentioned variable magnification image in the main scanning direction
If the data of the Ljth line of the data is Lr larger than 0.5,
By the time, Lj₊₁The data of the line can be
The final scaled image data is scaled in the scanning direction and is the Lith
You can remove it. This extraction is, in the above-mentioned embodiment,
The printer PRT refers to the magnification data R to perform the processing. As described above, in any of the examples of the present invention,%
Adjacent to the original image data according to the specified scaling ratio R of the unit
Objects at a specified pitch in synchronization with the data clock DCLK.
And the scaled image in synchronization with the data clock
Data 0ij is calculated and output, so real-time processing is possible.
That is, the scaled image data is synchronized with the reading of the original image.
can get.

【The invention's effect】

As described above, the image data scaling processing device of the present invention is
Original image data sampling position information, which is associated with each variable-magnification image data sampling position i based on the designated magnification R%, and position difference information indicating a difference between the original image data sampling position and the variable-magnification image data sampling position,
Scaling means for storing the original image data sampling position information and position difference information corresponding to the scaled image data sampling position i; scaling processing information memory means; i in synchronization with the data clock DCLK of the source image data. Reading means for reading the original image data sampling position information and position difference information corresponding to i from the scaling processing information memory means while changing them one by one; the data clock DCLK when R ≧ 100, and the data clock when R <100 2 of DCLK
Sampling means for counting the data clock 2DCLK having a doubled frequency to extract the original image data specified by the read original image data sampling position information and one or more original image data adjacent thereto, and the data clock A scaled image data setting means for determining scaled image data at a position i in correlation with the extracted original image data and the read position difference information in synchronization with DCLK;
It is possible to realize a high-accuracy, fine, wide-range zoom ratio, and a simple structure of a scaling processor that does not change the input data clock and output data clock of image data even during scaling.

[Brief description of drawings]

FIG. 1a is a block diagram showing the configuration of the first embodiment of the present invention. FIGS. 1b and 1c are flowcharts showing the scaling processing control operation of the microprocessor 35 shown in FIG. 1a. FIG. 2a is a block diagram showing an essential part of the second embodiment of the present invention. FIG. 2b is a flowchart showing a part of the scaling processing control operation of the microprocessor 35 shown in FIG. 2a. FIG. 2c is a block diagram showing a modification of the arithmetic unit 28 shown in FIG. 2a. FIG. 3a is a block diagram showing an essential part of the third embodiment of the present invention. FIG. 3b is a flowchart showing a part of the scaling processing control operation of the microprocessor 35 shown in FIG. 3a. FIG. 3c is a block diagram showing a modification of the arithmetic unit 28 shown in FIG. 3a. FIG. 4 is a block diagram showing the main part of the fourth embodiment of the present invention. FIG. 5 is a graph showing the value of the interpolation function used in the cubic function convolution method for calculating the scaled image data, where the horizontal axis represents the sampling position assigned to the scaled image data with respect to the sampling position of the original image data. The amount of deviation is shown, and the vertical axis shows the value of the interpolation function. FIG. 6 shows the data Y which is the image reading output of the scan SCR shown in FIG. 1a, the synchronizing clocks LSYNC, DCLK and the latch 25.
3 is a time chart showing the relationship of the data Z that is the output of FIG. FIG. 7 shows the line buffer memory RAM1, RAM shown in FIG. 1a.
2 write data, read data and line sync pulse L
It is a time chart which shows the relationship with SYNC. FIG. 8 is a perspective view showing the appearance of a conventional image reading apparatus. FIG. 9 is a side view showing main mechanical components of one conventional image reading apparatus. FIG. 10 is a side view showing main mechanical components of another conventional image reading apparatus. FIG. 11 is a plan view showing the image data distribution on the memory corresponding to images when screen image data for one page is stored in the memory for image data scaling by a conventional electrical method. . FIG. 12 is a plan view showing the relationship between the sampling position of the original image data and the sampling position of the scaled image data when the scaled image data is calculated by the distance linear distribution method between adjacent pixels. 1: Image reading device, 2: Contact glass plate 3: Original pressure plate, 4: Operation part 5: Fluorescent lamp, 6: Selfoc lens, 7: Image sensor, 8: Reflected light 9: Carridge, 11 to 13: Reflected light 14 : Lens, SCR: Scan DOC: Original 35: Microprocessor (calculation means) 48: Preset counter (readout means) 64,65: Sampling circuit (sampling means) RAM1, RAM2: RAM (buffer memory means) RAM3: RAM (variable magnification) Processing information memory means) 28: calculator (scaled image data setting means)

Claims (6)

[Claims] 1. Original image data sampling position information, which corresponds to each variable-magnification image data sampling position i based on a designated magnification R%, and a position indicating a difference between the original image data sampling position and the variable-magnification image data sampling position. Difference information and calculation means for calculating the difference image information; variable magnification processing information memory means for storing the original image data sampling position information and position difference information corresponding to the changed image data sampling position i; and synchronizing with the data clock DCLK of the original image data. Then, i is changed one by one, and from the scaling processing information memory means,
Reading means for reading the original image data sampling position information and position difference information corresponding to i; When R ≧ 100, the data clock DCLK is counted; when R <100, the data clock 2DCLK having twice the frequency of the data clock DCLK is counted, Sampling means for extracting the original image data specified by the read original image data sampling position information and one or more original image data adjacent thereto, and the extracted original image data in synchronization with the data clock DCLK. And a scaled image data setting unit that determines scaled image data at the position i based on the correlation of the read position difference information. 2. The calculating means calculates 100i / [designated magnification R (%)] = Ji + Ri, i = 0 to R-1, an integer 0 ≦ Ri <1, Ji is an integer, and an integer Ji and a small number Ri are calculated. Then, the Ji calculation value Ji _-1 when i is smaller by ₁ is held, and the sampling position change amount of the original pixel data corresponding to the R value and the Ji-Ji _-1 value is stored as the original image data sampling position information. The data Ai shown is calculated, and as position difference information,
The image data scaling apparatus according to claim 1, which calculates data Bi indicating which one of the small area divisions Ri is in 0 to 1. 3. Sampling means: buffer memory means for storing original image data for one line; means for alternately setting the buffer memory means for writing / reading; address counting means for giving a writing / reading position to the buffer memory means; When writing to the buffer memory means, the data clock DCLK is given to the address counting means as a count pulse, and when reading from the memory means, i is changed by 1 in synchronization with the data clock DCLK, and R <100. In the case of Ai, one of the data clock 2DCLK and the data clock DCLK having twice the frequency of the data clock DCLK is given as a count pulse to the address counting means, and when R ≧ 100, the data corresponding to Ai Reads the original image data by applying / cutting off the clock DCLK to / from the address counting means. The image data scaling apparatus according to claim (2), further comprising a sampling position designating unit that designates a position x. 4. The scaled image data setting means is such that Bi is Ri ≦ 0.5.
The scaled image data is the original image data at the specified position x, and the scaled image data is the original image data at the position x + 1 when Bi is Ri> 0.5. An image data scaling device according to item (2) or (3). 5. The scaled image data setting means adds the weight of Ri indicated by Bi to the original image data at the position x, and the weight of 1-Ri indicated by Bi to the original image data at the position x + 1. Is the scaled image data, and the scaling processing device for image data according to claim (2) or (3). 6. The scaled image data setting means uses the scaled image data as a cubic function parameter having as parameters the original image data at Ri and position x indicated by Bi and the three original image data before and after the original image data. The image data scaling apparatus according to claim (2) or (3), which is obtained by a volume method.