JPH0828818B2 - Encoding / decoding system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data encoding / decoding device used in a facsimile, an electronic file system or the like.

2. Description of the Related Art A conventional encoding / decoding device of this type will be described with reference to FIG. FIG. 4A is an overall system configuration diagram in which the encoding / decoding device is used in a facsimile system, and FIG. 4B is an operation timing diagram. As shown in FIG. 4A, the image data for one line is input from the scanner 63 to the image memory 62, and after the input is completed, an interrupt request is issued to the microprocessor (hereinafter referred to as MPU). Next, the MPU makes a coding process request to the coding / decoding device 64 in order to code the data input to the image memory 62. Accordingly, the encoding / decoding device 64 inputs the previously input image data into the device and sets it as a facsimile encoding method according to CCITT (International Telegraph and Telephone Consultative Committee) Recommendation T.4.
Processing such as H coding and MR coding is performed. After the processing is completed, another interrupt request is issued to the MPU to notify the end of the processing. By repeating this, the input and encoding processing from the image scanner 63 over the entire page is executed. FIG. 4B shows the operation timing of the repetitive processing in which the image data is DMA-transferred from the image scanner to the image memory for one line and then the one line is encoded. Similarly, in the decoding process, the iterative process of decoding one line and DMA transfer of image data from the image memory 62 to the printer 61 is performed. As another method, input / output multiple lines,
This is repeated as a unit of encoding / decoding to execute the encoding / decoding processing of the entire page. In either case, at the end of input / output of image data and the end of encoding / decoding, an interrupt request is issued to the MPU, and the next processing cannot be performed without an instruction from the MPU. Have in common.

Problems to be Solved by the Invention In the above-described conventional method, (1) the MPU must be interrupted each time processing of one line or a plurality of lines is completed, which increases the load on the MPU. ) Even if the processing in one line of the encoding / decoding apparatus is made high speed, the waiting time between lines becomes large because the next processing cannot be performed unless there is an instruction from the MPU. There was a problem that I could not make full use of my ability.

The above-mentioned problem is that the conventional encoding / decoding device is a subordinate device of the MPU, and cannot encode or decode the entire page unless there is an instruction from the MPU for each line or multiple lines. It happened.

The present invention has been made in view of the above problems, and an MPU can be generated without generating an interrupt request to the MPU at the time of completion of line encoding processing, decoding processing, DMA transfer processing, or the like.
It is an object of the present invention to provide an encoding / decoding device capable of executing the encoding / decoding processing of the entire page while minimizing the load on the.

Means for Solving the Problems In order to solve the above problems, the present invention provides an input unit for inputting image data or code data from an image memory, and an encoding process for the image data input from this input unit or the above A code decoding means for executing code data decoding processing, an operation mode of the code decoding means,
A table that stores processing information such as the number of lines to be processed, and a control means that activates the encoding / decoding means by using the processing information stored in this table are provided, and the processing information stored in the table is stored in the table. In part, the connection information for connecting with the processing information used for the subsequent processing after the processing based on this processing information is completed is set.

Further, the connection information may be repeatedly executed until the encoding process or the decoding process of the data amount corresponding to one page of image data or one page of code data is completed.

A register file for storing a part of the processing information stored in the table is provided in the encoding / decoding means, and an encoding process or a decoding process is executed based on the processing information stored in the register file. You may

Further, the table is composed of a plurality of tables in which different processing information is stored, and a part of the processing information stored in each table is connected to the processing information stored in the table used for the subsequent processing. Connection information for
You may make it perform the process by the process information stored in each table sequentially according to this connection information.

Further, input means for inputting image data or code data from the image memory, code decoding means for executing the encoding processing of the image data input from this input means or the decoding processing of the code data, and the code A first table storing first processing information such as an operation mode of encoding processing by the decoding means and the number of lines to be processed, an operation mode of decoding processing by the encoding / decoding means, and a line to be processed A second table in which the second processing information such as the number is stored, and control for activating the code decoding means with reference to the first and second processing information stored in the first and second tables. A part of the processing information stored in the first and second tables, the encoding processing by the first processing information and the decoding processing by the second processing information are alternately performed. Execution It is obtained so as to set the order of the connection information.

In the encoding / decoding system configured as described above, the encoding process or the decoding process is performed only by giving a start instruction from the microprocessor to the encoding / decoding means by the connection information set in the table. It is repeatedly executed by referring to the set processing information, and the load on the microprocessor is reduced.

When the connection information is repeatedly executed until the encoding process or the decoding process of the data amount of one page of the image data or the data amount corresponding to the code data of one page is completed, the process for one page is Until the end, the encoding process or the decoding process is repeated without issuing an interrupt request to the microprocessor.

Then, a part of the processing information stored in the table is stored in the register file of the encoding / decoding means, and the encoding processing or the decoding processing is executed based on this.

In addition, the table is configured by a plurality of tables having connection information for connecting with the processing information stored in the table used for the subsequent processing, and the processing information stored in the plurality of tables is processed according to the connection information. The processes based on the process information stored in the table are sequentially executed.

Furthermore, by the connection information set in two tables,
Only by giving an activation instruction from the microprocessor to the encoding / decoding means, the encoding process and the decoding process are alternately and repeatedly executed, and the load on the microprocessor is reduced.

Embodiments Embodiments of the present invention will be described below with reference to FIGS. 1 to 3 and 5 to 26.
It will be described with reference to the drawings. The first embodiment is shown in FIGS.
This will be described with reference to FIGS.

FIG. 1 (a) is an overall system configuration diagram of the first embodiment, and the same parts as those in FIG. 4 are designated by the same reference numerals. The present embodiment is an example of a facsimile system. To explain the data flow, the image data to be encoded is read by the image scanner 63, and the image memory 62 is read by the DMA transfer function of the encoding / decoding device 64.
Is input to Then, the data is encoded and decoded by the encoding / decoding device 64.
Is encoded inside and encoded according to an encoding algorithm such as MH encoding, MR encoding, MMR encoding, which is an international standard for facsimile encoding. The encoded data is MP
It is output on the U data bus and stored in memory such as RAM. The sequence of this encoding process is the link table 60.
Execute based on the information set in. Since the link table 60 is a data structure created on the memory,
It can be configured using a partial area of the image memory 62. The data flow at the time of decoding is RAM on the MPU bus.
The encoded data in the memory such as is restored to the image memory 62 by the encoding / decoding device 64, is sent to the printer 61, is hard-copied, and is reproduced as a restored image. FIG. 1 (b) shows an example of the operation timing of (a).

FIG. 2 shows a schematic configuration of a coding / decoding device 64 with a chain function. Coding / decoding device with chain function
Reference numeral 64 denotes an image data input / output FIFO1, which temporarily holds encoded data, encoded reference data, and restored image data.
A mode determination unit 2 including a coded data, a pixel for detecting a change in coded reference data, and a coding / decoding mode determination circuit, a latch circuit 3 for temporarily holding a coding mode detection result, and a run length. Code ROM4 in which code or MR code is written, P / S conversion circuit 5 for converting output data of code ROM4 to serial data, shift register 6 for aligning serial data to word size, processing timings of 4 to 6 above The timing control circuit 7, which temporarily holds the coded data aligned in word size by the processing of the timing control circuit 7, 7, the timing control circuit 9 which controls the input / output timing with respect to the encoded data output FIFOs 8, 8, the data to be encoded temporarily Timing control circuit 11, FIF for controlling input / output of encoded data input FIFO10, FIFO10
O11 output data latch circuit 12, timing control circuit 1
3, code ROM 14 for decompression, conversion circuit 15 for converting the output of the latch 12 for retrieval of the code ROM 14, latch circuit 16 for temporarily holding the decoded code, controlling the entire encoding and decoding A control unit 17 including a sequencer and an arithmetic circuit, a control unit 18 under the control of the control unit 17, a timing control circuit 19 for the image data input / output FIFO1, an image data interface unit 20 for controlling the input / output of image data to / from the memory, and data A register 21 for temporarily holding the interface unit 22 with the MPU, a register file 23 accessed by the MPU, an image data bus 24, an address bus 25, an image memory access control,
Control signals 26 and 27 for executing DMA transfer, encoded reference data 2
8, encoded data 29, input / output signals 30, 31 of the mode determination unit 2,
Control bus 32 consisting of input / output signals of control unit 17, control signal 33,
34, data bus 35, MPU reads / register file 23 /
Address signal 36, R / W for writing, data request, IRQ
Control signals 37 and 38 for MPU and MPU peripheral devices including requests and the like, and MPU data bus 39.

FIG. 3 shows the internal structure of the control unit 18 shown in FIG. The configuration is multiplexer 181, 182, register 183, 184, 185, arithmetic logic operation unit (ALU) 186, shifter 187, accumulator 188 for holding the operation result of ALU 186, comparator 190, output signal 191, of comparator 190, register file 192, stack pointer. 19
3, stack file 194, program counter 195, mapping ROM 196, multiplexer 197, microprogram ROM 19 which determines the processing address according to the contents of input signal 33
8, Pipeline register 199 that latches the output of ROM198,
It comprises a multiplexer 200 and a next address control circuit 201 which determines the next processing address.

FIG. 5 shows an example of the structure of the link table used in this embodiment. The configuration is table reference information 600 indicating the processing contents in this link table, which includes information such as encoding / decoding distinction, presence / absence of DMA transfer, and encoding / decoding algorithm 600, and encoding , The processing line address 601 indicating the start address of the decoding start line on the memory, the DMA line address 602 indicating the start address of the DMA transfer line, and the number of processing lines indicating the number of lines to be continuously processed in this table 603, a memory end address 604 that indicates the final address of the image memory that can be actually used, and a link address 605 that indicates to which table the processing should be continued after the processing of this table is completed.

6 to 16 are flowcharts showing an example of setting the link table and its processing. Other figures will be described when cited in the operation description below.

The operation of the encoding / decoding device with chain function configured as described above will be described below. First, the internal operation of the chain function encoding / decoding device 64 will be described.

The MPU sends various parameters for encoding and decoding, such as the number of pixels in one line and the start address of the link table, through the interface unit 22, registers 23, 21, and internal data bus 35 to the register file 192 (in the control unit 18). (Fig. 3). Also, the data is output to 24 via the registers 23 and 21, and the link table 60 is stored in the image memory 62.
Create After that, set the bit of register 23,
An operation mode instruction is given to the encoding / decoding device 64 (hereinafter referred to as CODEC64) to start the processing. When the CODEC 64 is started from the MPU, it reads in-table setting information from the link table start address LNKT already set by the MPU in the register file 192 (FIG. 3) inside the control unit 18 into the register file 192. The data in the table outputs its memory address to the address bus 25 (Fig. 2),
The data in the image memory 62 is read onto the data bus 24 by the bus control signals 26 and 27. This data is stored in register 21,
It is written to a predetermined address in the register file 192 through the internal data bus 35. This series of processing is performed by the micro program sequencers 193-201 (third program
Figure) controlled by. CODEC64 fetches the necessary information inside, and then the table reference information 600 (Fig. 5).
Then, check what kind of processing is instructed. In this embodiment, the presence / absence of DMA transfer, the distinction between encoding and decoding processes, the algorithm thereof, etc. can be selected. In the following description, it is assumed that DMA transfer and encoding are designated. The “table type selection” in the table reference information 600 will be described later. The DMA transfer at the time of encoding is transferred from the scanner 63 (FIG. 1) to the image memory 62 (FIG. 1). The start address of DMA transfer is "DMA line address STRC" 60 in the link table.
This is the address set as 2. Therefore, the number of processing lines (NLINE) 603 from the address STRC by the DMA transfer processing
The data from the scanner 63 is transferred to the image memory 62 by the minute. The DMA transfer address is output on the address bus 25. Read / write, DMA transfer request from scanner 63,
Bus control signals such as transfer confirmation are 26 and 27.

When the DMA transfer for NLINE 603 is completed, the encoding process is started. The start address of the encoded data is in the link table
This is the “processing line address STRA” set in 601. The number of lines to be encoded is NLINE603. The coding algorithm is specified by the table reference information 600. The encoded data is sequentially read from the memory address STRA onto the data bus 24 and input to the image data input / output FIFO1. In the two-dimensional coding (MR), the address of the coded reference data is calculated based on STRA, and similarly input to the image data input / output FIFO1. The upper side of FIFO1 shows the reference data FIFO, and the lower side shows the encoded data FIFO. These data are sent to the coding mode determination unit 2 through the data lines 28 and 29. In the MR coding, coding is performed by defining the change pixels shown in FIG. 17, detecting the pass mode, the vertical mode, and the horizontal mode, and assigning the codes shown in FIG. 19 to them.

FIG. 17 is an explanatory diagram for defining the change pixel and the mode (a)
Shows a change pixel, (b) shows a pass mode, and (c) shows a vertical mode and a horizontal mode.

 The meanings of the symbols here are as follows.

Reference or origin change pixel on a ₀ code line At the beginning of the code line, a ₀ is placed on the virtual white change pixel located just before the first pixel of the line. During the coding of the coding line, the position of a ₀ is defined by the previous coding mode a ₁ The first change pixel to the right of a ₀ on the coding line a _{2 the} right of a ₁ on the coding line First change pixel of b ₁ a ₀ on the reference line on the right of b ₁ a ₀ and opposite in color to a ₀ b ₂ first change pixel on the right of b ₁ on the reference line FIG. 19 shows a two-dimensional code (MR code) table, FIG. 17, FIG.
The contents of the figure are
Internationally standardized by CCITT Recommendation T.4.

In MH coding, the continuous length (run) of white pixels and black pixels is coded based on a code table based on Huffman coding. Although a specific code table is omitted here, the symbol M (A
B) is the meaning of the MH code for runs A to B. Figure 18 is a flow chart for MR coding, and Figure 20 is MMR.
It is a flowchart of the encoding.

The mode determination unit 2 detects the changed pixels shown in FIG. 17, determines the encoding mode from the positional relationship, and outputs a predetermined intermediate code to the register 3 for each mode. The code ROM 4 is read out based on this intermediate code, P / S conversion 5 and packing processing 6 to the word size are performed and output to the encoded data output FIFO 8. Code ROM
The code shown in FIG. 19 and the MH code are written in 4. The MR coding process shown in FIG. 18 is executed under the control of the blocks 2 to 7 and the control unit 17. Similar processing is performed for the MMR encoding shown in FIG. The data of the encoded data output FIFO 8 is the timing control circuit 9
Is written in the register file 23 by and output to the MPU side. By repeating such an operation, the encoding processing of the image data for NLINE 603 is executed. When the encoding process ends, the process that refers to one table ends.

The link address shown in FIG. 5 605 indicates the head address of the table to be referred to next. When the processing of one table is completed, the processing moves to the table of the address indicated by the link address and the processing is continued. If the link address is set so as to indicate the top address of the table, one table is repeatedly referred to and the processing for the entire page is performed.

 Next, the operation inside the CODEC 64 at the time of decoding will be described.

It is assumed that the table reference information 600 specifies decoding and DMA transfer. In this case, the decoding process is first executed, and then the DMA transfer process is performed. The data to be restored is input to the encoded data input FIFO 10 via the MPU data bus 39 and the register 23. The data input to 10 is the latch
12 is entered and the code ROM 14 is controlled by the timing control circuit 13.
Is converted by the conversion circuit 15 for searching
It is output from the ROM 14 to the mode determination unit 2 as an intermediate code. The intermediate code passes through the latch circuit 16 and the mode determination unit 2
Is input to and decryption processing is performed. The restored data is stored in the memory table ST according to the "processing line address STRA" 601 set in the link table 60 (Fig. 5).
Sequentially stored from RA. As with the encoding, the decoding process is performed using the “number of processing lines NLINE” 60 set in the link table.
Run continuously for 3 minutes. After the completion of decoding NLINE, DMA transfer for NLINE is performed from “DMA line address STRC” 602.
If the DMA line address and the processing line address are the same, the restored NLINE data will be sent from the memory to the I / O of the printer and reproduced as a hard copy or soft copy. When the DMA transfer for NLINE is completed, the processing corresponding to one link table is completed. Link address 60
Since the address of the link table to be referred to next is set in 5, the following processing is performed according to the link table. In this way, the entire page is decoded by linking the link tables according to the link address.

Next, a connection example of the link table will be described. Sixth
The figure is an example of the encoding operation described above. As shown in FIG. 6 (c), the memory address is determined on a line-by-line basis. Sixth
As shown in FIG. 7A, the processing line address STRA and the DMA line address STRC are set to the address LINE0. The number of processing lines NLINE is 2. The memory end address MENDA 604 indicates the final address of the memory area that can be actually used. In this example, the address LINE
3 is defined as the final address of the memory. FIG. 6 (b)
"MR encoding" and "with DMA" can be specified by the bit settings shown in. Further, depending on the table type, it is possible to select whether or not to refer to the memory end address when calculating the line head address to be processed next after the completion of one line processing. In this example, the table type is set to "1" and the memory end address is referred to. By doing so, the area from LINE0 to LINE3 (hatched portion) of the memory area shown in FIG. 6C is repeatedly used. When the encoding / decoding apparatus is activated by the above settings, the processing is performed according to the flowchart shown in FIG.

In steps 700 to 703 of FIG. 7, the setting values of the link table are loaded into the register file 192. As described above, other parameters are already set in the register file 192 by the MPU. Input of these data is performed by inputting the data (for example, the data of the image memory 62) on the data bus 24 (FIG. 2).
STRA, etc.) and outputs it to the internal bus 35 through the register 21. This is done by inputting this data to a predetermined register (eg REG2).
These controls are executed by the sequencers (193 to 201). In step 704, it is judged whether or not there is a DMA transfer set in the table reference information bit 1. If there is a DMA transfer instruction, it is executed in step 705. Then step 706
˜708 determines the encoding algorithm set in the table reference information bits 3 and 4. Steps 712 to 714 are executed according to the algorithm. In step 709, it is determined whether the encoding of the entire page is completed. In step 711, the start address of the link table is updated. As shown in Fig. 6, the link address LNKA is the address LNKT initially set by the MPU.
The contents of the register LNKT are not changed by the step 711 because they point to. Step 710 is an interrupt for notifying the MPU of the end after the encoding end condition for one page is satisfied. The interrupt to the MPU only occurs in step 710. FIG. 15 is an explanatory diagram of step 713. The MR encoding processing of step 713 is composed of MR encoding 7130 and data input processing 7131, as shown in FIG. Step 7130 is the mode determination as described above.
2. Execution of the flow chart shown in FIG. 18 centering on the control unit 17 (FIG. 2). FIG. 16 shows the contents of step 7131. In step 71310, the start addresses STRA and STRC set in the link table are set in registers inside the image bus interface unit 20. This is done as follows. The processing start address is set in the register file 192 (third part in step 701 shown in FIG. 11).
(Fig.) Input to REG2 inside. As shown in FIG. 3, STRA, which is the contents of REG2, is read out from the register 192 onto the internal data bus 35, and the multiplexer 184, ALU18
6, passing through the shifter 187, input to the accumulator 188, output on the internal data bus 202, and input to the image bus interface unit 20. In step 71311, it is determined whether or not there is a space in the image data input / output FIFO1, and if there is a space, the input processing from the memory is performed in step 71312.
In step 71313, it is judged whether or not the input of the data for one line is completed. This is because the output of ACCA188 in FIG. 3 indicates the address of the memory, so that the output 191 of the comparator 190 can be monitored by the sequencer (193 to 201) by setting the final address of the line in REGC189. Can be found by Step 71314 is processing to set the next processing address to LINE1 after the processing of the data contained in FIG. 6 LINE0 is completed. In steps 71315 to 71317, the processing result of step 71314 is compared with the memory end address MENDA set in the link table, and if it exceeds MENDA, the processing line address is set to STRA set in the table. . In the example of FIG. 6, after the processing of the data in the address LINE2 is completed, the next processing line address becomes LINE0.
As described above, the data flow from the I / O to the memory and from the memory to the main encoding / decoding device 64 is as shown in FIG. 13 (a). The fact that LINE0 is written in the sequence chart in FIG. 13 (a) means that this data is input or output from the address LINE0 in FIG. 6 (c).

FIG. 8 shows a configuration example of a link table when decoding and DMA transfer are designated by the table reference information. FIG. 9 shows a flowchart.
The difference from FIG. 7 is that the steps 807 and 808 are the decoding process 8
This is the point executed after 13 to 815. Description of each process is omitted. The data flow is shown in FIG. 13 (b).

Figure 10 prepares two tables, one for encoding,
On the other hand, it shows an example of using the link table when the decoding is set and the encoding and the decoding are alternately executed for each NLINE. In this example, decoding is MH and encoding is MR, as shown in FIG. 10 (b). Further, the link address of Table 1 indicates the start address of Table 2, and the link address of Table 2 indicates the start address of Table 1. FIG. 11 shows an example of processing with the table configuration of FIG. Similar to FIG. 7, steps 900 to 903 are the input processing of the link table setting values. Step
At 904, it is determined whether the table reference information bit 2 indicates encoding or decoding. Step 905 is
The flag is checked to determine whether or not the encoding process for the entire page has already been completed. Step 906 is DMA
Determine whether there is a transfer. Step 907 is a DMA transfer process from the I / O to the memory. According to steps 908 to 910, each encoding process is executed in steps 916 to 918. In step 911, it is determined whether or not the encoding processing for the entire page has been completed by the processing in steps 916 to 918. When the encoding process for one page is completed, the encoding end flag is set in step 912. In step 913, it is determined whether or not the entire processing of encoding and decoding is completed. If all processing is not completed, the link table top address is updated in step 915. When all the processes are completed, an interrupt is generated in step 914, the MPU is notified, and the process is completed. Steps 919 to 926 are the decryption processing flow. In the configuration example of the link table in FIG. 10, the first table indicates MH decoding, and NLINE is set to 2, so in step 929, MH decoding for two lines is executed. Then, in step 915, the link address is changed to the head address LNKT1 of the second table. After that, MR encoding is executed according to the second table. Decoding, until the whole process is completed like this,
The encoding is performed alternately for each NLINE. The interrupt to the MPU is only issued in step 914 after the completion of all the processes, and there is no interrupt to the MPU before the completion of all the processes or the activation waiting state from the MPU.

FIG. 14 shows a data flow corresponding to FIGS. 10 to 12.

Next, a second embodiment will be described with reference to the drawings used in the first embodiment and FIGS. 21 to 26.

The overall system configuration is the same. FIG. 21 differs from FIG. 3 only in the register file 192.

FIG. 22 shows the structure of the register file 192. The register file 192 is roughly divided into a parameter area for setting parameters and a link table area for creating a link table. Figure 22 shows some parameters and the structure of the link table.
C-STRA1921 and D-STRA1922 are head addresses of encoding and decoding processing lines, respectively. C-PWDR and D-PWDR are the number of pixels in one line of the encoding and decoding lines, respectively. C-LNGT
H and D-LNGTH are the numbers of coding and decoding lines for continuous processing, respectively. The start address of the link table is set in LNKT1927. The link table is 1928-1932. TBLR
EF indicates the processing content in this link table. FIG. 23 is a configuration example of TBLREF. STRA1929 is the start address of the image processed by this link table, and NLINE1930 is the number of processing lines in this table. MENDA1931 is the final address of the image memory area. LNKA1932 is a link address for instructing which table to move to after the processing of the link table is completed. A series of flow of this encoding process is executed based on the information set in the link tables 1928 to 1932. Since the link table is a data structure created inside the memory, it can be configured by using a partial area of the register file 192. The data flow at the time of decoding is that the encoded data in the memory such as RAM on the MPU bus is encoded and decoded by the encoding / decoding device 6
4 is restored to the image memory 62 by the printer 6
It is sent to 1 and made into a hard copy or soft copy and played back as a restored image.

The operation of the chain function encoding / decoding device internal 64 in the above data flow will be described.

The MPU sends various parameters for encoding / decoding, such as the number of pixels in one line and the start address of the link table, through the interface unit 22, registers 23, 21 internal data bus 35 to the register file 192 (first twenty one
(Fig.) Also, the data is output to 24 through the registers 23 and 21, and the link table 60 is created in the image memory 62.

After that, the bits of the register 23 are set, the operation mode is instructed to the encoding / decoding device 64, and the processing is started.

When the process starts, the process is performed by referring to the link table address LNKT1927. It is assumed that the link table shown on the left side of FIG. 24 is created in the link table area.
As shown in this figure, there are two link tables, which are created at addresses TB1 and TB2, respectively. It is assumed that LNKT indicates the first table address TB1 and the table reference information (TBLREF) of the first table is set to MH decoding.
The link address LNKA in the first table indicates the address TB2 in the second table, and MR in the TBLREF in the second table.
It is assumed that encoding is set. Further, the link address LNKA of the second table indicates the first table address TB1.

When activated from the MPU, it operates according to the flow shown in Figs. First, the start address STRA set in the table is loaded into C-STRA1921 and D-STRA1922 (steps 100 and 101). In this step, since the first table shows the decoding mode, the STRA of the first table is
Is loaded into D-STRA1922, and similarly, STRA in the table of FIG. 2 is loaded into C-STRA1921. In step 102, the 0th bit of TBLREF in the first table is checked to determine whether encoding or decoding is performed. Since the first table is set for decryption, the process moves to step 117 in FIG.
In step 117, it is determined whether or not all the decoding processing has been completed. In this embodiment, as all decoding processing conditions, 1) the restoration of the number of lines set in the D-LNGTH1926 in advance is completed, 2) the signal (RTC code) indicating the end of the coded data is detected, and 3) the error that cannot be restored. Of occurrence. If the flag is set in step 117, the decoding process is not performed. In steps 118 to 120, the first and second bits of TBLREF are checked to determine the MH, MR, MMR etc. coding mode. Since it is assumed that the MH has been set in the first table, the process proceeds to step 123 and the MH decoding process is performed.

In the MH decoding process, the data to be restored is input to the encoded data input FIFO 10 via the MPU data bus 39 and the register 23. The data input to 10 enters the latch 12 and is converted by the conversion circuit 15 for searching the encoding ROM 14 under the control of the timing control circuit 13, and is output from the decoding code ROM 14 to the mode determination unit 2 as an intermediate code. The intermediate code is input to the mode determination unit 2 via the latch circuit 16 and decoded. The restored data is sequentially stored from the memory address STRA according to the "processing line address STRA" set in the link table. Decryption process is the number of processing lines NLINE set in the link table.
Run continuously for minutes. Since NLINE is 2 in this embodiment, data for 2 lines is restored from the address LINE0 indicated by STRA. In step 124, the restored memory address D-STRA is updated for the next decoding process.
In this process, D-STRA shows LINE2 in FIG. step 1
In 25, replace the contents of D-LNGTH1926 with the value obtained by subtracting NLINE from it. As described above, the total number of lines to be restored is preset in the D-LNGTH by the MPU. In step 126, it is judged whether or not the result of step 125 is 0. If this is 0, the decoding end flag is set in step 127. In step 114, it is judged whether or not all the encoding and decoding processes have been completed. Step
In 116, link table address LNKT is set to link address L
Replace with NKA. By this processing, TB2 which is the content of the link address of the first table is set in LNKT.

After step 116, step 102 is executed again. In step 102, the 0th bit of TBLREF in the second table is determined. Since MR encoding is set in the second table, the process proceeds to step 103. In step 103, it is determined whether or not all the encoding processing has been completed. The total number of encoded lines is set in advance to C-LNGTH1925 by the MPU. The first and second bits of TBLREF are checked in steps 104 to 106. In the second table, MR encoding step 108 is performed.

In step 110, the start address of the image data to be encoded in the encoding process is updated. In this example, NLINE
Since 2 is 2, LINE2 in Fig. 24 becomes the content of C-STRA. In step 111, the content of C-LNGTH is replaced with the original value minus NLINE. Step 112 determines whether the value of step 111 is 0. If this value is 0, the encoding end flag is set in step 113. In step 114, it is determined whether both the encoding end flag and the decoding end flag are set. When all the processes are completed, the IRQ is issued to the MPU in step 115 and the process is completed.

If all the processing is not completed, the value of the link table address LNKT is replaced with the content TB1 of the link address LNKA of the second table in step 116. Then, the above-mentioned decryption processing is executed. Thus, in this embodiment, the D-LNGT
2 lines until the value of H1926, C-LNGTH1925 becomes 0 (NLIN
Decoding and encoding are repeated for each E) and MH for one page
The process of encoding the decoded data with MR is executed.

The above flow chart and each operation are executed by the microprogram sequencer and ALU shown in FIG.

EFFECTS OF THE INVENTION As is clear from the above description, the present invention sets information and operation modes required for encoding, decoding, and DMA transfer in a link table, and makes one table correspond to one processing unit. By making it possible to indicate the processing order of the entire page by the connection information connecting the link tables, it is not necessary to interrupt the MPU every time one processing unit is completed, so the load on the MPU is reduced, and By eliminating the state of waiting for instructions from the MPU, it is possible to speed up processing, and by connecting various tables, it is also possible to concatenate and process data distributed in memory. I have.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a schematic configuration diagram of an encoding / decoding device with a chain function, FIG. 3 is a detailed configuration diagram of a control unit in FIG. 2, FIG. 4 is a system configuration diagram using a conventional encoding / decoding device, and FIG. FIG. 6 is a diagram showing a configuration example of a link table, FIG. 6 is a diagram showing an example of a link table and an image memory at the time of encoding, and FIG.
FIG. 8 is a flowchart showing an example of a link table and an image memory at the time of decoding, and FIG.
Flowchart corresponding to the figure, FIG. 10 is a diagram showing an example of a link table and an image memory when performing decoding and encoding alternately, FIG. 11, FIG. 12 is a flowchart corresponding to FIG. FIG. 13 is a diagram showing a data flow corresponding to FIGS. 6 and 8, FIG. 14 is a diagram showing a data flow corresponding to FIG. 10, FIGS. 15 and 16 are processing flow diagrams,
Fig. 17 is an explanatory diagram that defines the changing pixels and modes, and Fig. 18 is
Flow diagram showing an example of implementation of MR encoding, FIG. 19 is a diagram showing a two-dimensional code (MR code), FIG. 20 is a flow diagram showing an example of implementation of MMR encoding, FIG. 21 is the control of FIG. FIG. 22 is a diagram showing the memory contents of the control unit shown in FIG. 21, FIG. 23 is a diagram showing a configuration example of table reference information, and FIG. 24 is a configuration example of a link table. FIG. 25, FIG. 25, and FIG. 26 are flowcharts corresponding to FIG. 60 ... Link table, 61 ... Printer, 62 ... Image memory,
63 ... Scanner, 64 ... Coding / decoding device with chain function, MP
U: Microprocessor unit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hideyuki Shirai, Inventor Hideyuki Shimeguro 2-3-8, Meguro-ku, Tokyo Matsushita Densen Co., Ltd. (72) Inventor Toshiko Nishida 2-3-8 Shimeguro, Meguro-ku, Tokyo Matsushita Dentsu Co., Ltd. (56) Reference JP-A-57-106976 (JP, A)

Claims (5)

[Claims] 1. Input means for inputting image data or coded data from an image memory, and code decoding means for executing a coding process of the image data input from this inputting device or a decoding process of the coded data. A table storing processing information such as the operation mode of the encoding / decoding means and the number of lines to be processed, and a control means for activating the encoding / decoding means using the processing information stored in the table, Coding, characterized in that a part of the processing information stored in the table is set with connection information for connecting to processing information used for subsequent processing after processing by this processing information is completed. -Decryption system. 2. The connection information is information to be repeatedly executed until an encoding process or a decoding process of one page of image data or a data amount corresponding to one page of code data is completed. The encoding / decoding system according to claim 1. 3. A register file for storing a part of the processing information stored in the table is provided in the encoding / decoding means, and an encoding process or a decoding process is performed based on the processing information stored in the register file. The encoding / decoding system according to claim 1 or 2, which is executed. 4. The table is composed of a plurality of tables in which processing information different from each other is stored, and a part of the processing information stored in each table includes processing information stored in a table used for subsequent processing. 2. The encoding / decoding system according to claim 1, further comprising: connection information for connecting with, and sequentially executing processing according to the processing information stored in each table according to the connection information. 5. Input means for inputting image data or coded data from an image memory, and code decoding means for executing a coding process of the image data input from this inputting device or a decoding process of the code data. A first table storing first processing information such as an operation mode of encoding processing by this encoding / decoding means, the number of lines to be processed, and an operation mode and processing of decoding processing by the encoding / decoding means. A second table in which the second processing information such as the number of lines to be stored is stored, and the encoding / decoding means is activated using the first and second processing information stored in the first and second tables. And a control unit for performing the encoding process according to the first process information and the decoding process according to the second process information in a part of the process information stored in the first and second tables. Alternating fruit Encoding and decoding system, characterized in that the connection information for is set.