JPH0828975B2 - Power supply circuit for telephone - Google Patents

Description

TECHNICAL FIELD The present invention relates to a low loss rectification circuit with a small voltage drop used in a telephone or the like.

[Conventional technology]

In telephones, a full-wave rectifier circuit is inserted on the line terminal side when the polarity of the loop current leading to the internal circuit is constant, regardless of the line voltage polarity of the telephone line. This type of full-wave rectifier circuit is required in various telephones whose internal circuit is composed of semiconductor elements, and a full-wave rectifier circuit in which four sides of a fritted circuit are constituted by ordinary diodes is generally used.

[Problems to be solved by the invention]

However, when a full-wave rectifier circuit using a diode is used, the forward voltage of this is 0.5 to 0.6 V per element,
If it is a bridge circuit, two elements will always be in series and the voltage drop of the rectifier circuit will be 1.0 to 1.2V, so this will not cause any problems in standard use, but it will be connected in parallel with the telephone with a low internal DC resistance value. , If the off-hook is performed at the same time, the line voltage may decrease depending on the relationship with the resistance value of the telephone line, and the voltage may be close to the operable voltage of the majority of the circuits configured by semiconductor elements. At this time, the voltage drop of the rectifier circuit cannot be ignored, and depending on the conditions, this voltage drop causes a problem that the internal circuit cannot operate.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constituted by the following means.

That is, in a full-wave rectifier circuit in which four sides of a bridge circuit are composed of directional elements, a current flows between the drain and source between either the positive or negative terminal of the DC output terminal and the first AC input terminal. Direction and a bias is applied from the second AC input terminal to the gate of the first enhancement type transistor, and between the drain and source of current between the one terminal and the second AC input terminal. A second enhancement type transistor which is inserted as a flow direction and to which a bias is applied to the gate from the first AC input terminal is provided as at least two sides of the bridge circuit, and the first and second enhancement type transistors are provided. The gate is provided with a voltage limiting element.

[Work]

Therefore, the first and second enhancement type transistors are turned on when the AC input terminal to which they are connected and the AC input terminal on the opposite side are in a polarity such that they are forward biased, and these transistors are alternately repeated. However, a rectifier circuit with a low voltage drop is obtained because the drain-source acts as a diode when turned on, and the on resistance value at this time is extremely low. Further, the voltage control element provided at the gates of the first and second enhancement type transistors can surely operate up to the drain / source reverse withstand voltage of the transistor even with respect to the surge input voltage.

[Examples] Details of the present invention will be described below with reference to the drawings illustrating examples.

This figure is a block diagram of a subscriber's telephone set, and a fax switch HS, a full-wave rectifier circuit (hereinafter, REC) 1 and a pulse are sent to the line terminals L ₁ and L ₂ to which the telephone line from the exchange is connected. A call circuit (hereinafter, TKC) 3 including a handset is connected through a circuit (hereinafter, DPS) 2, and a dial circuit (hereinafter, DIC) is connected in parallel with TKC3 via a constant current circuit (hereinafter, CIC) 4. 5 is connected, DIC
The output of the dial key (hereinafter, DK) 6 is given to 5.

In addition, REC1 is a directional element and V (Vertical groov
e) Enhancement transistors such as MOS type (hereinafter,
TR) Q _{1 to} Q ₄ are used to configure the four sides of the bridge circuit. In this example, TR · Q _{1 to} Q ₄ are N channel TRs.
In addition, the first TR · Q ₁ drain · between the negative electrode terminal 12 of the DC output terminals 11, 12 and the first AC input terminal 13
Insert the current between the sources as a direction in which the current flows from the negative terminal 12, and also to the gate of TR / Q ₁ from the second AC input terminal 14 via the resistor R ₁ and the voltage limiting circuit of the constant voltage diode ZD ₁ to the bias voltage. one and summer and used to apply a is inserted as the same direction as described above to between the second TR-Q ₂ of the drain-source of the negative terminal 12 and the AC input terminal 14, the TR-Q ₂ A bias voltage is applied to the gate from the AC input terminal 13 via the resistor R ₂ and the voltage limiting circuit of the constant voltage diode ZD ₂ , and TR ・
The Q _1, Q ₂ constitute two sides of Buritsuji circuit.

On the other hand, between the positive terminal 11 and the AC input terminals 13 and 14, the TR-Q ₃ and Q ₄ drain-source terminals are connected to the positive terminal 11 respectively.
Together are inserted into each individual as the direction of current leads to, TR · Q _3, the gate of Q ₄ are commonly connected to the source of each, they are turned off by the zero bias,
The equivalent parasitic diode d formed between the drain and the source acts as a diode.

Therefore, when the AC input terminal 13 is positive, TR ・ Q ₃
With leading current from the positive terminal 11 through the negative terminal 12, via a resistor R _2, and the voltage is limited by Zener diode ZD _2, a forward bias is applied to the gate of the TR · Q ₂ When TR · Q ₂ is turned on, a current flows from the source to the drain, and is caused to flow back to the AC input terminal 14, which has a negative polarity at this time.

If the AC input terminal 14 has a positive polarity and the same terminal 13 has a negative polarity, the voltage is limited to the gate of TR / Q ₁ via the resistor R ₁ and is regulated by the constant voltage diode ZD ₁ to forward bias. Is applied, TR ・ Q ₁ turns on and current flows from the source to the drain, and TR ・ Q ₄ acts in the same way as TR ・ Q ₃ , so that current flows from the positive terminal 11 to the negative terminal 12. Therefore, the loop current with a constant polarity is applied to the DPS2 regardless of the line voltage polarity of the telephone line connected to the line terminals L ₁ and L ₂ .
~ It connects to the internal circuit of DIC5.

Therefore, if you go off-hook, you will get the Hooks Switch HS.
When REC is turned on, a loop current with a constant polarity is passed to TKC3 by REC1 to close the DC loop, and a part of the loop current via CIC4 activates DIC5 to operate DK6. The DPS2 is controlled accordingly, and a dial pulse is sent by turning the switching element off and on using TR etc., and the exchange responds to this to make a switching connection. If the other side responds, the TKC3 Handsets allow you to talk freely.

However, due to the above connections, TR ・ Q ₃ and Q ₄ used for REC1 have a forward saturation voltage as a diode as low as about 0.4V even at a small current, while TR ・ Q ₁ and Q ₂ are turned on. The resistance value becomes about 5Ω when forward bias is applied, and the forward saturation voltage as a diode becomes about 0.1V in the flowing current of about 20mA, so when TR · Q ₃ and Q ₂ are connected in series, and When TR ・ Q ₄ and Q ₁ are connected in series, the voltage drop as REC ₁ is about
It is extremely low at 0.5V.

Therefore, when it is connected in parallel with a 601 type telephone with an internal DC resistance of about 100 Ω, and is turned off at the same time,
Even if the line voltage drops due to the relationship with the resistance value of the telephone line, REC1
The voltage drop of is decreased by about 0.7V, and the applied voltage of the internal circuit rises according to this decrease, so the internal circuit will operate sufficiently even when semiconductor elements and integrated circuits are used for the internal circuit. In particular, the operating state of the transmitter amplifier and the receiver amplifier in TCK3 is maintained, and the call can be secured.

However, if you use P channel enhancement type as TR / Q ₃ and Q ₄ , and connect in the same way as TR / Q ₁ and Q ₂ ,
Q _3, a forward voltage of about 0.1V next to Q _4, can be reduced to about 0.2V voltage drop REC1.

That is, as shown in FIG. 2 (A), the relationship between the gate-source voltage V _GS and the drain current I _D of the N channel and the P channel is shown in FIG. 2 (B).
The flow of I _D starts according to V _GS , and I _D increases, and the drain-source exhibits a diode action, whereas in the P channel, it depends on the negative −V _GS. Since I _D changes in the same way and the diode function is assumed to exist between the drain and source, TR channel, Q ₃ and Q ₄ should be P channels, and should be turned on based on the characteristics of (B). It suffices to apply a bias to.

3 and ₄ are replaced by TR · Q ₃ and Q ₄ in FIG.
FIG. 4 is a circuit diagram showing REC1 when TR · Q ₅ and Q _{6 of} P channel are used. In FIG. 3, line voltage is TR · Q ₁ , Q ₂ ,
Q _5, the maximum gate-to-source voltage of Q ₆ It is a condition that does not exceed TR.Q ₁ , Q ₂ gates are directly connected to AC input terminals 14, 13, while TR · Q ₅ , Q ₆
Between the drain and source of the positive terminal 11 and AC input terminal 13,
Insert each of the currents to and from 14 as the direction of current flow, and the gate of TRQ _{5 to} the AC input terminal 14
・ The gates of Q ₆ are connected to the same terminal 13 individually.

Therefore, when the AC input terminal 13 has a positive polarity and the AC terminal 14 has a negative polarity, a negative forward bias is applied to the TR / Q ₅ gate to turn it on, and also to the TR / Q ₂ gate. Is turned on by applying a positive-direction forward bias, current flows from the AC input terminal 13 to the positive terminal 11, and further from the negative terminal 12 to the AC input terminal 14, and the AC input terminal 14 is positive and the same terminal 13 Is negative, TR ・ Q ₆ and Q ₁ are also turned on, and the AC input terminal 14 goes to the positive terminal 11 and the negative terminal
Current flows from 12 to the AC input terminal 13, and full-wave rectification can be performed in the same way as in Fig. ₁ , and TR ・ Q ₁ , Q ₂ , Q ₅ ,
The voltage drops of Q ₆ are about 0.1V each, and the total voltage drop can be about 0.2V.

Figure 4 is to limit the voltage applied to the gate as in the first figure, each resistor against _{TR · Q 5, Q 6 R} 3, R 4 and constant voltage diodes ZD _3, ZD ₄ 1 is the same as that of FIG. 1 and FIG.

However, the constant voltage diodes ZD ₃ and ZD ₄ are connected with the gate side serving as the anode in order to limit the negative forward bias.

The Zener voltage of the constant voltage diodes ZD _{1 to} ZD ₄ is
TR ・ Q ₁ , Q ₂ , Q ₅ , Q ₆ is fully saturated V
_It should be set according to _GS .

At present, it is difficult to obtain an enhancement type TR of P channel, and the one shown in FIG. 1 is suitable for practical use.

However, TR · Q ₃ and Q ₄ in FIG. 1 may be general diodes, and TR · Q ₁ and Q ₂ in FIGS. ₃ and ₄ may be diodes as well.

In addition to subscriber telephones, it can be applied to various telephones such as public telephones that require diode bridges, and can be used in various electronic devices that require a low-loss rectifier circuit with a small voltage drop. Various modifications such as the above are possible.

〔The invention's effect〕

As is clear from the above description, according to the present invention, a low-loss rectifier circuit is realized, and a sufficient output voltage can be obtained even if the input voltage is reduced with a small voltage drop in the rectifier circuit.
The operation of the circuit connected to the output side of the rectifier circuit can be ensured. Furthermore, since the drain-source reverse withstand voltage of the enhancement type transistor can be operated reliably against surge input voltage, the transistor element can be protected from reverse surge voltage, which is a remarkable effect in various electronic devices. Present.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, FIG. 1 is a block diagram of a telephone, FIG. 2 is a view showing characteristics of an enhancement type transistor, and FIGS. 3 and 4 are full-wave rectification circuits showing other embodiments. It is a circuit diagram of. 1 …… REC (Full wave rectifier circuit), 11,12 …… DC output terminal,
13,14 ...... AC input terminals, Q ₁ ~Q ₆ ...... TR (transistor), R ₁ ~R ₄ ...... resistors, ZD ₁ ~ZD ₄ ...... constant voltage diode.

Claims (2)

[Claims] 1. A first terminal (13) and a second terminal (14) are connected to a telephone line, and a third terminal (11) and a fourth terminal (12).
Is connected to the telephone circuit (TEL) and the telephone circuit (TE
A power supply circuit (REC) for a telephone, which supplies a DC voltage of constant polarity to L), wherein the power supply circuit (REC) for the telephone has a first terminal (13) and a second terminal (13).
Between the first terminal (13) and the second terminal (14), and the first arm (A1) connected between the terminals (14) and (4) with the midpoint connected to the fourth terminal (12). Connected, the middle point is the third terminal (1
1) and a second arm (A2) connected to the first arm (A1), and the first arm (A1) is a first arm composed of N channels.
Enhancement transistor (Q1) and a second enhancement transistor (Q2) composed of N-channel, the drain of the first enhancement transistor (Q1) is connected to the first terminal (13), The gate is connected to the second terminal (1
4), the first voltage limiting element (ZD1) having the cathode connected to the gate side is connected between the gate and the source,
The second enhancement transistor (Q2) has a drain connected to the second terminal (14), a gate connected to the first terminal (13) via a second resistor (R2), and a gate-source. A second voltage limiting element (ZD2) having a cathode connected to the gate side is connected between the sources, and sources of the first enhancement transistor (Q1) and the second enhancement transistor are commonly connected to form a first arm. The second arm (A2) forms the midpoint of (A1) and the third arm consists of N channels.
Enhancement transistor (Q3) and a fourth enhancement transistor (Q4) composed of N-channels. The third enhancement transistor (Q3) has a source and a gate at the first terminal (1).
3), the fourth enhancement transistor (Q4) has a source and a gate connected to the second terminal (14), and a third enhancement transistor (Q4).
3) and the drain of the 4th enhancement transistor (Q4) are connected together to form the midpoint of the 2nd arm (A2). 2. A first terminal (13) and a second terminal (14) are connected to a telephone line, and a third terminal (11) and a fourth terminal (12).
Is connected to the telephone circuit (TEL) and the telephone circuit (TE
A power supply circuit (REC) for a telephone, which supplies a DC voltage of constant polarity to L), wherein the power supply circuit (REC) for the telephone has a first terminal (13) and a second terminal (13).
Between the first terminal (13) and the second terminal (14), and the first arm (A1) connected between the terminals (14) and (4) with the midpoint connected to the fourth terminal (12). Connected, the middle point is the third terminal (1
1) and a second arm (A2) connected to the first arm (A1), and the first arm (A1) is a first arm composed of N channels.
Enhancement transistor (Q1) and a second enhancement transistor (Q2) composed of N-channel, the drain of the first enhancement transistor (Q1) is connected to the first terminal (13), The gate is connected to the second terminal (1
4), the first voltage limiting element (ZD1) having the cathode connected to the gate side is connected between the gate and the source,
The second enhancement transistor (Q2) has a drain connected to the second terminal (14), a gate connected to the first terminal (13) via a second resistor (R2), and a gate-source. A second voltage limiting element (ZD2) having a cathode connected to the gate side is connected between the sources, and sources of the first enhancement transistor (Q1) and the second enhancement transistor (Q2) are commonly connected to each other. The second arm (A2) forms the middle point of the first arm (A1), and the second arm (A2) forms the third point composed of the P channel.
Enhancement transistor (Q5) and a fourth enhancement transistor (Q6) composed of a P-channel, the third enhancement transistor (Q5) has a drain connected to the first terminal (13), The gate has the second terminal (14) through the third resistor (R3)
The drain of the fourth enhancement transistor (Q6) is connected to the second terminal (14) and the gate of the fourth enhancement transistor (Q6) is connected to the first terminal (13) through the fourth resistor (R4). , The third enhancement transistor (Q5)
The power supply circuit for a telephone set in which the sources of the fourth enhancement transistor (Q6) and the source of the fourth enhancement transistor (Q6) are connected together to form the midpoint of the second arm (A2).