JPH0831028B2 - Divider for programmable controller - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divider for a programmable controller.

[Prior art]

Generally, in a programmable controller (hereinafter, abbreviated as PC), the same CPU executes the processing for controlling the external input device and the external output device and the four arithmetic operations. In a PC that requires time control, the four arithmetic operations are a bolt neck. Among the four arithmetic operations, multiplication and division have a problem that the algorithm is complicated and the processing time is long. In order to solve such problems, PCs that require high speed are also being provided with hardware dedicated to multiplication, but division requires complicated control and is linked with the CPU. Since it is necessary to do so, the current situation is that we do not yet have dedicated hardware. By the way, as a division method, a procedure as shown in FIG. 5 is considered. First, when the dividend Dd and the divisor Ds are given, the divisor Ds is subtracted from the upper part (0010) of the dividend Dd. If the result of the subtraction is negative, 0 is added to that digit of the quotient M and the dividend Dd is shifted left by one digit (or the divisor Ds is shifted right by one digit). If the result of the subtraction is positive or 0 (corresponding to the third time of the above subtraction), 1 is added to that digit of the quotient M, and the partial dividend Dp obtained as a result of the subtraction is moved to the left by one digit. Shift (or divisor
Shift Ds one digit to the right). This calculation is repeated a predetermined number of times to obtain the quotient M and the remainder R. The number of repetitions is determined by the difference in the number of digits between the dividend Dd and the divisor Ds. A general-purpose divider used in a large computer or the like has a configuration shown in FIG. 6 in order to realize the above algorithm as hardware. Here, the hardware for dividing only a positive number is shown. That is, the dividend Dd, the divisor Ds, and the number of repetitions N are given from the outside and set in the dividend shift register 71, the divisor register 72, and the counter 73, respectively. Further, when the calculation is completed, the quotient M is stored in the quotient shift register 74, and the remainder R is stored in the dividend shift register 71. Divisor Ds set in divisor register 72
Is input to the complementer 75 and the two's complement of the divisor Ds is obtained. The 2's complement of the divisor Ds is obtained because the partial dividend Dp is obtained by subtracting the divisor Ds from the dividend Dd by adding the dividend Dd. The output value of the complementer 75 is input to the adder 76. The adder 76 adds the 2's complement of the divisor Ds to the value set in the dividend shift register 71. When the output value of the adder 76 is a positive number or 0, the addition result is sent to the dividend shift register 71 via the selector 77 controlled by the selection signal sel generated corresponding to the sign bit of the output value of the adder 76. Return, next-stage partial dividend Dp
And At the same time, 1 is stored in the least significant bit of the quotient shift register 74 by the selection signal sel. On the other hand, when the output value of the adder 76 is a negative number, the selector 77 receiving the selection signal sel causes the dividend shift register 71
The contents stored in the dividend shift register
The value is returned to 71, and the partial dividend of the next stage is set to Dp. Also, 0 is stored in the least significant bit of the quotient shift register 74 by the selection signal sel. The addition by adder 76 is performed by the addition control signal add from the CPU of the PC.
Is executed each time is input, and the counter receives the decrement signal dec from the CPU each time an addition is performed.
The repeat count N stored in 73 is decremented by one. The value stored in the dividend shift register 71 and the quotient shift register 74 is the shift signal sft from the CPU.
In response, shift to the left by one digit. When the value stored in the counter 73 becomes 0 by repeating the above calculation, the calculation end signal end is returned to the CPU of the PC to notify the end of the calculation, and the value stored in the quotient shift register 74 at this point is The quotient M and the value stored in the dividend shift register 71 become the remainder R.

[Problems to be Solved by the Invention]

When the divider is configured as described above, the CPU of the PC tells the divider that the dividend Dd, the divisor Ds, the number of repetitions N, the addition control signal add, the shift control signal sft, and the decrement signal.
It is necessary to give dec, and it is necessary to return the quotient Q, the remainder R, and the operation end signal end from the divider to the CPU. In this way, the control of the divider requires multiple control signals, and if the timing of various control signals is set in the CPU, the load on the CPU will not be significantly reduced despite the provision of the divider. It will be. In particular, in the divider having the above configuration, it is necessary to receive control signals such as addition control signal add, shift control signal sft, and decrement signal dec from the CPU even during the division calculation, and the CPU is not completely released during the calculation. If processing is performed in parallel with other processing, it is necessary for the CPU to achieve load distribution by time-division processing, etc., and it becomes very troublesome to program such processing as application instructions on the PC. On the other hand, considering the divider, it can be seen that the number of iterations N can be determined by the divisor Ds if the maximum number of bits of the dividend Dd and the divisor Ds is limited. Further, in the divider used for the PC, the dividend Dd, the divisor Ds, and the operation start point are given from the CPU at the start of the operation, and the operation end point, the quotient Q, and the remainder R are returned to the CPU at the end of the operation. It is desirable to eliminate the exchange of signals with the CPU during calculation. The present invention has been made in view of the above viewpoint, and PC
With the CPU, only the dividend, divisor, quotient, remainder, calculation start point, and calculation end point are exchanged, and the exchange of signals with the CPU is eliminated during the calculation to minimize CPU load and speed up division. It is intended to provide a programmable controller divider that can be implemented.

[Means for Solving the Problems]

In the present invention, in order to achieve the above object, the first storage means and the second storage means in which the maximum bit lengths of the respective stored values are defined, and the second storage means based on the values stored in the first storage means And a subtraction means for subtracting the value stored in the first storage means, and a subtraction result is stored in the first storage means when the subtraction result is positive or zero, and an output value of the first storage means is stored in the first storage means when the subtraction result is negative. Selecting means, and shift means for shifting the value stored in the second storage means to the right by one digit relative to the value stored in the first storage means after subtraction.
The third storage means stores 1 in the corresponding digit when the subtraction result is positive or 0 and stores 0 in the corresponding digit when the subtraction result is negative, and stores the subtraction result after the subtraction is repeated a predetermined number of times. And a controller that stops the subtraction when the subtraction is performed by the number of repetitions, and the controller uses the programmable controller to divide the dividend and the divisor into the first storage unit and the second storage unit, respectively. When the operation start signal is received from the programmable controller in the state that the value is delivered to the programmable controller, consecutive 0s are removed from the most significant bit of the divisor and the most significant bit of the second storage means is set to 1. It is set by setting the value obtained by adding 1 to the number obtained by subtracting the number of remaining digits after removing consecutive 0s from the upper rank from the number of digits of the dividend, as the number of iterations. The number of times of repetition is returned to the programmable controller, and when the subtraction of the number of times of repetition is completed, an operation end signal is sent to the programmable controller to deliver the quotient stored in the third storage means and the remainder stored in the fourth storage means. I have to.

[Action]

According to the above configuration, the controller for controlling the division unit for obtaining the quotient and the remainder from the dividend and the divisor is provided, and in the controller, when the dividend and the divisor are given from the programmable controller and the operation start signal is input, The programmable controller determines the number of iterations based on the dividend and the divisor, determines that subtraction has been performed by the number of iterations, and outputs a computation end signal to pass the quotient and divisor. Since it is not necessary to send and receive a signal regarding division between the output and the reception of the operation end signal, other processing can be performed during the division.
In other words, pipeline processing enables high-speed calculation. When the number of repetitions is set, the number of repetitions is returned to the programmable controller.
It is possible to predict the time required until the end of the division based on the number of repetitions, and it is possible to select the content of the processing performed by the programmable controller before the end of the division based on the estimated time.

【Example】

In this embodiment, control signals for performing various controls inside the divider
A controller 10 that generates
Do not exchange signals with CPU of programmable controller)
I need it. The configuration of each part except the controller 10 is
Almost the same as the configuration of FIG. 6 described in the section “Prior Art”
Is. However, in this embodiment, signed division is performed.
And the dividend and divisor are both 32 bits.
ing. In addition, negative numbers are expressed in 2's complement.
To do. As shown in FIG. 1, the dividend Dd is passed through the selector 6
The dividend register 1 is set and the divisor Ds is the divisor shift level.
It is set in Dista 2. Also, the dividend Dd and the divisor Ds
The most significant bit, which is the sign bit of
11 and divisor code latch 12 respectively. dividend
Dd and divisor Ds are the instructions to start the calculation from the CPU of the PC.
Before the calculation start signal start is given to the controller 10,
Stand up and load signal ld1 output from controller 10
It is given from the PC in synchronization with the operation start signal start
Is output from controller 10 after is output
Synchronized with signal ld1, dividend register 1 and divisor respectively
It is latched in the shift register 2. Here, the dividend register
Star 1, divisor shift register 2, dividend code latch 11,
The divisor code latch 12 is reset by the operation start signal start.
It is supposed to be. The quotient M and the calculation result
And the remainder R are the quotient shift register 4 and the remainder shift, respectively.
It is stored in the register 5. Here, the quotient shift register 4
And the remainder shift register 5 has a dividend Dd and a divisor Ds.
The initialization signal init output immediately after the latch of
Is set. When the quotient M and the remainder R are obtained, the operation end
Completion signal end is output from controller 10 to the outside
Is indicated to the PC. The selector 6 provided before the dividend register 1 is
Depending on the switching signal sw1 from the tracker 10, the dividend Dd and the part
Which of the fractional dividend Dp is to be input to the dividend register 1
Select In the switching signal sw1, the dividend Dd is the dividend register
Pass the dividend Dd until it is latched by
Cuts the selector 6 so that it passes the partial dividend Dp.
Change it. In addition, data is stored in dividend register 1.
The write enable input WE that sets the timing for
The load signal ld1 described above and the load signal ld2 described later are logical
It is input via the circuit 21. This logic circuit 21 loads
Outputs the negation of the AND of the signal ld2 and the load signal ld1
The load signal ld1 rises and the load signal ld2 rises.
When falling, the data in the dividend register 1
Is being done. Internal calculation is a positive number
When the dividend Dd is a negative number, the complementer 13
Thus, the two's complement of the dividend Dd is obtained. However, 2
The complement of is calculated only once at the start of calculation,
Interface 13 will only pass data. Also, the dividend
When Dd is a positive number, complementer 13
I will only let it pass. The operation of complementer 13 is
The switching signal sw2 output from the controller 10
Can be replaced. This switching signal sw2 is used for the dividend code latch 11
Is set based on the dividend code signal sign1 which is the output of
It On the other hand, the divisor Ds is the divisor shift register as described above.
Taken in 2. The divisor shift register 2 is
Latch mode and shift by switching signal sw1
And the latch mode
Then, latch the data in synchronization with the signal to the clock input CK.
However, in shift mode, it is synchronized with the signal to clock input CK.
Shift the data to the left one digit at a time. Divisor shift register
The load signal ld1 and the control signal
Of the count signal cnt from the controller 10 via the logic circuit 22
Is entered. Logic circuit 22 counts with load signal ld1
Outputs the negation of the logical product with the signal cnt. Load signal ld1
Latch mode by switching signal sw1 when output
Is selected and the divisor Ds is stored in the divisor shift register 2.
Be cut. When the count signal cnt is input
Shift mode is selected by the switching signal sw1.
The divisor Ds set in the divisor shift register 2 is
One digit is shifted to the left in synchronization with the count signal cnt,
Meanwhile, in the controller 10, the divisor shift register 2
Register monitoring signal ri is used to determine whether the most significant bit is 1.
monitor by n. Divisor shift in controller 10
Counts when the most significant bit of register 2 becomes 1.
Stop the signal cnt and wait until the count signal cnt stops.
The value obtained by adding 1 to the number of generated unt signal cnt is repeated.
Let N be the number. When the number of iterations N is determined, the controller 10
Returns the lag signal flg to the PC, and the PC receives the flag signal flg
Then, the controller 10 corresponds to the number of repetitions N.
Request the number signal num. PC based on this frequency signal num
Then, estimate the time required for division, and
The appropriate process is selected and executed. Once the number of iterations N has been determined, the section of "Prior Art"
The calculation is performed according to the procedure described in. Divisor Ds is a positive number
If so, the two's complement of the divisor Ds is obtained, and the divisor Ds is a negative number.
If there is, the output of the divisor shift register 2 is directly added to the adder 3
Is input to Here, the two's complement of the divisor Ds is the complement
It is required without using a mentor. That is, the divisor shift level
Each bit of the register 2 is not inverted by the output selection signal.
Force and inverting output.
If the number Ds is a positive number, the output of the divisor shift register 2
Inverted output is selected and carry in adder 3
Output 1 to force CIN. That is, the divisor Ds is a positive number
And 1,0 of each bit of divisor Ds is inverted and 1 is
Since they are added, the two's complement of the divisor Ds is obtained.
It Output selection signal to divisor shift register 2 and adder
The signal to the carry input CIN of 3 is the divisor sign latch 12
Of the divisor code signal sign2, which is the output of
It is set to be 1 when it is a number. Divisor Ds is negative
Then, the output of the divisor shift register 2 becomes a non-inverted output.
Therefore, the carry input CIN of the adder 3 becomes 0. The adder 3 outputs the output value of the complementer 13 and the divisor shift
The output value of register 2 is added. Also carry input
If CIN is 1, add carry-in CIN to the least significant bit.
Calculate. The output value of adder 3 is 33 bits,
The bit becomes the sign bit. Sign of output value of adder 3
No. bit becomes the selection signal sel to the selector 7, and the remaining 3
2 bits are input to the selector 7. With selector 7
Depending on the selection signal sel, the output value of the adder 3
Or output 0, the output value of the adder 3 is output.
However, if it is shown to be a negative number, the complementer 13
Output the force value. That is, the output value of the selector 7 is a partial
It becomes the dividend Dp. The output value of the selector 7 shifts to the left by one digit.
Is set in the dividend register 1 via the selector 6.
To be Here, the output of the selector 7 and the selector
The input of 6 and the input are shifted by one digit and are connected.
A value obtained by shifting the output value of the selector 7 to the left by one digit by a line
Is input to the selector 6. Also, at this point
The switching signal sw1 to the controller 6 indicates the partial dividend Dp
Needless to say, it is set so that
Yes. The partial dividend Dp is the log output from the controller 10.
Latched in dividend register 1 in synchronization with the read signal ld2
It Also, the selection signal sel is added by the adder 3
Whether the result is 0 if the result is positive or 0, and 1 if it is negative
The selection signal sel via the knot circuit 23.
Set to the least significant bit of star 4. That is, the partial coverage
If the divisor Dp is a positive number or 0, the quotient shift register 4
The least significant bit is incremented by 1, and if it is a negative number, the quotient shift register
0 is set in the least significant bit of data 4. control
From La10, quotient shift signal msft together with load signal ld2
Is output and the partial dividend Dp is set in the dividend register 1.
The value set in the quotient shift register 4 is 1 digit
It is designed to be shifted to the left. Quotient shift signal msft
Is output each time the addition operation is performed by the adder 3.
The same number of times as the number of repetitions N, while the load signal
ld2 is output by the number of iterations N minus 1.
It Here, in the dividend register 1, the load signal ld2
Data is latched by the load signal ld1 in advance.
Therefore, as a result, the data of
Will be switched. The controller 10 is based on the divisor Ds.
Repeat the above procedure for the number of repetitions N calculated by
Controls each part. The calculation is repeated N times.
Then, the quotient M is stored in the quotient shift register 4.
It By the way, whether the quotient M becomes a positive number or a negative number depends on
It is determined by the sign of divisor Dd and divisor Ds (dividend
If the divisor and the divisor have the same sign, a positive number;
Exclusive output of divisor code latch 11 and divisor code latch 12
The output of the logic circuit 24 that outputs the logical OR is
Positive or negative can be determined. Therefore, the quotient M is a negative number
When it becomes, it is completed based on the output value of the logic circuit 24.
The mentor 14 complements the output value of the quotient shift register 4 by 2.
Calculate the number and set it as the quotient M. When the quotient M becomes a positive number,
The implementer 14 keeps the output value of the quotient shift register 4 as it is.
And let it be a quotient M. The dividend Dd is the maximum number and
Since the quotient M overflows when the number Ds is -1,
With the most significant bit of complementer 14 and the output of logic circuit 24
It is determined whether there is an overflow based on the
Overflow latch 16 is closed when low occurs.
Latch the buffalo signal over. On the other hand, the remainder shift register 5 is added by the adder 3.
Is selected, the selector is synchronized with the load signal ld2.
Latch the output value of 7. The remainder shift register 5 is
Switch mode and shift mode are selected by the switching signal sw3.
Selected, and clock input in latch mode.
Data is latched in synchronization with the signal to the
Mode, the data is moved to the right in synchronization with the signal to the clock input CK.
Shift one digit at a time. Clock of remainder shift register 5
Input signal CK has load signal ld2 and operation stop signal sto
p and the remainder shift signal rsft are input via the logic circuit 25.
I will be forced. The logic circuit 25 calculates and negates the load signal ld2.
Outputs the negation of the logical product of the stop signal stop and the remainder shift signal rsft
Force Load signal ld2 and operation stop signal stop are input
Latch mode is selected by the switching signal sw3.
Has been selected and is selected each time the adder 3 performs an addition operation.
The output value of the data 7 is latched. Therefore, the load signal
Repeated times N by ld2 and operation stop signal stop
The output value of the selector 7 will be latched. In addition,
The arithmetic shift signal stop is output to the extra shift register 5.
Immediately after that, the switching signal sw3 output from the controller 10
Shift mode, at which point the remainder shift register
Data stored in data 5 into the remainder shift signal rsft.
It shifts to the right one digit at a time. That is,
Residue shift residue at the time when the operation stop signal stop is output
The remainder stored in data 5 is 1 from the number of repetitions N
The digit shifts to the left by the number of subtracted digits.
No. rsft shifts to the right by (N-1) digits.
It If the dividend Dd is negative, is the remainder also negative?
Based on the dividend code signal sign1
Find the 2's complement of the output value of the remainder shift register 5 at 5
Let the remainder be R. When the dividend Dd is a positive number, the comp
The rementer 15 outputs the output value of the remainder shift register 5 as it is.
And let it be the remainder R. In this way, the remainder of the remainder shift signal rsft
When the digit alignment is complete, the controller 10
The calculation end signal end is output to the outside, and the CPU of the PC
And the remainder R. Therefore, the PC
Signals for synchronization, dividend Dd, divisor Ds, calculation for calculator
After the start signal start is given, the operation end signal e from the divider
Until nd is output, other processing is performed regardless of division.
Can be executed and pipes for division
Line processing becomes possible. Signals for operating each part are output by the above procedure.
In order to apply the force, the controller 10 is configured as shown in FIG.
Be done. For synchronization input from the PC to the controller 10
The system clock signal clk and three types of phase
Signals ph2, ph4, ph6, and dividend Dd, divisor from the CPU of the PC
When Ds and the operation start signal start are given, the division is started.
So that each signal is sequentially output. Phase signal ph2, ph4,
ph6 is a system clock signal clk (Fig. 3 (b), 4th).
Each half cycle in Fig. (A)) is defined as 1 phase and 6 phases
The second of the six phase signals that make up one cycle
Phase signal ph2, 4th phase signal ph4, 6th phase
The signal ph6 is used. Each phase signal ph2, ph4, ph6 is the third
As shown in Figures (c) to (e) and Figures 4 (b) to (d).
, Becomes "L" in the corresponding phase. When the CPU of the PC requests division, refer to Fig. 3 (a).
After giving the dividend Dd and the divisor Ds as shown in Fig. 3 (a)
(Part where the lines intersect), FIG. 3 (f), 4
As in Figure (e). Give the calculation start signal start (standing
Lower). Given the calculation start signal start,
As above, dividend register 1, divisor shift register 2,
The dividend code latch 11 and the divisor code latch 12 are reset respectively.
It is canceled. As shown in Fig. 3 (g) and Fig. 4 (f).
Control signal before the operation start signal start is given.
Only the load signal ld1 is generated from LA10.
Then, the load signal ld1 is the rising edge of the second phase signal ph2.
Latch that latches the negative of the operation start signal start when rising
OR of inverted output of circuit 31 and second phase signal ph2
To be obtained as the output signal of the logic circuit 32 that outputs
Has become. That is, the calculation start signal start is input.
Before the reset, the inverted output of the latch circuit 31 is "L",
Second phase signal ph2 becomes load signal ld1 and calculation starts
The first second phase signal ph2 after the signal start is input
2nd phase after is output as the load signal ld1
Inverted output of latch circuit 31 due to rising of signal ph2
Becomes “H”, and the load signal ld1 does not change after that.
It The non-inverted output Q of the latch circuit 31 is the initialization signal init.
Inverted output as shown in Fig. 3 (h) and Fig. 4 (g)
Is output (falls) when becomes “H”. initial
When the conversion signal init is output, the quotient shift register 4, the remainder
The shift register 5, the number counters 41, 51 described later, etc.
Reset is released. The dividend Dd and the divisor Ds rise when the load signal ld1 rises.
The dividend register 1 and the divisor shift register respectively.
When latched by the star 2, FIG. 3 (i) and FIG. 4 (h)
, The switching signal sw1 changes from "L" to "H".
Then, as described above, the dividend shift register 2 is latched.
Mode to shift mode and select
Switch so that the output of the controller 6 becomes the output of the selector 7.
It The switching signal sw1 is the sixth signal after the initialization signal init is generated.
Latch the output to "H" at the rising edge of phase signal ph6
It is obtained as the output of the latch circuit 33. Ie initialization
The sixth phase signal ph in the cycle in which the signal init is output
The switching signal sw1 rises with the rise of 6.
It After that, the switching signal sw1 is kept at "H" until the calculation is completed.
Be drunk The divisor shift register 2 is shifted by the switching signal sw1.
3 (j) and 4 (i) when switched to the mode
Divisor shift register synchronized with count signal cnt like
The divisor Ds latched in data 2 is shifted one digit to the left.
Be done. The count signal cnt is obtained as the output of the logic circuit 34.
To be In the logic circuit 34, after the initialization signal init is generated,
The output goes to "H" at the first fall of the second phase signal ph2
The output of the latch circuit 35 for latching and the divisor shift register
Register monitoring that becomes "L" when the most significant bit of 2 becomes 1
Signal rin (see Fig. 4 (j)) and system clock signal
Outputs the negation of the logical product with No. clk. Ie initialization
The signal init goes through the logic circuit 36 along with other signals described later.
Input to the latch circuit 35 before the initialization signal init is generated.
Alternatively, if another signal described later is “L”, the latch circuit 35
The output is held at "L". Initialization signal init is the second phase
It occurs at the rising edge of the signal ph2, and the switching signal sw1 is the first
The sixth phase signal within the same cycle as the generation of the period signal init
Since it rises with the rise of No. ph6, the latch
The output of the path 35 is output after the cycle when the switching signal sw1 rises.
The falling edge of the second phase signal ph2 in the cycle
Becomes "H". On the other hand, the register monitoring signal rin
Occurs when the most significant bit of shift register 2 becomes 1.
(Falls down), and is it "H" until then?
As for the count signal cnt, the switching signal sw1 has risen.
After that, after the output of the latch circuit 35 becomes "H", register monitoring
Until the visual signal is generated (“L”), the system clock
It is output as an inverted signal of the lock signal clk. divisor
When the most significant bit of shift register 2 becomes 1, the register
Data count signal rin is generated (becomes "L")
No. cnt stopped (maintained at “H”), divisor shift register
2 stops shifting the divisor Ds. The count signal cnt has a 5-bit up / down output.
A pair of counters 41 and 51 consisting of counters
It is also input to the force UP, and it is counted by each number counter 41, 51
Count up the number of times the signal cnt falls. each time
Number counters 41 and 51 are input to CLEAR input CLEAR respectively.
Is initialized by the initialization signal init (output value is 00
000), both count counters 41 and 51 receive a count signal.
The number of occurrences of signal cnt is set. That is, the number of times cow
The value obtained by subtracting 1 from the number of repetitions N is set in the
To be The count input of one counter 41, DOWN,
The down signal is input. Countdown signal
It is obtained as the output of the logic circuit 37. The logic circuit 37 is a latch
The output of the circuit 35, the output of the latch circuit 38, and the fourth phase
Outputs the negation of the logical product with the negation of the signal ph4. Latch times
The output of the latch circuit 35 is negated and the register monitoring signal is
The output of the logic circuit 39 that outputs the negation of the logical sum with the signal rin is
Input as data, generation of initialization signal init
After that, the data is changed by the rising edge of the sixth phase signal.
It is supposed to be. Therefore, the counting signal
After the output of signal cnt is started, the divisor shift register 2
The most significant bit becomes 1 and the register monitoring signal rin is generated.
When it falls (falls), the output of the logic circuit 39 becomes “H”,
The rise of the first 6th phase signal ph6 output after that
As the output rises, the output of the latch circuit 38 becomes "H".
is there. In short, the count down which is the output of the logic circuit 37
Is the cycle in which the count signal cnt has been output.
From the next cycle of, output with the 4th phase signal ph4.
Will be forced. The output of the latch circuit 38 is
When the number of returns N is decided, it becomes "H", so it is repeated
Issued as a flag signal flg that returns to the PC that the number has been determined.
When this flag signal flg is generated, the number of times
The output value of the counter 41 corresponds to the number of repetitions N
Estimate the time required for division by reading it as No. num
It By the way, the switching signal sw2 is the system clock signal clk.
Latch that latches the dividend code signal sign1 at the falling edge of
It is obtained as the output of the H circuit 42. This latch circuit 42 is
Initialization signal init and down input of frequency counter 41 to DOWN
The operating state is set based on the countdown signal and
It That is, when the initialization signal init is generated, the output is "H".
The countdown signal after the initialization signal init is generated.
Latch circuit 43 that latches the output at "L" at the falling edge of the signal
And the output of the latch circuit 43 and the initialization signal init.
And a logic circuit 44 that is provided, and the output of the logic circuit 44 is “H”.
And the output of the latch circuit 42 is kept at "L"
System clock signal clk when the output of circuit 44 is low
The dividend code signal sign1 is input to the latch circuit 42 at the falling edge of
It is designed to be latched. Logic circuit 44 latches
The negation of the logical product of the output of path 43 and the negation of the initialization signal init
Output. Therefore, the output of the logic circuit 44 is the initialization signal.
It goes to "L" with the occurrence of No. init and the first counter
It goes to "H" when the down signal falls. as a result,
The switching signal sw2 is the first signal after the initialization signal init is generated.
Dividend due to falling of system clock signal clk
It becomes the output corresponding to the code signal sign1, and then the first
Goes to "L" when the countdown signal of falls
Of. The output from the output terminals Q0 to Q4 of the frequency counter 41
Entered on road 45. In this logic circuit 45,
41 5-bit outputs are all "L" (that is, the output value is
It outputs a signal that is the countdown signal inverted until it reaches 0).
Force The output of this logic circuit 45 becomes the load signal ld2.
(See FIG. 4 (k)). In short, the load signal ld2 is
The countdown signal output to the frequency counter 41 opens.
From the start until the output value of the counter 41 becomes 1
In between, (N-1) load signals for the number of repetitions N
It outputs ld2. In addition, the frequency counter 41
Output from carry output CO when force overflows
(Hereafter, carry output CO) is set to "L" and output
When the underflow occurs, the output from the borrow output terminal BO (below
Below, borrow output BO is abbreviated)
ing. That is, the output values from the output terminals Q0 to Q4 are 0 to 11
Within the 111 range, carry output CO and borrow output BO
Are both "H", but when the output value exceeds the above range,
One becomes "L". Carry output CO and borrow output
BO is input to the logic circuit 46 that outputs the negation of the logical product,
The output of the logic circuit 46 is input to the latch circuit 47. latch
The circuit 47 outputs the logic circuit 46 after the initialization signal init is generated.
The output is inverted when the force rises. According to
The output of the latch circuit 47 is the initialization signal init.
Sometimes "L", carry output CO and borrow output BO
When either of the two becomes "L", it becomes "H". Computation stop signal stop is based on borrow output BO and latch circuit 46.
The output of the logic circuit 48 that outputs the logical sum of the output and
When the borrow output BO occurs, the logic circuit 46 and latch
A signal that becomes "L" only for the time delay due to path 47
No. stop is output (see FIG. 4 (l)). Computation stop
The signal stop is the RS flip-flop with the initialization signal init
Entered in 49. This RS flip-flop 49 is
In the state, the non-inverting output Q is set to “L”, and the initialization signal init
After the occurrence of the
The inverted output Q is set to "H". Non flip of RS flip-flop 49
The inverted output Q is input to the logic circuit 45, and the borrow output BO
The non-inverted output Q of the RS flip-flop 49 becomes "H".
After that, keep the load signal ld2 at "L".
It Further, the output of the RS flip-flop 49 is output to the logic circuit 45.
At the same time, the output of the latch circuit 46 is also input.
When carry output CO is generated from the Unta 41,
The output signal ld2 is output. The output terminals QO to Q4 of the frequency counter 41 are loaded with the load signal.
In the logic circuit 51 provided separately from the logic circuit 45 that creates ld2
Is also entered. The logic circuit 51 includes an RS flip-flop 49
The non-inverted output Q of is also input. From the counter 41
When the borrow output BO occurs, the counter 41 outputs
The outputs of the input terminals Q0 to Q4 are all “H” (that is, the output value is 11
111), logic circuit 51
When detected, the output is set to "H". Output of logic circuit 51
Force enters the RS flip-flop 52 with the initialization signal init.
I will be forced. The inverted output of this RS flip-flop 52 is
A logic circuit that outputs the negation of the logical sum with the countdown signal
Entered on path 53. Inverted output of RS flip-flop 52
Is "L" in the initialized state, and the output of the logic circuit 51 rises.
It rises to "H". Therefore, the logic circuit 53 is
When a countdown signal is generated, the countdown signal is
The inverted signal is output as the quotient shift signal msft (Fig. 4
(See (m)), quotient shift signal due to occurrence of borrow output BO
Stop msft. Therefore, the quotient shift signal
Means that msft will be output as many times as the number of repetitions N
Become. Here, the non-inverted output Q of the RS flip-flop 52
Is “H” until the borrow output of the frequency counter 41 falls.
Is input to the logic circuit 36 described above.
When the quotient shift signal msft ends,
The latch circuit 35 is controlled so that the down signal is stopped. By the way, when the divisor Ds is 0, the division result is not
This is an error because it will be indeterminate or indeterminate.
It is necessary to detect it. If divisor Ds is 0, divisor
The code signal sign2 is "L", and the carrier of the frequency counter 41 is
ー Output CO becomes “L” and carry output CO becomes “L”
Register monitoring signal rin is not generated
(Hold to “H”)
The combination of these signals determines whether the divisor Ds is 0 or not.
Set. That is, the logic circuit 54 uses the divisor code signal sign2
Is “L”, carry output CO is “L”, register monitoring signal is “H”
, The output is set to “H” and the count signal cn
Carry output CO after shifting all digits of divisor Ds by t
When becomes "L", it is determined that the divisor Ds is 0 and the output is
Set to “H”. The output of the logic circuit 54 is
Is input to the RS flip-flop 55. RS flip flow
In the initial state, the up 55 sets the inverted output to "L",
When the logic circuit 54 determines that the divisor Ds is 0,
The inverted output is set to "H" as the error signal err.
It As long as the error signal err does not occur, the RS flip-flop
The non-inverting output Q of the lop 55 is “H”, and the non-inverting output Q is
The error signal err that has been input to the logic circuit 36 described above
A countdown signal is output when is not generated
The latch circuit 35 is controlled as described above. By the way, the calculation stop signal stop is
It is also input to the latch circuit 56 that sets the output to “H” at the rising edge.
The output of this latch circuit 56 becomes the switching signal sw3.
(See FIG. 4 (n)). That is, as mentioned above,
The value obtained by subtracting 1 from the repeat count N is displayed in the count counter 41.
It is set, and the adder 3 is based on this value.
When the calculation stop signal stop is short after the addition of the specified number of times
Since it goes to "L" only for a while, the rising edge of the calculation stop signal stop
The switching signal sw3 is raised by and the remainder shift register 5 is switched.
Switch to soft mode. After the switching signal sw3 becomes "H", the counter 61
Based on the set value, the remainder shift signal rsft and the operation end
Generate the end signal end. That is, the frequency counter 61
Is set to the value obtained by subtracting 1 from the number of repetitions N
The output value from the output terminals Q0 to Q4 of the number counter 61 is 1
Until, the remainder shift signal rsft is output and the output value is
When the value becomes 0, the remainder shift signal rsft is stopped and the operation ends.
It is sufficient to output the end signal end. Counter 61
Down input DONW of RS flip-flop 52
Force, the output of the logic circuit 62, and the fourth phase signal ph4
Set the logic circuit 63 that outputs the negative of the logical product with the inverted signal.
The passed signal is input. The logic circuit 63 is a frequency counter
When the output value of 61 is other than 0, the output is set to "H". divisor
If Ds is not 0, when the quotient shift signal msft stops
Is the inverted output of the RS flip-flop 52 and the logic circuit 62
Since both output and “H”, quotient shift signal msft is stopped.
After stopping, the countdown signal which is the output of the logic circuit 63
Becomes the same signal as the fourth phase signal ph4. This cow
Shift-down signal is remainder-shifted as remainder shift signal rsft
It is input to the register 5 (see Fig. 4 (o)).
), The counter 44 by this countdown signal
When the output value of is 0, does the output of the logic circuit 63 become "H"?
, The remainder shift signal rsft is
(N-1) pieces are generated and stopped. When the output of the remainder shift signal rsft stops, the operation end signal
No. end rises (see Fig. 4 (p)). That is,
The quotient shift signal msft stops and the RS flip-flop 52
When the inverted output Q becomes "L", this non-inverted output Q and initialization
The output of the logic circuit 64 that outputs the logical sum of the signal init and
The value obtained by inverting and inverting the output of the logic circuit 62 decreases in the fourth phase.
Operates the latch circuit 65 that latches at the falling edge of the signal ph4
enable. In short, the latch circuit 65 is
Each time a countdown signal is input to 61, logic circuit 62
The inverted value of the output of
When the output value of 61 becomes 0, the output of the latch circuit 65 becomes the fourth
It goes to "H" with the falling edge of the phase signal ph4. La
The output of the switch circuit 65 is the same as the output of the RS flip-flop 55.
Is it input to the logic circuit 66 that outputs the negative of Riwa?
If the error signal err has not risen, the
With the end of the countdown signal for the Unta 61
The output of the logic circuit 66 falls. Also, the error signal err
If it rises, it will be discussed regardless of the output value of the frequency counter 61.
The output of the logic circuit 66 falls. The output of this logic circuit 66 is
It is output as the operation end signal end. Take
The countdown signal to the frequency counter 61
Output as the output signal rsft and the output value of the frequency counter 61
It becomes 0 and the shift of the contents of the remainder shift register 5 is completed.
When completed, the operation end signal end is generated. The CPU of the PC receives an interrupt from the operation end signal end.
Then, the quotient M and the remainder R are received from the divider.
It

【The invention's effect】

As described above, the present invention is provided with a controller that controls a division unit that obtains a quotient and a remainder from a dividend and a divisor, and in the controller, when the dividend and the divisor are given by a programmable controller and a calculation start signal is input, The programmable controller determines the number of iterations based on the dividend and the divisor, determines that subtraction has been performed by the number of iterations, and outputs a computation end signal to pass the quotient and divisor. Since it is not necessary to send and receive a signal regarding division between the output and the reception of the operation end signal, other processing can be performed during the division. That is, there is an advantage that a high-speed operation becomes possible by using the pipeline. Also, when the number of repeats is set, the number of repeats is returned to the programmable controller, so the programmable controller can predict the time required to complete the division based on the number of repeats, and the division ends. Before that, there is an advantage that the contents of the processing performed by the programmable controller can be selected based on the estimated time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of the present invention, FIG. 2 is a circuit diagram showing a controller used in the same as above, FIGS. 3 and 4 are operation explanatory diagrams of the same as above, and FIG. 5 is a principle of division. FIG. 6 is a block diagram showing a conventional example. 1 ... dividend register, 2 ... divisor shift register, 3
... Adder, 4 ... quotient shift register, 5 ... remainder shift register, 6, 7 ... selector, 10 ... controller.

Claims (1)

[Claims] 1. A first storage means and a second storage means in which a maximum bit length of each stored value is defined, and a value stored in the second storage means is subtracted from a value stored in the first storage means. Subtraction means for storing the subtraction result in the first storage means when the subtraction result is positive or 0, and storing the output value of the first storage means in the first storage means when the subtraction result is negative, and the subtraction After performing, the shift means for relatively shifting the value stored in the second storage means to the right by one digit with respect to the value stored in the first storage means, and when the subtraction result is positive or 0, the corresponding digit has 1 When stored and negative, 0 is stored in the corresponding digit; third storage means; fourth storage means for storing a subtraction result after repeating subtraction a predetermined number of times; Control to stop the subtraction ; And a over La, controller,
When an arithmetic start signal is received from the programmable controller with the dividend and the divisor being delivered from the programmable controller to the first storage means and the second storage means, respectively, consecutive 0s are removed from the most significant bit of the divisor. The most significant bit of the second storage means is set to 1, and the value obtained by subtracting 1 from the number of digits of the dividend and adding 1 to the number of digits remaining after removing consecutive 0s from the most significant digit of the divisor is repeated. It is set as the number of times, the set number of repetitions is returned to the programmable controller, and when the subtraction of the number of repetitions is completed, an operation end signal is sent to the programmable controller and the quotient stored in the third storage means and the fourth storage means. A programmable controller divider that delivers the remainder stored in the.