JPH0831029B2 - Approximate inverse generator for division - Google Patents
Approximate inverse generator for divisionInfo
- Publication number
- JPH0831029B2 JPH0831029B2 JP1177029A JP17702989A JPH0831029B2 JP H0831029 B2 JPH0831029 B2 JP H0831029B2 JP 1177029 A JP1177029 A JP 1177029A JP 17702989 A JP17702989 A JP 17702989A JP H0831029 B2 JPH0831029 B2 JP H0831029B2
- Authority
- JP
- Japan
- Prior art keywords
- divisor
- mantissa
- normal form
- binary
- reciprocal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
- G06F2207/5356—Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49936—Normalisation mentioned as feature only
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は除算用近似逆数生成装置に関し，特に除数の
仮数を２進正規形にしたのち，上位所定ビットから近似
逆数を生成する除数の近似逆数生成装置に関する。Description: TECHNICAL FIELD The present invention relates to an approximate reciprocal number generation device for division, and more particularly, to approximation of a divisor number that generates an approximate reciprocal number from a predetermined upper bit after converting a mantissa of a divisor into a binary normal form. The present invention relates to an inverse number generator.
［従来の技術］ 従来，除算を被除数と除数の近似逆数との積におきか
え，引放し法を用いて毎回多数桁の部分商を発生してい
くようなある種の除算装置（例えば，特開昭57−041737
号公報「除算装置」）では，除算の仮数を２進正規形に
したのちその上位所定ビットから近似逆数を生成してい
た。このような方式による近似逆数の生成は，例えば第
２図のような装置をもちいて実現されてきた。第２図に
おいて，除数レジスタ11は除算にもちいる除数の仮数を
格納するレジスタである。また，除数チェック回路12
は，除数レジスタ11出力の上位２ビットから除数レジス
タ11に格納された除数が２進正規形か否かを判定する。[Prior Art] Conventionally, a kind of division device that replaces a product of a dividend and an approximate reciprocal of a divisor with each other and generates a partial quotient of a large number of digits each time by using the parsing method (for example, Japanese Patent Laid-Open No. 2000-242242) Sho 57-041737
In Japanese Patent Laid-Open Publication "Division apparatus"), the mantissa of the division is made into a binary normal form, and then the approximate reciprocal is generated from the upper predetermined bits. Generation of an approximate reciprocal by such a method has been realized by using a device as shown in FIG. 2, for example. In FIG. 2, the divisor register 11 is a register for storing the mantissa of the divisor used for the division. Also, the divisor check circuit 12
Determines from the upper 2 bits of the output of the divisor register 11 whether the divisor stored in the divisor register 11 is in binary normal form.
ここで，除数を２の補数表示形状式とした場合の除数
チェック回路12の働きを第３図に示す。Here, FIG. 3 shows the operation of the divisor check circuit 12 when the divisor is a two's complement display form expression.
次に,2進正規化シフトカウント生成回路14は，除数レ
ジスタ11出力を入力とし，除数の仮数を２進正規形にす
るのに必要な左レフトカウントを生成する。また２進正
規化シフタ15は，除数レジスタ11出力を２進正規化シフ
トカウント生成回路14出力に応じて左シフトすることに
より２進正規形にする。Next, the binary normalization shift count generation circuit 14 receives the output of the divisor register 11 and generates the left left count required to make the mantissa of the divisor a binary normal form. Further, the binary normalization shifter 15 shifts the output of the divisor register 11 to the left according to the output of the binary normalization shift count generation circuit 14 to make it into a binary normal form.
ここで,2進正規化シフトカウント生成回路14および２
進正規化シフタ15の働きの例を第４図に示す。Here, the binary normalized shift count generation circuits 14 and 2
An example of the function of the decimal normalization shifter 15 is shown in FIG.
さらに，除数セレクタ10は，近似逆数の生成にあたり
最初に与えられる除数の仮数もしくは２進正規化シフタ
15出力を選択するセレクタである。近似逆数生成回路13
は除数レジスタ11出力の上位所定ビットから除数レジス
タ11に格納された除数の仮数の近似逆数を生成する。第
２図の回路をもちいての除数の近似逆数生成は，以下の
ようにおこなわれる。Further, the divisor selector 10 is a mantissa or binary normalization shifter of the divisor first given in the generation of the approximate reciprocal.
This is a selector that selects 15 outputs. Approximate inverse number generation circuit 13
Generates an approximate reciprocal of the mantissa of the divisor stored in the divisor register 11 from the upper predetermined bits of the output of the divisor register 11. Approximate reciprocal generation of the divisor using the circuit of FIG. 2 is performed as follows.
（１）除数の仮数を除数セレクタ10を介して除数レジス
タ11に格納する。(1) The mantissa of the divisor is stored in the divisor register 11 via the divisor selector 10.
（２）除数チェツク回路12において除数レジスタ11出力
が２進正規形か否かを判定する。(2) The divisor check circuit 12 determines whether the output of the divisor register 11 is in the binary normal form.
（３）除数チェック回路12において除数レジスタ11出力
が２進正規形であると判定された場合には（５）を実
行，そうでなければ（４）を実行する。(3) When the divisor check circuit 12 determines that the output of the divisor register 11 is in the binary normal form, (5) is executed, and otherwise (4) is executed.
（４）除数レジスタ11出力を２進正規化シフタ15をもち
いて２進正規化し，除数セレクタ10を介して再び除数レ
ジスタ11に格納し（５）を実行する。(4) The output of the divisor register 11 is binary-normalized using the binary normalization shifter 15, stored again in the divisor register 11 via the divisor selector 10, and (5) is executed.
（５）除数レジスタ11出力の上位ビットから近似逆数生
成回路13をもちいて除数の近似逆数を生成する。(5) The approximate reciprocal of the divisor is generated from the upper bits of the output of the divisor register 11 by using the approximate reciprocal generator 13.
なお，ここでは被除数の仮数部のとり扱いについては
説明を省略したが，除数の仮数を２進正規化した場合に
は，必要に応じて被除数の仮数部を同量だけ左シフトす
る必要があることは言うまでもない。Although the explanation of the handling of the mantissa part of the dividend is omitted here, if the mantissa part of the divisor is binary-normalized, it is necessary to shift the mantissa part of the dividend by the same amount to the left. Needless to say.
［発明が解決しようとする課題］ 上述した従来の近似逆数生成装置によれば，除数の仮
数部が２進正規形でなかった場合には，除数の仮数部を
いったん２進正規形にする必要があったため，近似逆数
の生成にかかる実行時間が長くなるといった欠点があっ
た。[Problems to be Solved by the Invention] According to the above-described conventional approximate reciprocal number generation device, when the mantissa part of the divisor is not the binary normal form, the mantissa part of the divisor needs to be once converted to the binary normal form. Therefore, there is a drawback that the execution time required to generate the approximate reciprocal becomes long.
なお，除数の仮数を２進正規形にするためには，まず
仮数の上位から符号ビットと同じ値のビットがいくつ連
続するかを求め，その値に従って仮数を左シフトすると
いった動作が必要であり，これは通常１ないし２クロッ
クサイクルかかる。In order to make the mantissa of the divisor a binary normal form, it is necessary to first find out how many bits of the same value as the sign bit continue from the higher order of the mantissa and shift the mantissa to the left according to that value. , This normally takes 1 to 2 clock cycles.
ここで，除数の指数の基数が16である場合を考える
と，ひとつのプログラム中に演算結果を正規化する浮動
小数点演算命令が他にいくつか存在すれば，浮動小数点
除算命令に使用される除数は，殆んどの場合,16進正規
形である。しかし，除数が16進正規形であったとして
も,2進正規形である確率は低い。したがって，指数の基
数を16とするプログラムにおける浮動小数点除算命令で
は，殆んどの場合において，除数の仮数を２進正規形に
なおすという無駄な実行時間が存在することになる。な
お，前述の従来例では，近似逆数の生成に用いる除数の
仮数は２進正規形でなければならないといった前提のも
とに説明をおこなったわけだが，これは「除数の仮数が
２進正規形」という条件がなければ，近似逆数を生成す
る為の金物量が多大になるという理由によるものであ
る。Considering that the base of the exponent of the divisor is 16, if there are some other floating point arithmetic instructions that normalize the operation result in one program, the divisor used for the floating point division instruction. Is in hexadecimal normal form in most cases. However, even if the divisor is hexadecimal normal form, the probability that it is binary normal form is low. Therefore, in almost all cases, the floating-point division instruction in a program whose exponent base is 16 has a wasteful execution time of converting the mantissa of the divisor into the binary normal form. In the above-mentioned conventional example, the explanation has been made on the assumption that the mantissa of the divisor used to generate the approximate reciprocal has to be in the binary normal form. This is because unless there is such a condition, the amount of metal to generate the approximate reciprocal becomes large.
すなわち，除数の最上位ビットと次のビットの間に小
数点があるとすれば,2進正規形の（２の補数表示）の除
数Ｙは であらわされ，その近似逆数ｒ≒1/Yは以下の範囲にお
さまる。That is, if there is a decimal point between the most significant bit and the next bit of the divisor, the divisor Y in binary normal form (two's complement notation) is The approximate reciprocal r≈1 / Y falls within the following range.
ところが「Ｙが２進正規形でない」とすると,r≒1/Y
の整数部が無限に増えつづける。仮に，除数Ｙに「除数
が16進正規形ならば」という条件にすれば，逆数の整数
部は有限の値にはなるが，「除数が２進正規形」という
条件の場合にくらべれば，近似逆数の生成に要する金物
は莫大なものとなる。 However, if "Y is not a binary normal form", then r≈1 / Y
The integer part of continues to grow infinitely. If the condition of the divisor Y is "if the divisor is in hexadecimal normal form", the integer part of the reciprocal will be a finite value, but compared to the condition of "divisor is in binary normal form", The hardware required to generate the approximate reciprocal is enormous.
本発明の目的は，以上の問題点を解決し，少量の金物
で効率良く除算用近似逆数を生成することにある。An object of the present invention is to solve the above problems and efficiently generate an approximate reciprocal for division with a small amount of metal.
［課題を解決するための手段］ 本発明による除算用近似逆数生成装置は，除算を被除
数と除数の近似逆数との積におきかえ引放し法を用いて
毎回多数桁の部分商を発生していく除算装置で用いられ
る浮動小数点除数の近似逆数生成装置であって，前記除
数の指数の基数より一意に決まる前記除数の仮数の上位
所定ビットから前記除数が基数正規形であるか否かを判
定する除数チェック回路と，前記除数が前記除数チェツ
ク回路において基数正規形であると判定された場合に，
前記除数の指数の基数より一意に決まる前記除数の仮数
の上位所定ビットから前記除数の仮数を２進正規形にす
るための第１の正規化シフトカウントを生成する第１の
正規化シフトカウント生成回路と，前記除数の仮数全体
から前記除数の仮数を２進正規形にするための第２の正
規化シフトカウントを生成する第２の正規化シフトカウ
ント生成回路と，前記第１の正規化シフトカウントをう
け，前記除数の近似逆数生成に必要な前記除数の仮数の
上位所定ビットのみを第１の２進正規形にして出力する
第１の正規化シフタと、前記第２の正規化シフトカウン
トをうけ，前記除数の仮数全体を第２の２進正規形にし
て出力する第２の正規化シフタとを有し，前記除数チェ
ック回路において前記除数が基数正規形であると判断さ
れる場合には，前記第１の正規化シフタの出力をもちい
て前記除数の近似逆数を生成し，そうでない場合には前
記第２の正規化シフタの出力のうち前記除数の近似逆数
生成に必要な上位所定ビットをもちいて前記除数の近似
逆数を生成することを特徴とする。[Means for Solving the Problem] The approximate reciprocal reciprocal generator for division according to the present invention replaces the division with the product of the dividend and the approximate reciprocal of the divisor, and generates a large number of partial quotients every time by using the release method. A device for generating an approximate reciprocal of a floating-point divisor used in a divider, which determines whether or not the divisor is in a radix normal form from the upper predetermined bits of the mantissa of the divisor uniquely determined by the radix of the exponent of the divisor. A divisor check circuit, and when the divisor is determined to be a radix normal form in the divisor check circuit,
First normalized shift count generation for generating a first normalized shift count for converting the mantissa of the divisor into a binary normal form from the upper predetermined bits of the mantissa of the divisor that is uniquely determined by the radix of the exponent of the divisor. A circuit, a second normalization shift count generation circuit for generating a second normalization shift count for converting the mantissa of the divisor into a binary normal form from the whole mantissa of the divisor, and the first normalization shift A first normalization shifter which receives a count and outputs only the upper predetermined bits of the mantissa of the divisor necessary for generating the approximate reciprocal of the divisor, and outputs the first binary normal form; and the second normalization shift count And a second normalization shifter that outputs the entire mantissa of the divisor in a second binary normal form, and when the divisor is determined to be in the radix normal form by the divisor checking circuit. Is before The output of the first normalization shifter is used to generate the approximate reciprocal of the divisor, and if not, the upper predetermined bits necessary for generating the approximate reciprocal of the divisor of the output of the second normalization shifter are used. And generating an approximate reciprocal of the divisor.
［実施例］ 次に，添付図面を参照しながら，本発明の実施例につ
いて説明する。[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.
第１図は，本発明の一実施例による除算用近似逆数生
成装置を示す図である。FIG. 1 is a diagram showing an approximate reciprocal reciprocal generator for division according to an embodiment of the present invention.
第１図において，除数セレクタ1,除数レジスタ2,2進
正規化シフトカウント生成回路7,及び２進正規化シフタ
８は，それぞれ，第２図中の除数セレクタ10,除数レジ
スタ11,2進正規化シフトカウント生成回路14,及び２進
正規化シフタ15と同様の働きをする。基数モード信号線
３は除数の指数の基数を示すモード信号線であり，例え
ば“1"なら16進モード（指数の基数＝24＝16），“0"な
ら２進モード（指数の基数＝21＝２）をあらわす。ま
た，除数チェック回路４は，基数モード信号線３の指示
に従い，除数レジスタ２の上位５ビットから除数レジス
タ２に格納された除数が基数正規形か否かを判定する。In FIG. 1, the divisor selector 1, the divisor register 2, the binary normalization shift count generation circuit 7, and the binary normalization shifter 8 are respectively the divisor selector 10, the divisor register 11, and the binary normalization in FIG. The same functions as the digitized shift count generation circuit 14 and the binary normalization shifter 15. The radix mode signal line 3 is a mode signal line indicating the radix of the exponent of the divisor. For example, "1" is the hexadecimal mode (exponent radix = 2 4 = 16), and "0" is the binary mode (exponent radix = 2 1 = 2) is represented. Further, the divisor check circuit 4 determines whether the divisor stored in the divisor register 2 from the upper 5 bits of the divisor register 2 is in the radix normal form according to the instruction of the radix mode signal line 3.
ここで，除数を２の補数表示形式とした場合の除数チ
ェック回路４の働きを第５図に示す。Here, the operation of the divisor check circuit 4 when the divisor is in the 2's complement display format is shown in FIG.
次に，逆数生成データシフトカウント生成回路５は，
指数モード信号線３の指示を受け，除数レジスタ２出力
の上位５ビットから除数レジスタ２に格納された除数が
基数正規形であった場合に，さらに２進正規形にするの
に必要な左シフトカウントを生成する。逆数生成データ
シフト回路６は，逆数データシフトカウント生成回路５
出力をうけ，除数レジスタ２出力のうち，近似逆数生成
回路９で必要とする上位所定ビットのみ左シフトして２
進正規化し，近似逆数生成回路９に近似逆数を生成する
為のデータを供給する。Next, the reciprocal generation data shift count generation circuit 5
When the divisor stored in the divisor register 2 from the upper 5 bits of the output of the divisor register 2 is in the radix normal form in response to the instruction from the exponential mode signal line 3, the left shift is required to make the binary normal form. Generate a count. The reciprocal data shift count generation circuit 6 includes a reciprocal data shift count generation circuit 5
After receiving the output, of the output of the divisor register 2, only the upper predetermined bits required by the approximate reciprocal generation circuit 9 are left-shifted to 2
Data for generating an approximate reciprocal number is supplied to the approximate reciprocal number generating circuit 9 after the normalization is performed.
ここで，逆数データシフトカウント生成回路５および
逆数データシフト回路６の働きを第５図に示す。The functions of the reciprocal data shift count generation circuit 5 and the reciprocal data shift circuit 6 are shown in FIG.
第１図の回路をもちいての除数の近似逆数の生成は，
以下のようにおこなわれる。Generation of the approximate reciprocal of the divisor using the circuit of FIG.
This is done as follows.
（１）除数レジスタ２に除数セレクタ１を介して除数の
仮数を格納する。(1) The mantissa of the divisor is stored in the divisor register 2 via the divisor selector 1.
（２）基数モード信号線３の指示に従い，除数チェック
回路４において除数レジスタ２の出力が基数正規形か否
かを判定する。(2) According to the instruction of the radix mode signal line 3, the divisor check circuit 4 determines whether or not the output of the divisor register 2 is in the radix normal form.
（３）除数チェック回路４において，除数レジスタ２出
力が基数正規形であると判断された場合に（５）を実行
し，そうでない場合には（４）を実行する。(3) If the divisor check circuit 4 determines that the output of the divisor register 2 is in the radix normal form, (5) is executed, and if not, (4) is executed.
（４）除数レジスタ２出力を２進正規化シフト８をもち
いて２進正規形にし，除数セレクタ１を介して再び除数
レジスタ２に格納し，（５）を実行する。(4) The output of the divisor register 2 is converted to the binary normal form by using the binary normalization shift 8 and stored again in the divisor register 2 via the divisor selector 1 to execute (5).
（５）基数モード信号線３の指示に従い，除数レジスタ
２の上位５ビットをもとに除数レジスタ２出力を２進正
規形にするのに必要なシフトカウントを逆数生成データ
シフトカウント生成回路５においてもとめ，これをもと
に近似逆数を生成するのに必要な除数レジスタ２の上位
所定ビットのみを逆数データシフト回路６において左シ
フトして近似逆数生成回路９に供給し，近似逆数生成回
路９において除数の近似逆数を生成する。(5) In accordance with the instruction of the radix mode signal line 3, the reciprocal number generation data shift count generation circuit 5 calculates the shift count necessary for converting the output of the divisor register 2 into the binary normal form based on the upper 5 bits of the divisor register 2. First, based on this, only the upper predetermined bits of the divisor register 2 necessary for generating an approximate reciprocal are left-shifted in the reciprocal data shift circuit 6 and supplied to the approximate reciprocal generator 9, and the approximate reciprocal generator 9 Generates the approximate reciprocal of the divisor.
ここで，演算結果を正規形にするような浮動小数点命
令を含むフログラム中に浮動小数点除算命令が存在する
場合について考える。このとき，浮動小数点除算命令で
用いられる除数は，殆んどの場合，正規形である（指数
の基数が２であれば２進正規形,16であれば16進正規
形）。すると，本発明によれば，除算命令の実行におい
て，通常は１ないし２クロックサイクルかかるところの
除数の仮数全体の（仮数全体をみて正規化シフトカウン
トを求める）２進正規化という動作（前述の（４）の動
作）を殆んどの場合省略できることになり，実行性能を
向上できることがわかる。Here, consider a case where a floating-point division instruction exists in a program that includes a floating-point instruction that makes the operation result a normal form. At this time, the divisor used in the floating point division instruction is in the normal form in most cases (binary normal form if the radix of the exponent is 2, hexadecimal normal form if the exponent base is 16). Then, according to the present invention, in the execution of the division instruction, an operation called binary normalization of the entire mantissa of the divisor (which obtains the normalized shift count by looking at the entire mantissa) which normally takes 1 or 2 clock cycles (the above-mentioned operation). It is understood that the operation (4) can be omitted in almost all cases, and the execution performance can be improved.
なお，本実施例においても，被除数の仮数のとり扱い
については説明を省略したが，除数の仮数を２進正規形
にした場合には，必要に応じて被除数の仮数を同量だけ
左シフトする必要があることは言うまでもない。In the present embodiment as well, description of the handling of the mantissa of the dividend is omitted, but when the mantissa of the divisor is in binary normal form, the mantissa of the dividend is left-shifted by the same amount as necessary. Not to mention the need.
［発明の効果］ 以上説明したように，本発明によれば，少量の金物量
の追加だけで除算にもちいる除数の近似逆数生成を効率
良く実行することができ，浮動小数点命令（特に指数の
基数が16＝24の浮動小数点除算命令）の実行性能を向上
できる。[Effects of the Invention] As described above, according to the present invention, it is possible to efficiently execute the approximate reciprocal generation of a divisor used for division by adding a small amount of metal, and to execute floating-point instructions (especially radix can be improved 16 = 2 4 execution performance of floating point divide instructions).
第１図は本発明の一実施例による除算用近似逆数生成装
置を示すブロック図，第２図は従来の除算用近似逆数生
成装置を示すブロック図，第３図は第２図における除数
チェック回路12の働きを示す図，第４図は第１図および
第２図における２進正規化シフトカウント生成回路およ
び２進正規化シフタの働きを示す図，第５図は第１図に
おける除数チェック回路4,逆数データシフトカウント生
成回路5,および逆数データシフト回路６の働きを示す図
である。 １……除数セレクタ,2……除数レジスタ,3……基数モー
ド信号線,4……除数チェック回路,5……逆数生成データ
シフトカウント生成回路,6……逆数生成データシフト回
路,7……２進正規化シフトカウント生成回路,8……２進
正規化シフタ,9……近似逆数生成回路。1 is a block diagram showing an approximate reciprocal number generator for division according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional approximate reciprocal number generator for division, and FIG. 3 is a divisor check circuit in FIG. 12 is a diagram showing the operation of FIG. 4, FIG. 4 is a diagram showing the operation of the binary normalized shift count generation circuit and the binary normalized shifter in FIGS. 1 and 2, and FIG. 5 is the divisor check circuit in FIG. 4 is a diagram showing the operation of a reciprocal data shift count generation circuit 5 and a reciprocal data shift circuit 6. FIG. 1 ... Divisor selector, 2 ... Divisor register, 3 ... Radix mode signal line, 4 ... Divisor check circuit, 5 ... Reciprocal generation data shift count generation circuit, 6 ... Reciprocal generation data shift circuit, 7 ... Binary normalization shift count generation circuit, 8 ... Binary normalization shifter, 9 ... Approximate reciprocal number generation circuit.
Claims (1)
きかえ引放し法を用いて毎回多数桁の部分商を発生して
いく浮動小数点除算装置でもちいられる除数の近似逆数
生成装置であって， 前記除数の指数の基数より一意に決まる前記除数の仮数
の上位所定ビットから前記除数が基数正規形であるか否
かを判定する除数チェック回路と， 前記除数が前記除数チェック回路において基数正規形で
あると判定された場合に，前記除数の指数の基数より一
意に決まる前記除数の仮数の上位所定ビットから前記除
数の仮数を２進正規形にするための第１の正規化シフト
カウントを生成する第１の正規化シフトカウント生成回
路と， 前記除数の仮数全体から前記除数の仮数を２進正規形に
するための第２の正規化シフトカウントを生成する第２
の正規化シフトカウント生成回路と， 前記第１の正規化シフトカウントをうけ，前記除数の近
似逆数生成に必要な前記除数の仮数の上位所定ビットの
みを第１の２進正規形にして出力する第１の正規化シフ
タと、 前記第２の正規化シフトカウントをうけ，前記除数の仮
数全体を第２の２進正規形にして出力する第２の正規化
シフタとを有し， 前記除数チェック回路において前記除数が基数正規形で
あると判断される場合には，前記第１の正規化シフタの
出力をもちいて前記除数の近似逆数を生成し，そうでな
い場合には前記第２の正規化シフタの出力のうち前記除
数の近似逆数生成に必要な上位所定ビットをもちいて前
記除数の近似逆数を生成することを特徴とする除算用近
似逆数生成装置。1. An approximate reciprocal reciprocal generator for a divisor, which is used in a floating point divider for generating a large number of partial quotients every time by replacing the product with the product of the dividend and the approximate reciprocal of the divisor. A divisor check circuit that determines whether or not the divisor is in a radix normal form from the upper predetermined bits of the mantissa of the divisor that is uniquely determined by the radix of the divisor exponent; and the divisor is a radix normal in the divisor check circuit. Form, a first normalized shift count for converting the mantissa of the divisor into a binary normal form from the upper predetermined bits of the mantissa of the divisor, which is uniquely determined by the radix of the exponent of the divisor. A first normalized shift count generating circuit for generating a second normalized shift count for converting the mantissa of the divisor into a binary normal form from the entire mantissa of the divisor;
And the first normalized shift count, and outputs only the upper predetermined bits of the mantissa of the divisor necessary for generating the approximate reciprocal of the divisor in the first binary normal form. A first normalization shifter; and a second normalization shifter which receives the second normalization shift count and outputs the entire mantissa of the divisor as a second binary normal form. If the circuit determines that the divisor is in radix normal form, the output of the first normalization shifter is used to generate an approximate reciprocal of the divisor; otherwise, the second normalization is performed. An approximate reciprocal number generation apparatus for division, wherein an approximate reciprocal number of the divisor is generated by using high-order predetermined bits necessary for generating the approximate reciprocal number of the divisor among outputs of the shifter.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177029A JPH0831029B2 (en) | 1989-07-11 | 1989-07-11 | Approximate inverse generator for division |
| US07/551,094 US5153851A (en) | 1989-07-11 | 1990-07-11 | Method and arrangement of determining approximated reciprocal of binary normalized fraction of divisor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177029A JPH0831029B2 (en) | 1989-07-11 | 1989-07-11 | Approximate inverse generator for division |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0342715A JPH0342715A (en) | 1991-02-22 |
| JPH0831029B2 true JPH0831029B2 (en) | 1996-03-27 |
Family
ID=16023903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1177029A Expired - Lifetime JPH0831029B2 (en) | 1989-07-11 | 1989-07-11 | Approximate inverse generator for division |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5153851A (en) |
| JP (1) | JPH0831029B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2502836B2 (en) * | 1991-03-19 | 1996-05-29 | 富士通株式会社 | Preprocessing device for division circuit |
| JP3012357B2 (en) * | 1991-05-29 | 2000-02-21 | 日本電気株式会社 | Shift amount detection circuit |
| US5768171A (en) * | 1996-06-28 | 1998-06-16 | Intel Corporation | Method and apparatus for improving the precision or area of a memory table used in floating-point computations |
| US5923577A (en) * | 1996-10-21 | 1999-07-13 | Samsung Electronics Company, Ltd. | Method and apparatus for generating an initial estimate for a floating point reciprocal |
| US7058675B1 (en) * | 2000-09-28 | 2006-06-06 | Altera Corporation | Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices |
| US7080112B2 (en) * | 2002-11-13 | 2006-07-18 | International Business Machines Corporation | Method and apparatus for computing an approximation to the reciprocal of a floating point number in IEEE format |
| JP4564287B2 (en) | 2004-06-15 | 2010-10-20 | 株式会社東芝 | Drum washing machine |
| JP5061688B2 (en) * | 2007-03-29 | 2012-10-31 | 富士通セミコンダクター株式会社 | Data transfer control device and data transfer control method |
| US9658827B2 (en) * | 2014-10-21 | 2017-05-23 | Arm Limited | Apparatus and method for performing reciprocal estimation operation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3633018A (en) * | 1969-12-18 | 1972-01-04 | Ibm | Digital division by reciprocal conversion technique |
| GB2115190B (en) * | 1982-02-10 | 1985-11-20 | Singer Co | Data word normalisation |
| JPS60142738A (en) * | 1983-12-30 | 1985-07-27 | Hitachi Ltd | Division device using interpolation approximation |
| US4789956A (en) * | 1985-10-16 | 1988-12-06 | Harris Corp. | Maximum negative number detector |
| US4905178A (en) * | 1986-09-19 | 1990-02-27 | Performance Semiconductor Corporation | Fast shifter method and structure |
| US4823301A (en) * | 1987-10-22 | 1989-04-18 | Tektronix, Inc. | Method and circuit for computing reciprocals |
-
1989
- 1989-07-11 JP JP1177029A patent/JPH0831029B2/en not_active Expired - Lifetime
-
1990
- 1990-07-11 US US07/551,094 patent/US5153851A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0342715A (en) | 1991-02-22 |
| US5153851A (en) | 1992-10-06 |
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