JPH0831031B2 - Program instruction execution device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving the problem (Fig. 1) Operation Example Effect of the invention [Outline] Execution of program instructions Regarding the device, the program instruction for writing N bytes of data to the memory is sequentially repeated for the purpose of making it possible to judge the micro instruction branch in one step by configuring not to further -1 when the counter is zero. , By executing a program instruction that writes data of less than N bytes to memory,
In the program instruction execution device that writes N bytes or more of data to the memory, the value is updated at a constant value each time 1 byte of data is written, and when the length of the data to be written to the memory becomes less than N bytes. When the initial value is set so that the value becomes 0, and when the value becomes 0, the counter that does not update the value even if the data of less than N bytes is written to the memory byte by byte and the value of the counter are Whether to repeat the execution of the program instruction that updates the fixed value corresponding to N bytes, checks whether the counter value is 0 every time the memory write of N bytes of data is executed, and writes the N bytes of memory It is characterized by comprising a control circuit for controlling whether or not.

[Industrial applications]

The present invention relates to a program instruction execution device, and in particular, it is possible to exit from a microinstruction loop by using a counter controlled by the instruction of a microinstruction, and at the same time, it is possible to realize a memory write repeated in units of a plurality of bytes with a small number of instruction steps. Regarding things.

[Conventional technology]

In a computer, when performing loop processing by a microinstruction, for example, when writing is performed, the value of a counter is used to exit from this loop, for example, to advance to the next step at the end of writing.

For example, when writing 3 bytes of data in the memory, the counter is subtracted 3 times by -1 for high speed writing, 3 bytes are written when the counter is subtracted 3 times, and 1 byte is written 3 times when the counter is decremented 3 times. There is a method to do.

In the former method, when the number of bytes to be written is M and the number of bytes to be written at one time is N, the counter is M- (N
Initialize to -1). For example, if the number of bytes to be entered is 7, and the byte length to be entered at one time is 3, the counter is 7-
(3-1) = 5 is initialized. And the counter is -1
Subtract 3 times each and fill in 3 bytes the 3rd time. At this time, the value of the counter becomes 2, that is, "010", and once again 3
The byte writing routine is repeated, the counter is again decremented by -1 three times, and the third byte is written. At this time, the counter becomes "001", "000", "111". Therefore, when the counter is "111", the process exits from the 3-byte writing loop, and by decoding "111", the remaining 1 byte is recognized and the 1-byte writing process is started. .

Similarly, when entering 8 bytes, set the counter to 8- (3
-1) = 6 is initialized and the counter is "000" when the 3-byte writing loop is repeated twice, so the decoding of this makes it possible to recognize the existence of the remaining 2 bytes, and exit from the 3-byte writing loop. Move to the 2-byte entry process.
When writing 3 bytes, set the counter to 3- (3-1) =
When it is initialized to 1, and when 3 bytes are written after -1 subtraction is performed, the counter becomes "110", so this exits the 3-byte entry loop and this "11"
By decoding "0", it is recognized that the number of remaining bytes is zero. When writing 3 bytes at a time, the counter status is "000", "111", or "110".
It was necessary to determine whether or not to exit the loop. FIG. 4 (A) shows a flowchart of this state. Generally, when the number of bytes to be written at one time is N, it is necessary to determine the pattern of the N times counter.

Also, in the latter method, when writing 1 byte at a time and decrementing the counter by -1 each time, the counter is set to 3 first, and when writing 1 byte, the counter is decremented by 1.
Since the write routine is exited when the counter becomes all zero, every time one byte is written, it is checked whether or not the counter is all zero. FIG. 4B shows the flow chart in this state.

[Problems to be Solved by the Invention]

Therefore, in the former method shown in FIG. 4 (A), it is necessary to prepare and compare three patterns in order to get out of the write loop, so that three steps (N Not only N steps are required for writing a byte length), but a counter pattern corresponding to the number of steps is prepared, so that a storage capacity for storing the counter pattern is required. In the latter method shown in FIG. 4 (B), since the pattern of the counter must be checked every time, the number of steps for this purpose becomes large and only one byte can be written at a time. Becomes longer.

Therefore, it is an object of the present invention to perform the determination for exiting from such a loop in only one step with one pattern of the counter, and moreover, a program instruction that can realize a memory write repeated in a unit of a plurality of byte lengths with a small number of instruction steps. It is to provide an execution device.

[Means for solving the problem]

In order to achieve the above object, in the present invention, as shown in FIG. 1, when the count value becomes zero once, the zero stop counter 4 which does not count any more is used. This zero-stop counter is controllable by a microinstruction, and the control circuit 3 controls a microinstruction branch.

For example, when the microinstruction read out from the microinstruction holding memory 1 is once retained in the microinstruction output register 2 and the control circuit 3 operates in response to this, when this microinstruction is, for example, a 4-byte entry instruction in a memory (not shown). , The zero-stop counter 4 is set to 4- (3-1) = 2, and the zero-stop counter 4 is continuously set three times-
When 1 is controlled and 3 bytes are written for the third time, it becomes zero when -1 is performed twice, and this state of zero is maintained even for -1 at the third time. Therefore, the control circuit 3 only checks whether or not the zero-stop counter 4 is zero, and if it is zero, it is possible to exit this 3-byte write routine.

[Action]

Since the exit from the routine can be performed by checking only one pattern, not only the memory capacity for holding the pattern can be reduced, but also only one check step is required.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an operation explanatory diagram thereof.

In FIG. 2, the same symbols as those in FIG. 1 indicate the same parts, and thus the description thereof will be omitted.

The zero-stop counter 4 includes registers 4-0 and 4-
1, 4-2, a -1 subtraction circuit 4-3, and AND gates 4-4, 4-5. And Gate 4-4
An inverter is formed at the input part of each of the registers 4-0 to 4-2. The counter set clock is output to each of the registers 4-0 to 4-2 via the AND gate 4-5. The -1 subtraction circuit 4-3 subtracts -1 from the 3-bit output value of the registers 4-0 to 4-2. The output of the register 4-2 is the least significant bit and the output of the register 4-0 is the output. It is -1 from the value displayed by 3 bits which is the most significant bit. For example, the output of these registers 4-0 to 4-2 is "10.
When it is "1", "100" which is -1 is output from this, and each bit is set in the corresponding register 4-0 to 4-2. However, when the counter set clock is not applied to the registers 4-0 to 4-2, the output of the -1 subtraction circuit 4-3 is not set to the registers 4-0 to 4-2. Therefore, when the registers 4-0 to 4-2 output all zeros, that is, when it is "000", it is -1 from this.
When the subtracted "111" is output by the -1 subtraction circuit 4-3,
If the counter set clock is not applied, the registers 4-0 to 4-2 are not set.

The outputs of the registers 4-0 to 4-2 are the -1 subtraction circuit 4-
Not only 3 but also to the AND gate 4-4.
However, since an inverter is provided at each input portion of the AND gate 4-4, these registers 4-0 to 4-
AND gate 4 when the output of 2 is 1 even if it is 1 bit
-4 outputs "0"'. But And Gate 4-
Since an inverter is also provided in the input part of the AND gate 4-4 in 5, the AND gate 4-5 outputs the counter set clock when the AND gate 4-4 outputs "0". Each register 4-0
4-2 is applied.

However, when all the registers 4-0 to 4-2 output "0", "1" is output from the AND gate 4-4, so that the AND gate 4-5 sets the counter set.
The clock is not output, and the registers 4-0 to 4-2 retain zero. This state is maintained until another counter set clock is applied to the registers 4-0 to 4-2 by appropriate means.

Therefore, when the operation output in the -1 subtraction circuit 4-3 is "000", it is held in the state set in the registers 4-0 to 4-2, and therefore, as shown in FIG. It is possible to exit from the loop of the 3-bit write routine by checking whether the output of the registers 4-0 to 4-2, that is, the counter, is "000" for one step after -1.

In a normal transfer process or the like, since the number of transferred bytes is large, the determination loop will be repeated many times. At this time,
In the present invention, the steps for checking the loop out of the write routine are shorter than the conventional steps, so that the total number of steps can be reduced even if the remaining write determination is performed. .

Note that the above explanation is for the case where the counter has 3 digits, and 1
Although the case of writing 3 bytes at a time has been described, the present invention is of course not limited to the number of digits, the byte length in writing, the case of writing, and the like.

〔The invention's effect〕

According to the present invention, it is sufficient to determine whether or not the counter is zero before leaving the loop, and the determination can be performed in only one step.

In addition, the memory write that is repeated in the unit of a plurality of bytes can be realized with a smaller number of instruction steps than the conventional one.

As described above, according to the present invention, in the loop of the microinstruction controlled by the value of the counter, when exiting from the loop, it is not necessary to judge the value of the counter by the number of times of subtraction in the loop. Therefore, the number of steps of the micro instruction can be reduced. Also, only one type of determination pattern is required, and a plurality of determination patterns are unnecessary, so the storage capacity may be small.

In this way, it is possible to improve the performance of the computer and reduce the amount of hardware for the memory that stores microinstructions.

[Brief description of drawings]

 FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention, FIG. 3 is a diagram illustrating the operation of the present invention, and FIG. 1 ... Micro instruction holding memory 2 ... Micro instruction output register 3 ... Control circuit 4 ... Zero stop counter

Front page continuation (72) Inventor Kazuyasu Nonomura, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Takumi Maruyama, 1015, Kamedota, Nakahara-ku, Kawasaki, Kanagawa (72) Inventor Takumi Takeno 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Shinya Kato 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa FUJITSU LIMITED (56) Reference JP 60-49938 (JP, B2)

Claims (1)

[Claims] 1. A program for writing data of N bytes or more to a memory by sequentially repeating a program instruction of writing N bytes of data to the memory and further executing a program instruction of writing data of less than N bytes to the memory. In the instruction execution unit, the value is updated every time a 1-byte data is written, and the initial value is set so that the value becomes 0 when the length of the data to be written to the memory becomes less than N bytes. , When the value becomes 0, a counter that does not update the value even if the data less than N bytes is written to the memory byte by byte, and the counter value is updated by a constant value corresponding to N bytes. , Each time a memory write of N bytes of data is executed, it is checked whether or not the value of the counter is 0, and the execution of the program instruction to write the memory of N bytes Program instruction execution device characterized by comprising a control circuit for controlling whether or not return Ri.