JPH0831049B2 - Locked processor method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection system for a data processing device, and more particularly, a locked processor system in which two data processing devices simultaneously perform the same operation to detect fraud. Regarding

[Conventional technology]

In order to improve the data integrity of the data processing device, there are various types of conventional locked processor systems in which two data processing devices execute the same processing, but a typical example is COMPUTER. (Volume
17, Number8, August′84) Intel 432; A
VLSI Archetecture for Fault Tolerant Computer Syst
It is shown in ems.

This Intel 432 computer has two GDP (Gene
ralized Data Processor) is connected to the multi-bus, one is the master, the other is defined as a checker and have the same operation at the same time. At this time, the master GDP outputs data with parity added to the bus, and the checker GDP inputs the data output by the master GDP to the bus and compares it with its own internal data.

[Problems to be solved by the invention]

In the conventional locked processor method described above, all data including parity is output from the data processing device side defined as the master, and the data processing device on the check side does not output anything to the bus, and the data on the bus is always output. Since it is only checked by comparing the data with its own data, if the master data processing device operates illegally, if you look only at the data on the bus, the parity is always correct and the normal data format. The data transmitted to the bus when the data processing device on the receiving side detects an error is always processed as correct data on the receiving side (for example, the storage device). If data is written to the wrong address in the storage device due to such an illegal operation, it will be difficult to restart the data anymore. Therefore, even if the illegal operation is performed, the receiving side will process it as correct data. It is desirable to reduce the probability.

The present invention has been made in view of such circumstances, and an object thereof is to allow a parity error to occur on the receiving side as much as possible when an illegal operation occurs in any of the data processing devices. , To increase the likelihood of restarting the system.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention provides a locked processor system in which two data processing devices are connected to the same bus to execute the same processing at the same time to perform an operation check. First selection means for selectively outputting only the data part of the data with parity in the data processing device to the bus; and second selecting means for selectively outputting only the parity part of the data with parity to the bus. Selecting means, first comparing means for receiving the data part on the bus, and comparing the received data part with the data part of the data with parity in the data processing device, and the first comparing means. A first control means for controlling validity and invalidity; and a second control means for receiving a parity part on the bus and comparing the received parity part with a parity part of data with parity in the data processing device. Comparing means and second controlling means for controlling the validity and invalidity of the second comparing means are provided, and when one data processing device outputs a data section to the bus, the other data processing device is parity. The first and second control means are controlled so as to output a unit to the bus, and each data processing device further includes a data unit or a parity unit which is not itself output to the bus, and a data on the bus. The first and second control means are set so as to compare the data section or the parity section, and when any one of the data processing apparatuses detects a comparison disagreement, one of the data processing apparatuses performs an illegal operation. Is configured to generate a signal indicating

[Action]

One data processing device outputs only the data part of the internal parity-added data to the bus, and the other data processing device outputs only the parity part of the internal parity-added data to the bus. Data is formed. Therefore, when any one of the data processing devices is illegally operated, the parity-added data on the bus is parity-checked to the extent depending on the format of the parity, that is, the format of how many bits of the data have 1-bit parity. Since an error occurs, the probability that the data with parity on the bus will be processed as correct data can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of a data processing system to which the present invention is applied. In the figure, reference numeral 200 denotes a system bus, which provides a data transfer path between devices in the system.
The system bus 200 corresponds to the multi-bus in the Intel 432 computer system. A storage device 220 stores processing programs and data.
Reference numerals 210 and 211 denote data processing devices, which execute programs stored in the storage device 220. This data processor 21
Reference numerals 0 and 211 are the same device, and are locked processor type devices that perform the same processing (execution of instructions) by two units and run while being compared with each other. Reference numerals 230 and 231 denote input / output processing devices, which control data transfer between a peripheral device (not shown) and the storage device 220 in accordance with commands from the data processing devices 210 and 211. A service processor 240 controls the operation modes of the data processing devices 210 and 211 and performs error recovery processing.

FIG. 1 is a block diagram of an embodiment of a system bus interface unit in the data processing devices 210 and 211. Since the data processing devices 210 and 211 operate in comparison with each other, they do not have a check circuit for parity or the like inside. Therefore, in the interface portion to the system bus 200, it is necessary to generate parity for the output address / data and perform parity check for the input data.

In FIG. 1, 100 and 500 are parity check circuits for the above-mentioned input data, PE0 and PE1 are parity error signals, and 101 and 501 are parity generation circuits for output addresses / data. Data out registers (DOR) 150 and 550 are used to temporarily store address or data information to be output to the system bus 200. The data out registers 150 and 550 have a capacity corresponding to 8 bits of data and 1 bit of parity in this embodiment.

130 and 530 are tri-state drivers for data bits, which consist of 8 gates. The tri-state drivers 130 and 530 output the contents of the data portion of the data out registers 150 and 550 to the system bus 200 when the control signals ENDT0 and ENDT1 from the service processor 240 are “1”, and the control signals ENDT0, When ENDT1 is “0”, the output becomes high impedance and does not drive system bus 200.

Reference numerals 131 and 531 denote tri-state drivers for the parity bit, which are composed of one gate. When the control signals ENPT0, ENPT1 from the service processor 240 are “1”, the tri-state drivers 131, 531 output the parity bits of the parity part of the data out registers 150, 550 to the system bus 200 and control signals. When ENPT0 and ENPT1 are “0”, the output becomes high impedance and does not drive the system bus 200.

140 and 540 are receivers for data bits, and are composed of 8 gates. The receivers 140 and 540 receive the contents of the data section from the system bus 200. 141 and 541 are receivers for the parity bit, and system bus
Receives parity bit from 200.

110 and 510 are the contents of the data section of the data out registers 150 and 550 to be output to the system bus 200 and the receiver 14
0,540 is a comparison circuit that compares the contents of the data part of the system bus 200 received.
Data out register 150,550 to be output to 00
2 is a comparison circuit for comparing the parity bit of the above with the parity bit on the system bus 200 received by the receivers 141 and 541.

151 and 551 are data-in registers (DIR). When the data received from the system bus 200 is used internally, the data information is temporarily held in this register. The data-in registers 151 and 551 are registers having a capacity corresponding to 8 bits of data and 1 bit of parity. When the data in the data-in registers 151 and 551 are taken in internally, the parity is used when checked by the parity check circuits 100 and 500.

120 and 520 are AND gates that control the validity and invalidity of the outputs of the data bit comparison circuits 110 and 510, and control them when the control signals CMPD0 and CMPD1 from the service processor 240 are “1” and invalid when they are “0”. .

121 and 521 are AND gates that control the validity and invalidity of the outputs of the parity bit comparison circuits 111 and 511, and are valid when the control signals CMPP0 and CMPP1 from the service processor 240 are "1" and invalid when they are "0". To do.

122 and 522 are OR gates that logically OR the outputs of the AND gates 120 and 520 and the outputs of the AND gates 121 and 521.

190 is a comparison error signal (OR
A signal that indicates that one of the data processing devices has performed an illegal operation by ORing the output of the gate 122) and the comparison error signal of the data processing device 211 (the output of the OR gate 522).
An OR gate that outputs CMPER to the service processor 240.

Each of the above control signals ENDT0, ENDT1, ENPT0, ENPT1, CMPD0, CM
PD1, CMPP0 and CMPP1 are provided from the service processor 240 as described above, and an example of a combination of the above control signals is shown in FIG.

In FIG. 3, Case 1 and Case 2 are examples of setting of each control signal when implementing the method of the present invention, and Case 3 and Case 4 are one of the data processing devices as in the method described in the prior art. 2 is a setting example of each control signal when the system of FIG. 2 implements a method of outputting data and parity as a master and comparing data and parity as a checker, and Case 5 and Case 6 are tests and diagnostics. It is an example of setting each control signal when the lock is released and the data processing devices are operated one by one to execute a test program or the like. Note that Case 5 is the data processing apparatus 210 only mode, and Case 6 is the data processing apparatus 211 only mode. Hereinafter, the operation of the embodiment of the present invention will be described by taking Case 1 as an example.

In FIG. 2, when the control signal ENDT0 from the service processor 240 becomes "1" and the control signal ENDT1 becomes "0", the tri-state driver 130 is enabled and the tri-state driver 530 is disabled. , Data out of the data processor 210
The contents of the data part of the register 150 are output to the system bus 200, and the contents of the data part of the data out register 550 of the data processing device 211 are not output to the system bus 200. Also, the control signal ENPT0 is “0”, the control signal
By setting ENPT1 to “1”, tri-state
Driver 131 is disabled, tri-state driver 531 is enabled, and data processor 210 data out register 150 parity
No bits are output on the system bus 200, and the parity bits of the data out register 550 of the data processing unit 211 will be output on the system bus 200. Further, when the control signal CMPD0 is "0" and the control signal CMPD1 is "1", the AND gate 120 is closed and the AND gate 520 is opened, so that the data output of the data processing device 211 is out. Data part of register 550 (system bus 200
Output of the comparison circuit 510 for comparing the data portion not output to the device) and the data portion fetched from the system bus 200 (the data portion transmitted by the data processing device 210), the control signal CMPP0 becomes "1", When the control signal CMPP1 becomes “0”, the AND gate 121 is opened and the AND gate 521 is closed, so that the parity bit of the data out register 150 of the data processing device 210 (system bus The output of the comparison circuit 110, which compares the parity bit not output to 200) with the parity bit fetched from the system bus 200 (parity bit sent by the data processing device 211), becomes effective. That is, case 1
Then, the data processor 210 transfers the data part to the system bus 2
00 to compare the internal parity bit with the parity bit of the system bus 200 (actually the output of the data processing unit 211), while the data processing unit 211 outputs the parity bit.
The bits will be output to the system bus 200 and the internal data portion will be compared with the parity bits of the system bus 200 (actually the output of the data processor 210).

Therefore, if either one of the data processing devices 210 and 211 performs an illegal operation and the value of the data part of the data out register 150 of the data processing device 210 and the value of the data part of the data processing device 211 are different, A mismatch is detected by the comparison circuit 510 of the processing unit 211, and the mismatch signal is notified to the service processor 240 as a signal CMRER via the AND gate 520, the OR gate 522, and the OR gate 190, and the data is received by the service processor 240. Processor 21
The error recovery processing of 0,211 will be performed.
In this case, the probability that a parity error will occur due to the parity bit output from the data processor 211 on the system bus 200 is such that 1 bit parity is added to 8 bits of data in the embodiment of FIG. So
For example, the probability that the storage device 220 that receives the data on the system bus 200 will process it as correct data can also be halved.

Contrary to case 1, case 2 is a data processing device.
211 shares the data bits on system bus 200,
This is the case where the data processing device 210 shares the parity bit, and the operations of the data processing devices 210 and 211 are opposite to those in case 1 described above.

In the above embodiment, the data in each data processing device is 8 bits, and 1 bit parity is added to the data. However, in general, the present invention handles n × m bit data.
It is applicable to a data processing device of a data format in which 1-bit parity is added for every m bits.

FIG. 4 shows that the present invention is applied to a data processing device 210 ', 211' of a data format in which the data part has 32 bits and 1 bit parity is added for each 8 bits.
(1), 401 (1) is a system bus interface section that handles the first byte data and parity, 400 (2), 401
(2) is the system bus interface that handles the second byte of data and parity, and 400 (3) and 401 (3) are 3
System bus interface section handling byte data and parity, 400 (4) and 401 (4) are system bus interface section handling 4th byte data and parity. It has the same configuration as the system bus interface section shown. Also,
The system bus 200 'is composed of four sets of buses for transmitting data of the first to fourth bytes and parity, and an OR gate 410 corresponding to the OR gate 190 in FIG. A signal from an OR gate corresponding to the OR gate 122 in FIG. 1 in the interface section is added. In such a configuration, the probability that a parity error will occur in the data format on the system bus 200 'is 15/16 when an illegal operation is performed in any of the data processing devices 210' and 211 '. The probability that the receiving side will process it as correct data can be reduced to 1/16.

〔The invention's effect〕

As described above, according to the present invention, in the locked processor system, one is configured to output the data part and the other is configured to output the parity part, and the data part or the parity part that does not output each other is used as the internal data. By comparing with the parity part or the parity part, while achieving an error detection rate of 100% as in the conventional case, when an illegal operation is performed in any of the data processing devices, the parity output is performed on the data output on the bus. An error can be generated, and the probability that the data will be erroneously processed as correct data on the receiving side can be reduced. Therefore, there is an effect that it is possible to increase the possibility of restarting at the time of an illegal operation.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention showing a configuration example of a system bus interface section in a data processing device, and FIG. 2 is a block diagram of an example system including a data processing device to which the present invention is applied. FIG. 3 is a diagram showing an example of setting various control signals, and FIG. 4 is a block diagram of another embodiment of the present invention. In the figure, 100,500 ... Parity check circuit, 101,5
01 ... parity generation circuit, 150,550 ... data out register, 110,111,510,511 ... comparison circuit, 151,551 ... data in register, 120,121,520,521 ... and gate, 122,522,190,410 ... or gate, 130,131,530,531
… Tri-state drivers, 140,141,540,541…
Receiver, 200,200 '... System bus, 210,211,21
0 ', 211' ... Data processing device, 220 ... Storage device, 230, 231
... I / O controller, 240 ... Service processor.

Claims (1)

[Claims] 1. A locked processor system in which two data processing devices are connected to the same bus to execute the same processing at the same time to perform an operation check, wherein each of the two data processing devices has a data processing device. First selecting means for selectively outputting only the data part of the data with parity in the bus to the bus, and second selecting means for selectively outputting only the parity part of the data with parity to the bus, First comparing means for receiving the data part on the bus and comparing the received data part with the data part of the data with parity in the data processing device, and controlling the validity / invalidity of the first comparing means. First control means, second comparing means for receiving the parity part on the bus and comparing the received parity part with the parity part of the data with parity in the data processing device; and the second ratio means. Second control means for controlling the validity and invalidity of the comparing means are provided, and when one data processing device outputs a data part to the bus, the other data processing device outputs a parity part to the bus. The first and second selection means are controlled by each of the data processing devices, and each data processing device compares a data part or a parity part which the data output device does not output to the bus with a data part or a parity part on the bus. The first and second control means are set so that when any one of the data processing devices detects a comparison mismatch, it generates a signal indicating that one of the data processing devices has performed an illegal operation. Locked processor method characterized by being configured.