JPH0831054B2 - History information storage method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of storing history information, and more particularly to a data processing system controlled by a micro program stored in a control memory, and an address of a micro instruction executed and The present invention relates to a history information storage method in a tracer that stores control information as history information.

[Conventional technology]

In data processing systems controlled by microprograms, RAS (Reliability Availability Servicea
time series data such as microinstruction addresses is stored in the tracer memory as part of the eility), and history information stored in the tracer memory is read when a failure occurs or debugging work is performed, and the contents are analyzed to generate a problem. The cause is investigated and measures are taken.

As shown in FIG. 5, the conventional microinstruction sequence trace has a structure in which all executed microinstruction addresses are traced at a uniform rate.

In FIG. 5 showing an example of a conventional microinstruction sequence trace, 1 is a control memory (memory) for storing a microprogram, 2 is this control memory (memory) 1
Is a register that holds a microinstruction address for accessing. Reference numeral 3 is a register for receiving the accessed micro-instruction, which is divided into several fields. Then, the output of each field directly controls an individual circuit (not shown) to execute the micro instruction. The field 31 is a field of a command for controlling the order of microinstructions, and is input to the branch determination circuit 4 via the signal line 103. Here, the above command is roughly divided into an unconditional branch command and a conditional branch command.
If it is an unconditional branch command, the output of the branch judgment circuit 4 becomes the address itself held in the register 2, and if it is a conditional branch command, the output of the branch judgment circuit 4 is held in the register 2. The address is modified by the branch determination condition 104. The register 5 is a register that receives the output of the branch determination circuit 4, and always holds the address of the microinstruction to be actually executed.

The register 2 has its start address set via the signal line 101 at the start of an instruction or an interrupt process.
After that, the next address in the microinstruction word accessed at the start address is set via the signal line 102, and the microprogram is sequentially executed.

The register 6 is a register for holding the write data to the tracer, and the data (microinstruction address) held by the register 5 is set. The register 7 is an address register that holds the address of the tracer memory 8, and +1 is added every time data is stored in the tracer.

All the addresses of the micro-instructions executed by the above-described structure are all cyclically stored in the tracer memory 8 as history information.

[Problems to be Solved by the Invention]

In the conventional microinstruction sequence trace described above, it is originally possible to trace the actual sequence from the history information by leaving only the branch direction when the microinstruction sequence branches as history information. All the micro-instruction addresses were stored in the tracer memory as history information. For this reason, the tracer memory not only requires a large capacity memory, but especially in a microprogram forming a loop, there are many redundant parts in the history contents, and there is a problem that the memory resource is not used to advantage. It was

[Means for solving the problem]

The history information storage method of the present invention is a data processing system controlled by a microprogram stored in a control memory, and a microinstruction branches conditionally in a tracer that stores the address and control information of an executed microinstruction as history information. At that time, it is checked whether the branch direction matches the branch direction at the time of the previous conditional branch, and if they match, it is regarded as the appearance of the loop processing of the microprogram and the number of consecutive matches is counted. A storage means for storing information is provided, and when the count result is two or more, only the count result is stored as history information.

[Action]

In the present invention, unnecessary history information is not stored, and in the trace of a repeating sequence such as a loop, the number of times of repetition is used as history information.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a history information storage system according to the present invention.

In FIG. 1, the same reference numerals as those in FIG. 5 indicate corresponding parts, and 9 is a register for setting the field 31 of the register 3 at the next timing, which holds a micro instruction sequence control command. A decoder 10 detects that the data held in the register 9 is a conditional branch command, and the result is set in the register 11. The output 105 of the decoder 10 is also a set signal of the register (tracer write data register) 6, the register (tracer address register) 7, the counter 12 and the register 13. The register 11 outputs an enable signal indicating the tracer write permission.

And register (tracer write data register)
The microinstruction address held by the register 5 is set in the register 6 only when the register 9 holds the conditional branch command. That is, the branch direction address when the microinstruction sequence branches conditionally is held. The comparison circuit 14 compares the values of the registers 5 and 6, and the comparison result is set in the register 13 by the output 105 (set signal) of the decoder 10. This register (branch direction matching flag register) 13 indicates whether or not the branch direction when the micro instruction sequence branches conditionally is the same as the branch direction at the previous conditional branch. Then, the output of the register (branch direction match flag register) 13 becomes the selection signal 108 of the selector 15, and the selector 15 selects the output of the register (tracer write data register) 6 if the branch direction match flags do not match, and matches. If so, the output of the counter 12 is selected. This counter 12 is the output 10 of the decoder 10.
It is a counter that increments +1 by 5 (set signal). And the output 105 (set signal) of the decoder 10 is turned on.
However, if the comparison result of the comparison circuit 14 does not match, it is always reset to the initial value “001”.

The count value of the counter 12 represents the number of times the microinstruction sequence successively branches in the same direction.

In the decoder 16, the count value of the counter 12 is the initial value "00.
"1" is detected, and its output becomes one of the set conditions of the register 7. The register 7 is an address register that holds the address of the tracer. The output 107 of the decoder 16 and the inverted value 110 of the output 106 of the comparison circuit 14 are ORed with the OR gate 17 and the output 105 of the decoder 10 (set signal). +1 due to the result of ANDing AND with AND gate 18.
Is added. That is, the microinstruction sequence is a conditional branch, and the count value of the counter 12 is the initial value "00".
When it is "1" or the comparison result of the comparison circuit 14 does not match, +1 is added. Further, the overflow of the addition result is ignored and the address becomes cyclic. 19
Is a NAND gate having the output 106 of the comparison circuit 14 as an input.

The registers 5, 6, and 7, the tracer memory 8 and the register 9, the decoder 10, the register 11, and the selector 15 constitute means for storing the branch direction as history information when the microinstruction branches conditionally. , 6,7
And tracer memory 8 and counter 12 and register
13, the comparison circuit 14 and the selector 15 check if the branch direction of the microinstruction branches in the same way as the branch direction of the previous conditional branch, and if they match, count the number of consecutive matches and record the history information. It constitutes a means to store as.

Next, the operation flow will be described by taking the microprogram shown in FIG. 2 as an example.

In FIG. 2, alphabets A, B, C, ... Show microinstruction addresses, and when called as microinstruction A, it means the microinstruction at address A. In this example, conditional branch from B to E, conditional branch from E to G,
A conditional branch is made from K to J three times, and finally a conditional branch is made from K to L. That is, the third indicating the storage result of the tracer memory
It is assumed that the microprograms are executed in the order shown in FIG. In addition, in FIG. 3, (a)
Shows the storage result of the conventional tracer memory, and (b) shows the storage result of the tracer memory of the present invention.

FIG. 4 is a time chart of the operation in the present invention, and shows the time chart of each register when the microprogram of FIG. 2 is executed.

In FIG. 4, (a) shows the register 9 (: microinstruction order control command), and (b).
Is register 5 (: microinstruction execution address), (c)
Is register 6 (: tracer write data), (d) is register 11 (: tracer write enable), (e) is register 13 (: branch direction match flag), (f) is counter.
12, (g) is register 7 (: tracer address),
(H) shows the tracer memory 8.

In the register 9 shown in FIG. 4 (a), "BR" indicates that the microinstruction order control command is a conditional branch command, and the rest is an unconditional branch command. Then, the register 11 indicating the tracer write permission is turned ON at the next timing when the register 9 holds the conditional branch command by the decoder 10, so that T ₄ , T ₅ , T ₉ , T ₁₁ , T ₁₃ shown in FIG. It turns on at the timing of T ₁₅ , and the output 105 (set signal) of the decoder 10 also turns on at the same timing. Output 105 of this decoder 10
By the (set signal), the register (tracer write data register) 6 has an address E at the timing of T ₄ , a G at the timing of T ₅ , and a J at the timing of T ₉ , as shown in FIG. 4 (c). , At the timing of T ₁₁ , J is set at the timing of T ₁₃ , J is set at the timing of T ₁₅ , and L is set at the timing of T ₁₅ , and the values are held at other timings.

The register (branch direction matching flag register) 13 shown in (e) of FIG. 4 has T ₁₀ and T when the register 5 shown in (b) of FIG. 4 and the register 6 shown in (c) of FIG. _Since they match at the timing of ₁₂ , the output 105 (set signal) of the decoder 10 sets the value “0” at the timings T ₄ , T ₅ , T ₉ , and T ₁₅ , and the value “1” at the timings T ₁₁ and T _13. Is set. And, since the value in the other timing is held the value of the register 13 is "1" is the timing of T ₁₁ through T _14.

Further, the counter 12 counts up from 001 to 002 at timing T ₁₁ as shown in FIG. 4 (f) by the output 105 (set signal) of the decoder 10 and the output of the comparison circuit 14, and at timing T ₁₃ . Count up from 002 to 003. And timing T ₄ and timing T ₅ and timing
The initial value 001 is reset at T ₉ and timing T ₁₅ , and the value is held at other timings.

In addition, the register (tracer address register) 7 is
Timing T ₄ shown in FIG. 4 at which the set condition is satisfied,
+1 is added at T ₅ , T ₉ , T ₁₁ , and T ₁₃ . Then, at timing T ₁₃ , the output 105 (set signal) of the decoder 10 is ON, but at this timing T ₁₃ , the result of the comparison circuit 14 does not match, and the count value of the counter 12 at timing T ₁₂ is the initial value “ Since it is not "001", the set condition of the register (tracer address register) 7 is not satisfied and the value is held. Also, the value is held at other timings.

Since the write operation to the tracer memory 8 depends on the enable signal output from the register 11,
Depending on the value of 11, the timing T ₅ , T ₆ , T ₁₀ , shown in FIG.
Writing is performed at T ₁₂ , T ₁₄ , and T ₁₆ . At the timing of T ₅ , since the value of the register (branch direction match flag register) 13 at the timing of T ₄ is “0”, the selector 15 selects the register (tracer write register) 6,
The tracer memory 8 stores the micro instruction address E which is the value of the register 6 at the timing of T ₄ . Similarly, at the timing T ₆ , the micro instruction address G is stored in the next address of the tracer memory 8, and at the timing ₁₀ , the micro instruction address J is further stored in the next address. Then, at timing T ₁₂ , the value of the register (branch direction match flag register) 13 becomes “1” at timing T ₁₁ , so
The selector 15 selects the counter 12, and the value “002” of the counter 12 at the timing T ₁₁ is stored in the next address.

At timing T ₁₄ , the count value “003” is stored in the same manner, but since the register (tracer address register) 7 is held at timing T ₁₃ , the counter value “003” is overwritten on the address stored at timing T _12. To be done.

At timing T ₁₆ , the value of the register (branch direction match flag register) 13 becomes “0” at timing T ₁₅ , so
The selector 15 selects the register (tracer write data register) 6, and the micro instruction address L of the value at the timing T ₁₅ is stored in the next address.

As a result, the data stored in the tracer memory 8 becomes as shown in FIG. 3 (b), which is considerably smaller than the result of the conventional method shown in FIG. 3 (a).

〔The invention's effect〕

As described above, according to the present invention, unnecessary history information is not stored, so that it is possible to reduce the capacity of the tracer memory. Further, in tracing a repeating sequence such as a loop, by setting the number of times of repeating as history information, there is an effect that a redundant portion can be deleted and the tracer memory can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a history information storage system according to the present invention, and FIGS. 2 and 3 are used for explanation of the operation of FIG. 1 and storage of microprogram and tracer memory used for explanation of the present invention. Operation explanatory diagram showing results, No. 4
FIG. 5 is a time chart of the operation in the present invention, and FIG. 5 is a block diagram showing an example of a conventional microinstruction sequence trace. 1 ... control memory, 2,3 ... register, 4 ... branch judgment circuit, 5,6,7 ... register, 8 ... tracer memory, 9 ...
… Register, 10 …… Decoder, 11 …… Register, 12 ……
Counter, 13 ... Register, 14 ... Comparison circuit, 15 ... Selector, 16 ... Decoder, 17 ... OR gate, 18,19 ...
… And gate.

Claims (1)

[Claims] 1. A data processing system controlled by a microprogram stored in a control memory, wherein a tracer stores the address and control information of an executed microinstruction as history information, the branch being performed when the microinstruction branches conditionally. It is checked whether the direction matches the branch direction at the time of the previous conditional branch. If they match, it is regarded as the appearance of the loop processing of the microprogram, the number of consecutive matches is counted, and the count result is stored as history information. The history information storage method is characterized in that when the count result is 2 or more, only the count result is stored as history information.