JPH0831076B2 - Input/Output Processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an input/output processing device, and more particularly to a data transfer method between an input/output processing device and a main storage device for controlling data transfer between the input/output device and a main storage device.

Conventionally, data transfer between a main memory device and an input/output processing device involves, in the case of input transfer, when a certain number of bytes of data received from the input/output device are received, the data is written to memory in units of a certain number of bytes (usually in units of one word), and in the case of output transfer, when data stored in a data buffer is sent to the input/output device and a certain number of bytes become free in the data buffer, the certain number of bytes (usually one word) of data is read from the main memory device and the data buffer is replenished.

In such conventional data transfers, when the data buffer is empty or nearly empty, such as at the start of an output transfer, even if the main memory has the capacity to supply data, a single memory access is not enough to supply data to the data buffer, and memory access must be repeated several times.

Also, in the case of input transfer, several memory accesses are required to write the data clogged in the data buffer to the main storage device, resulting in the disadvantage that data overruns are likely to occur.

Furthermore, in the block transfer method where a few words of data are always read or written in one memory access,
This method has the disadvantage that it takes time to write data from the data buffer to the main memory or read data from the main memory to the data buffer, and there is a high possibility that data transfer will be temporarily interrupted.

OBJECT OF THEINVENTION The present invention has been made to eliminate the drawbacks of the conventional technology as described above, and has an object to provide an input/output processing device that can transfer data according to the transfer speed of the input/output device and can perform efficient memory access when the data transfer starts.

The input/output processing device according to the present invention transfers data between a main storage device and an input/output device, and receives n times (n times) a predetermined number of bytes per access to the main storage device.
an input/output processing device having a data buffer for temporarily holding data transferred in units of data (units of data being 4 or more), the device comprising: a counting means for counting the amount of data held in the data buffer; a determination means for determining the amount of data transfer between the device and the main memory device to be transferred in one access in accordance with the count value of the counting means; and a control means for controlling reading and writing to the main memory device in accordance with the amount of data transfer determined by the determination means.

Next, an embodiment of the present invention will be described with reference to the drawings.

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. 2 is a block diagram showing the system configuration of an embodiment of the present invention. In these figures, an input/output device 3
The common unit 1 is connected to a main memory device 4 connected to a central processing unit 5, and the input/output port units 2-1 to 2-4 are connected to input/output devices 6-1 to 6-4 via an I/O interface 100.
It is connected to 6-4.

Here, the main memory device 4 is capable of reading or writing 4 bytes (1 word), 8 bytes (2 words), 12 bytes (3 words), or 16 bytes (4 words) in one access.

A data transfer control unit 10 in the common unit 1 holds and updates memory addresses and data lengths, controls the memory interface, controls the interface with the input/output port units 2-1 to 2-4, and controls the data transfer sequence.

The data transfer control unit 10 is also connected to a microprocessor (not shown) that controls the input/output processing device 3 via an interface, but this interface is not shown in the figure.

The input data register (IB) 11 receives data from the data buffer 21 of the input/output port unit 2-1 and the other input/output ports 2-2 to 2-4 via the internal data bus 13.
That is, the data to be written to the main memory device 4 is temporarily stored.

An output data register (OB) 12 temporarily stores data read from the main storage device 4, and outputs the data via an internal data bus 14 to a data buffer 21 of the input/output port unit 2-1 and to the other input/output ports 2-2 to 2-4.

The priority decision circuit 15 gives permission to the memory request with the highest priority from the input/output port control unit 20 of the input/output port unit 2-1 and the input/output port control units (not shown) of the other input/output ports 2-2 to 2-4, sends the memory request data from the input/output ports 2-1 to 2-4 to the transfer control unit 10, and
The access bytecodes from 1 to 2-4 and their output data transfer flags are sent to the data transfer control unit 10 via the selection circuits 16 and 17.

The input/output port control unit 20 controls the input/output port unit 2-1, and performs data transfer sequence control and input/output interface control.

The memory pointer (MR) 22 is a 4-bit pointer that controls data transfer with the main memory 4 .

In the case of an output transfer, the value of the memory pointer 22 indicates the top address of the data buffer 21 to which the data read from the main memory 4 should be written. In the case of an input transfer, the value of the memory pointer
The value of 22 holds the leading address of data to be read from the data buffer 21 when data stored in the data buffer 21 is written to the main memory 4, and is updated as the data transfer with the main memory 4 progresses.

The I/O interface pointer (PP) 23 is a 5-bit pointer that controls data transfer on the I/O interface 100 .

In the case of an output transfer, the value of the I/O interface pointer 23 indicates the address of the data to be read from the data buffer 21 when sending the data to the I/O device 6-1, and in the case of an input transfer, the value of the I/O interface pointer 23 indicates the address of the data buffer 21 into which the data received from the I/O device 6-1 should be written, and is updated successively as data transfer with the I/O device 6-1 is executed.

The data buffer 21 is made up of 16 bytes, and receives data from the main memory 4 input via the output data register 12, one byte at a time, via a selection circuit 27, and outputs data to the input/output device 6-1, one byte at a time, via a selection circuit 28.
The data is output to the data out register (DTO) 30 byte by byte.

The data read from the data buffer 21 is output to the input data register 11 via the driver 29 and the internal data bus 13 .

Data buffer stored in the data out register 30
One byte of data from 21 is sent via driver 32 and I/O interface 100 to input/output device 6-1.

Data In Register (DTI) 31 is an I/O interface
100 and the input/output device 6-
1 to 1 byte of data is stored, and the data is written to the data buffer 21 via the selection circuit 27.

A subtractor 24 calculates the difference between the value of the memory pointer 22 and the value of the input/output interface pointer 23, and the calculation result is stored in a differential pointer (DP) 25. The value of the differential pointer 25 is output to the input/output port control unit 20 and a conversion circuit 26.

The input/output port control unit 20 determines whether there is free space in the data buffer 21 or whether there is data stored therein, based on the value of the differential pointer 25 and the value of the most significant bit of the input/output interface pointer 23, and if there is free space or data stored therein, outputs a memory request to the priority determination circuit 15 to request reading or writing of data from or to the main memory device 4, and also outputs an output data transfer flag to the data transfer control unit 10 via the selection circuit 17.

The conversion circuit 26 encodes the value of the differential pointer 25 into 2-bit information, and outputs the information to the data transfer control unit 10 via the selection circuit 16 as an access bytecode.

The data transfer between the main memory 4 and the data buffer 21 is performed in units of an integer multiple of 4 bytes (up to 16 bytes).
The input/output device 6-1 and the data buffer
Data transfer between the 21 and the host computer is performed in units of one byte.

In FIG. 1, only the circuits of the input/output port unit 2-1 are shown, and the other input/output port units 2-2 to 2-
Although the circuits of the input/output port unit 2 are not shown in the figure,
The configurations of -2 to 2-4 are the same as that of the input/output port section 2-1, and their operations are also the same.

3 is a diagram showing the relationship between the value of the differential pointer 25 in FIG. 1, the amount of data in the data buffer 21, and the access byte code. In the diagram, when the value of the differential pointer 25 is "00
When the data is 00", the amount of data in the data buffer 21 is 15 bytes in the case of output transfer, and 1 byte in the case of input transfer.

When the value of the differential pointer 25 is "0001", in the case of output transfer, the amount of data in the data buffer 21 is 14 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 2 bytes.

When the value of the differential pointer 25 is "0010", in the case of output transfer, the amount of data in the data buffer 21 is 13 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 3 bytes.

In the above case, if it is an output transfer, the input/output port control unit 20
If it is an input transfer, the input/output port control unit 20 determines that there is not enough data stored in the data buffer 21, and therefore the output of the memory request is suppressed.

When the value of the differential pointer 25 is "0011", in the case of output transfer, the amount of data in the data buffer 21 is 12 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 4 bytes.

When the value of the differential pointer 25 is "0100", in the case of output transfer, the amount of data in the data buffer 21 is 11 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 5 bytes.

When the value of the differential pointer 25 is "0101", in the case of output transfer, the amount of data in the data buffer 21 is 10 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 6 bytes.

When the value of the differential pointer 25 is "0110", in the case of output transfer, the amount of data in the data buffer 21 is 9 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 7 bytes.

In the above case, if it is an output transfer, the input/output port control unit 20
If the transfer is an input transfer, the input/output port control unit 20 determines that there is enough data stored in the data buffer 21, so a memory request is output and the conversion circuit
From 26, “00” is output as the access bytecode.

When the access bytecode is "00", it indicates reading of 4 bytes of data from the main memory 4 in the case of an output transfer, and indicates writing of 4 bytes of data to the main memory 4 in the case of an input transfer.

When the value of the differential pointer 25 is "0111", in the case of output transfer, the amount of data in the data buffer 21 is 8 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 8 bytes.

When the value of the differential pointer 25 is "1000", in the case of output transfer, the amount of data in the data buffer 21 is 7 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 9 bytes.

When the value of the differential pointer 25 is "1001", in the case of output transfer, the amount of data in the data buffer 21 is 6 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 10 bytes.

When the value of the differential pointer 25 is "1010", in the case of output transfer, the amount of data in the data buffer 21 is 5 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 11 bytes.

In the above case, if it is an output transfer, the input/output port control unit 20
If the transfer is an input transfer, the input/output port control unit 20 determines that there is enough data stored in the data buffer 21, so a memory request is output and the conversion circuit
From 26, “01” is output as the access bytecode.

When the access bytecode is "01", it indicates reading of 8 bytes of data from the main memory 4 in the case of an output transfer, and indicates writing of 8 bytes of data to the main memory 4 in the case of an input transfer.

When the value of the differential pointer 25 is "1011", in the case of output transfer, the amount of data in the data buffer 21 is 4 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 12 bytes.

When the value of the differential pointer 25 is "1100", in the case of output transfer, the amount of data in the data buffer 21 is 3 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 13 bytes.

When the value of the differential pointer 25 is "1101", in the case of output transfer, the amount of data in the data buffer 21 is 2 bytes, and in the case of input transfer, the amount of data in the data buffer 21 is 14 bytes.

When the value of the differential pointer 25 is "1110", in the case of output transfer, the amount of data in the data buffer 21 is 1 byte, and in the case of input transfer, the amount of data in the data buffer 21 is 15 bytes.

In the above case, if it is an output transfer, the input/output port control unit 20
If the transfer is an input transfer, the input/output port control unit 20 determines that there is enough data stored in the data buffer 21, so a memory request is output and the conversion circuit
From 26, “10” is output as the access bytecode.

When the access bytecode is "10", it indicates reading of 12 bytes of data from the main memory 4 in case of an output transfer, and indicates writing of 12 bytes of data to the main memory 4 in case of an input transfer.

When the value of the differential pointer 25 is "1111" and the most significant bit of the input/output interface pointer 23 is "0", the amount of data in the data buffer 21 is 0 bytes in the case of an output transfer, and 16 bytes in the case of an input transfer.
It's a part-time job.

In this case, if it is an output transfer, the input/output port control unit 20 judges that the data buffer 21 is empty, and if it is an input transfer, the input/output port control unit 20 judges that the data buffer 21 is empty.
Since it is determined that data is stored in all of them, a memory request is output and the conversion circuit 26 outputs "11" as the access byte code.

When the access bytecode is "11", it indicates reading of 16 bytes of data from the main memory 4 in case of an output transfer, and indicates writing of 16 bytes of data to the main memory 4 in case of an input transfer.

When the value of the differential pointer 25 is "1111" and the most significant bit of the input/output interface pointer 23 is "1", the amount of data in the data buffer 21 is 16 bytes in the case of an output transfer, and 0 bytes in the case of an input transfer.
It's a part-time job.

In this case, if it is an output transfer, the input/output port control unit 20 determines that all data is stored in the data buffer 21, and if it is an input transfer, the input/output port control unit 20 determines that the data buffer 21 is empty, so that the output of the memory request is suppressed.

The operation of the embodiment of the present invention will be described with reference to FIGS.

When you want to start an output transfer, the data transfer control
The data length and the address (start address of data transfer) on the main memory 4 are set in 10 by a microprogram. Note that the setting means is not shown in FIG.

Then, the input/output port control unit 20 of the input/output port unit 2-1 to which the input/output device 6-1 to be transferred is connected
An output data transfer flag (not shown) in the register 21 is set to "1", and all bits of the memory pointer 22 and the input/output interface pointer 23 are set to "0".

When all bits of the memory pointer 22 and the input/output interface pointer 23 are set to "0", the subtractor 24 calculates the difference between the value of the memory pointer 22 and the value of the input/output interface pointer 23, and the difference pointer 25 is set to "1111".
is set.

Here, the subtractor 24 calculates "the lower 4 bits of the input/output interface pointer 23 + the inverted value of all bits of the memory pointer 22".
The calculation "0" + "1111" is performed, and the result "1111" is set in the difference pointer 25.

The input/output port control unit 20 sets the value of the differential pointer 25 to "1111".
From the most significant bit of the input/output interface pointer 23 being "0", it is determined that the data buffer 21 is empty, and a memory request is output to the priority decision circuit 15 to request the reading of data from the main memory device 4.

At this time, the value "1" of the output data transfer flag is output from the input/output port control unit 20 to the data transfer control unit 10, and the value "1111" of the differential pointer 25 is encoded by the conversion circuit 26, and "11" is output as the access bytecode to the data transfer control unit 10. In this case, the access bytecode is "11", which indicates the reading of 16 bytes of data.

When the priority decision circuit 15 decides that the memory request from the input/output port control unit 20 has the highest priority, it grants permission to the memory request and transmits the memory request from the input/output port control unit 20 to the data transfer control unit 10.
The access bytecode from the input/output port unit 2-1 and its output data transfer flag are transmitted to the data transfer control unit 10 via the selection circuits 16 and 17.

In response to a memory request from the input/output port control unit 20, the data transfer control unit 10 sets the memory request to the main memory device 4 to "1" and accesses the main memory device 4 by outputting a command and address instructing a 16-byte read.

If the main memory device 4 can accept the memory request, it sets the accept to the data transfer control unit 10 to "1".
Thereafter, the first 4 bytes of the 16 bytes of data are sent to the output data register 12, and a reply to the data transfer control unit 10 is set to "1" to indicate receipt of the data.

The input/output processor 3 temporarily stores the data from the main memory device 4 in the output data register 12 and supplies the data to the selection circuit 27 via the internal data bus 14 .

In the case of output transfer, the selection circuit 27 selects and outputs the internal data bus 14 side, so that 4 bytes of data from the main memory 4 are written into the data buffer 21 and the value of the memory pointer 22 is incremented by +4 by the adder 22a.

Four bytes of data are successively output from the main memory 4 every machine cycle, and at the same time that these four bytes of data from the main memory 4 are written to the data buffer 21, the next four bytes of data from the main memory 4 are stored in the output data register 12.

After that, the above-mentioned processing operation is repeated three times, and the main memory device 4
The 16 bytes of data from the first data transfer command are written to the data buffer 21. If an abnormality is detected in the main memory device 4 during this time, the main memory device 4 notifies the data transfer control unit 10 of an error signal.

By the above processing operation, when 16 bytes of data from the main memory 4 are written sequentially into the data buffer 21, the memory pointer 22 is updated from '0' to '4', '8', and 'C'.
Return to '0' again.

When the value of the memory pointer 22 changes from 'C' to '0', the most significant bit of the input/output interface pointer 23 is inverted from "0" to "1", and the value of the difference pointer 25 becomes "11" again.
The result is 11".

The input/output port control unit 20 sets the most significant bit of the input/output interface pointer 23 to "1" and the value of the difference pointer 25 to "111
1", it is determined that data is stored in the entire data buffer 21, and the output of the next memory request is suppressed.

On the other hand, when data is stored in the data buffer 21, the data is read out from the data buffer 21 and the first byte is stored in the data-out register 30, and transfer to the input/output device 6-1 via the I/O interface 100 is started.

Every time data is read from the data buffer 21, the value of the input/output interface pointer 23 is incremented by an adder.
23a adds +1 each time.

When 4 bytes of data are transferred from the data buffer 21 to the input/output device 6-1, the value of the input/output interface pointer 23 becomes "10100", but the value of the memory pointer 22 remains "0", so the value of the difference pointer 25 becomes "0011".
It becomes.

Therefore, the input/output port control unit 20 detects four free bytes in the data buffer 21, and again sends a memory request to the priority decision circuit 15 to replenish those four bytes of data. However, this time the access byte code is "00", indicating a read of the four bytes of data.

Similar to the above-mentioned processing operation, the memory request from the input/output port control unit 20 is sent to the data transfer control unit 10 via the priority judgment circuit 15, and the data transfer control unit 10 outputs a command and address instructing a 4-byte read, thereby accessing the main memory device 4.

As a result, 4 bytes of data are read from the main memory 4 and written into the data buffer 21, and the value of the memory pointer 22 is incremented by +4 by the adder 22a.

As a result, the value of the memory pointer 22 becomes “0100”, the value of the differential pointer 25 becomes “1111” again, and the input/output port control unit 20 again determines that data is stored in all of the data buffer 21, and suppresses the output of the next memory request.

When data transfer is performed as described above, the data length and memory address set in the data transfer control unit 10 are updated to values corresponding to the accessed bytes for each memory access, and the data transfer ends when the data length is exhausted.

In the case of input transfer, similar to the above process, all bits of the memory pointer 22 and the input/output interface pointer 23 are set to "0" and data transfer is started, and data from the input/output device 6-1 to be transferred is supplied to the selection circuit 27 via the receiver 33 and the data-in register 31.

In the case of input transfer, the selection circuit 27 selects and outputs the data register 31 side, so that the first data from the input device 6-1 is written to address 0 of the data buffer 21,
The value of the input/output interface pointer 23 is incremented by +1 by an adder 23a.

When the data from the input/output device 6-1 reaches 4 bytes, the value of the input/output interface pointer 23 becomes "00100".
Therefore, the value of the differential pointer 25 becomes "0011", and the input/output port control unit 20 sends a memory request to the priority determination circuit 15 to write the 4 bytes of data stored in the data buffer 21 to the main memory device 4. At this time, the access byte code to the data transfer control unit 10 becomes "00", which indicates the writing of 4 bytes of data.

Therefore, 4 bytes of data are read from the address of the data buffer 21 indicated by the memory pointer 22 , and the data is temporarily stored in the input data register 11 via the driver 29 and the internal data bus 13 before being written into the main memory device 4 .

Fig. 4 is a block diagram showing the configuration of the main memory device 4 of Fig. 1, and Fig. 5 is a time chart showing the operation of the main memory device 4 shown in Fig. 4. A case where 16 bytes of data sent from the input/output device 6-1 is written to the main memory device 4 will be described with reference to Figs. 4 and 5.

Input/output device 6 sent via input/output processing device 3
When writing 16 bytes of data from -1 to the main memory device 4, when the request bank number from the input/output processor 3 is input to the request decision circuit 40, the request decision circuit 40 judges whether or not the memory request for that request bank number can be accepted.

If the request decision circuit 40 can accept the memory request for the requested bank number, it notifies the control circuit 49 of that fact and sets the requested bank number in the bank number register (BKN) 42 .

At this time, the address, command, write mask, and write data sent from the input/output processor 3 are respectively transferred through the selection circuit 41 to the address register (ADR) 45, the command register (CMDR) 46, and the write mask register (WMK) 47.
and the write data register (WDR) 48.

The control circuit 49 receives a notification from the request determination circuit 40, a request bank number input from the bank number register 42 via the bank number register 43, and a command register
It is determined from the command and write mask from the write mask register 46 and the write mask from the write mask register 47 that a 16-byte write is to be performed on the memory cell 53, and an instruction is given to write the write data to bank 0 of the memory cell 53.

In memory cell 53, an ECC (error detection and correction code) generating circuit 51 adds an ECC bit to the address sent from address register 45 via address register 50 in bank 0 specified by control circuit 49, and the first 4 bytes of write data input via write data register 52 are written.

Next, when the control circuit 49 receives the request bank number input from the bank number register 43 and incremented by +1 by the adder 44, it instructs writing of write data to bank 1 of the memory cell 53, and the next write data is written to bank 1 of the memory cell 53.

In the same manner as the above-mentioned processing operation, when the write data is written to the consecutive banks 2 and 3 of the memory cell 53,
Writing of 16 bytes of data to memory cell 53 is completed.

When the input/output processor 3 reads 16 bytes of data from the main memory 4, the data is read out successively from the successive banks 0 to 3 under the control of the control circuit 49 in the same manner as described above, and the data is sent to the read data register 54 via the selection circuit 54.
The data is set in the read data register 55, and after any errors are corrected by the ECC correction circuit 56, it is sent to the input/output processing device 3 via the read data register 57.

Here, the selection circuit 54 selects data from banks 0 to 3 in accordance with the request bank number supplied from the bank number register 43.

Incidentally, reading from or writing to the main storage device 4 by the central processing unit 5 is also performed in the same manner as the above-mentioned processing operations.

In this way, by determining the amount of data transferred between the data buffer and the main memory 4 in one access, i.e., the number of words read from the main memory 4 or the number of words written to the main memory 4, depending on the amount of remaining data in the data buffer or the number of bytes of free space, it is possible to supply a sufficient amount of data to the data buffer 21 in one memory access during output transfer.

Furthermore, since data can be written to the main memory device 4 in one memory access in accordance with the amount of data stored in the data buffer 21 during input transfer, it is not necessary to repeatedly access the memory and data overruns can be prevented.

Therefore, data transfer can be performed according to the transfer speeds of the input/output devices 6-1 to 6-4 without temporarily interrupting the data transfer, and efficient memory access can be achieved at the start of the data transfer.

Effects of the Invention As described above, according to the present invention, by performing read and write operations on the main memory device based on the amount of data transferred in one access to the main memory device, which is determined according to the amount of data held in the data buffer, data can be transferred according to the transfer speed of the input/output device, thereby achieving efficient memory access when the data transfer begins.

[Brief description of the drawings]

Fig. 1 is a block diagram showing the configuration of one embodiment of the present invention, Fig. 2 is a block diagram showing the system configuration of one embodiment of the present invention, Fig. 3 is a diagram showing the relationship between the value of the differential pointer in Fig. 1 and the data amount of the data buffer and the access bytecode, Fig. 4 is a block diagram showing the configuration of the main memory device in Fig. 1, and Fig. 5 is a time chart showing the operation of the main memory device shown in Fig. 4. Explanation of symbols of main parts 1...Common part 2-1 to 2-4...Input/output port part 3...Input/output processing device 4...Main memory device 6-1 to 6-4...Input/output device 10...Data transfer control part 15...Priority judgment circuit 16, 17, 27, 28...Selection circuit 20...Input/output port control part 21...Data buffer 22...Memory pointer 23...Input/output interface pointer 24...Subtractor 25...Differential pointer 26...Conversion circuit

Claims (1)

[Claims] [Claim 1] An input/output processing device having a data buffer that temporarily holds data transferred between a main memory device and an input/output device and transferred in units of n times a predetermined number of bytes (n is an integer greater than or equal to 4) that is preset for one access to the main memory device, characterized in that the input/output processing device has a counting means that counts the amount of data held in the data buffer, a determination means that determines the amount of data transfer between the main memory device and the main memory device to be transferred in one access in accordance with the counted value of the counting means, and a control means that controls reading and writing to the main memory device in accordance with the data transfer amount determined by the determination means.